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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / d3b70cd87e773bb298eb78fbafed68afaf06b1a2 / . / drivers / clk / imx / clk-imx8mn.c
blob: fb47f86e35e8c1e7258353787892232cfc8e4f14 [file] [log] [blame]
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2018-2019 NXP.
4 */
5
6#include <dt-bindings/clock/imx8mn-clock.h>
Anson Huangf95d5892020-02-12 15:02:23 +0800[diff] [blame]7#include <linux/clk-provider.h>
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]8#include <linux/err.h>
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]9#include <linux/io.h>
10#include <linux/module.h>
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]11#include <linux/of_address.h>
12#include <linux/platform_device.h>
Peng Fandaeb1452019-12-12 02:59:17 +0000[diff] [blame]13#include <linux/slab.h>
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]14#include <linux/types.h>
15
16#include "clk.h"
17
18static u32 share_count_sai2;
19static u32 share_count_sai3;
20static u32 share_count_sai5;
21static u32 share_count_sai6;
22static u32 share_count_sai7;
23static u32 share_count_disp;
24static u32 share_count_pdm;
25static u32 share_count_nand;
26
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]27static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
28static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
29static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
30static const char * const video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", };
31static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
32static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
33static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
34static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]35static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
36
37static const char * const imx8mn_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m",
38 "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
39 "audio_pll1_out", "sys_pll3_out", };
40
41static const char * const imx8mn_gpu_core_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
42 "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
43 "video_pll1_out", "audio_pll2_out", };
44
45static const char * const imx8mn_gpu_shader_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
46 "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
47 "video_pll1_out", "audio_pll2_out", };
48
49static const char * const imx8mn_main_axi_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll1_800m",
50 "sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out",
51 "video_pll1_out", "sys_pll1_100m",};
52
53static const char * const imx8mn_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
54 "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out",
55 "video_pll1_out", "sys_pll3_out", };
56
57static const char * const imx8mn_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
58 "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out",
59 "sys_pll2_250m", "audio_pll1_out", };
60
61static const char * const imx8mn_disp_axi_sels[] = {"osc_24m", "sys_pll2_1000m", "sys_pll1_800m",
62 "sys_pll3_out", "sys_pll1_40m", "audio_pll2_out",
63 "clk_ext1", "clk_ext4", };
64
65static const char * const imx8mn_disp_apb_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll1_800m",
Leonard Crestezb3d08a4b2019-08-13 20:05:30 +0300[diff] [blame]66 "sys_pll3_out", "sys_pll1_40m", "audio_pll2_out",
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]67 "clk_ext1", "clk_ext3", };
68
69static const char * const imx8mn_usb_bus_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m",
70 "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
71 "clk_ext4", "audio_pll2_out", };
72
73static const char * const imx8mn_gpu_axi_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out",
74 "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
75 "video_pll1_out", "audio_pll2_out", };
76
77static const char * const imx8mn_gpu_ahb_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out",
78 "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
79 "video_pll1_out", "audio_pll2_out", };
80
81static const char * const imx8mn_noc_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out",
82 "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out",
83 "video_pll1_out", "audio_pll2_out", };
84
85static const char * const imx8mn_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m",
86 "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out",
87 "audio_pll1_out", "video_pll1_out", };
88
89static const char * const imx8mn_audio_ahb_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m",
90 "sys_pll2_1000m", "sys_pll2_166m", "sys_pll3_out",
91 "audio_pll1_out", "video_pll1_out", };
92
93static const char * const imx8mn_dram_alt_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll1_100m",
94 "sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out",
95 "audio_pll1_out", "sys_pll1_266m", };
96
97static const char * const imx8mn_dram_apb_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
98 "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
99 "sys_pll2_250m", "audio_pll2_out", };
100
101static const char * const imx8mn_disp_pixel_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out",
102 "audio_pll1_out", "sys_pll1_800m", "sys_pll2_1000m",
103 "sys_pll3_out", "clk_ext4", };
104
105static const char * const imx8mn_sai2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
106 "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
107 "clk_ext3", "clk_ext4", };
108
109static const char * const imx8mn_sai3_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
110 "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
111 "clk_ext3", "clk_ext4", };
112
113static const char * const imx8mn_sai5_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
114 "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
115 "clk_ext2", "clk_ext3", };
116
117static const char * const imx8mn_sai6_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
118 "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
119 "clk_ext3", "clk_ext4", };
120
121static const char * const imx8mn_sai7_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
122 "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
123 "clk_ext3", "clk_ext4", };
124
125static const char * const imx8mn_spdif1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
126 "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
127 "clk_ext2", "clk_ext3", };
128
129static const char * const imx8mn_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m",
130 "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
131 "video_pll1_out", "clk_ext4", };
132
133static const char * const imx8mn_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
134 "clk_ext1", "clk_ext2", "clk_ext3",
135 "clk_ext4", "video_pll1_out", };
136
137static const char * const imx8mn_enet_phy_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m",
138 "sys_pll2_200m", "sys_pll2_500m", "video_pll1_out",
139 "audio_pll2_out", };
140
141static const char * const imx8mn_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out",
142 "sys_pll1_400m", "audio_pll2_out", "sys_pll3_out",
143 "sys_pll2_250m", "video_pll1_out", };
144
Leonard Crestezb3d08a4b2019-08-13 20:05:30 +0300[diff] [blame]145static const char * const imx8mn_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m",
146 "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m",
147 "sys_pll3_out", "sys_pll1_100m", };
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]148
149static const char * const imx8mn_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
150 "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
151 "audio_pll2_out", "sys_pll1_100m", };
152
153static const char * const imx8mn_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
154 "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
155 "audio_pll2_out", "sys_pll1_100m", };
156
157static const char * const imx8mn_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
158 "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
159 "audio_pll2_out", "sys_pll1_133m", };
160
161static const char * const imx8mn_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
162 "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
163 "audio_pll2_out", "sys_pll1_133m", };
164
165static const char * const imx8mn_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
166 "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
167 "audio_pll2_out", "sys_pll1_133m", };
168
169static const char * const imx8mn_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
170 "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
171 "audio_pll2_out", "sys_pll1_133m", };
172
173static const char * const imx8mn_uart1_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
174 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
175 "clk_ext4", "audio_pll2_out", };
176
177static const char * const imx8mn_uart2_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
178 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
179 "clk_ext3", "audio_pll2_out", };
180
181static const char * const imx8mn_uart3_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
182 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
183 "clk_ext4", "audio_pll2_out", };
184
185static const char * const imx8mn_uart4_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
186 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
187 "clk_ext3", "audio_pll2_out", };
188
189static const char * const imx8mn_usb_core_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m",
190 "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
191 "clk_ext3", "audio_pll2_out", };
192
193static const char * const imx8mn_usb_phy_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m",
194 "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
195 "clk_ext3", "audio_pll2_out", };
196
Leonard Crestezbe378b62019-08-13 20:05:31 +0300[diff] [blame]197static const char * const imx8mn_gic_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
198 "sys_pll2_100m", "sys_pll1_800m", "clk_ext2",
199 "clk_ext4", "audio_pll2_out" };
200
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]201static const char * const imx8mn_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
202 "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
203 "sys_pll2_250m", "audio_pll2_out", };
204
205static const char * const imx8mn_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
206 "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
207 "sys_pll2_250m", "audio_pll2_out", };
208
209static const char * const imx8mn_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
210 "sys_pll1_40m", "sys_pll3_out", "clk_ext1",
211 "sys_pll1_80m", "video_pll1_out", };
212
213static const char * const imx8mn_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
214 "sys_pll1_40m", "sys_pll3_out", "clk_ext1",
215 "sys_pll1_80m", "video_pll1_out", };
216
217static const char * const imx8mn_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
Leonard Crestezb3d08a4b2019-08-13 20:05:30 +0300[diff] [blame]218 "sys_pll1_40m", "sys_pll3_out", "clk_ext2",
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]219 "sys_pll1_80m", "video_pll1_out", };
220
221static const char * const imx8mn_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
222 "sys_pll1_40m", "sys_pll3_out", "clk_ext2",
223 "sys_pll1_80m", "video_pll1_out", };
224
225static const char * const imx8mn_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m",
226 "vpu_pll_out", "sys_pll2_125m", "sys_pll3_out",
227 "sys_pll1_80m", "sys_pll2_166m", };
228
229static const char * const imx8mn_wrclk_sels[] = {"osc_24m", "sys_pll1_40m", "vpu_pll_out",
230 "sys_pll3_out", "sys_pll2_200m", "sys_pll1_266m",
231 "sys_pll2_500m", "sys_pll1_100m", };
232
233static const char * const imx8mn_dsi_core_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m",
234 "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
235 "audio_pll2_out", "video_pll1_out", };
236
237static const char * const imx8mn_dsi_phy_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_100m",
238 "sys_pll1_800m", "sys_pll2_1000m", "clk_ext2",
239 "audio_pll2_out", "video_pll1_out", };
240
241static const char * const imx8mn_dsi_dbi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_100m",
242 "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
243 "audio_pll2_out", "video_pll1_out", };
244
245static const char * const imx8mn_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
246 "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
Leonard Crestezb3d08a4b2019-08-13 20:05:30 +0300[diff] [blame]247 "audio_pll2_out", "sys_pll1_100m", };
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]248
249static const char * const imx8mn_camera_pixel_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m",
250 "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
251 "audio_pll2_out", "video_pll1_out", };
252
253static const char * const imx8mn_csi1_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m",
254 "sys_pll1_800m", "sys_pll2_1000m", "clk_ext2",
255 "audio_pll2_out", "video_pll1_out", };
256
257static const char * const imx8mn_csi2_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m",
258 "sys_pll1_800m", "sys_pll2_1000m", "clk_ext2",
259 "audio_pll2_out", "video_pll1_out", };
260
261static const char * const imx8mn_csi2_esc_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m",
262 "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
263 "clk_ext3", "audio_pll2_out", };
264
265static const char * const imx8mn_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
266 "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
267 "sys_pll2_250m", "audio_pll2_out", };
268
269static const char * const imx8mn_pdm_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
270 "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
271 "clk_ext3", "audio_pll2_out", };
272
273static const char * const imx8mn_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
274
275static const char * const imx8mn_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "osc_27m",
Leonard Crestezb3d08a4b2019-08-13 20:05:30 +0300[diff] [blame]276 "sys_pll1_200m", "audio_pll2_out", "vpu_pll",
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]277 "sys_pll1_80m", };
278static const char * const imx8mn_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m",
279 "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out",
280 "video_pll1_out", "osc_32k", };
281
Peng Fandaeb1452019-12-12 02:59:17 +0000[diff] [blame]282static struct clk_hw_onecell_data *clk_hw_data;
283static struct clk_hw **hws;
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]284
Peng Fandaeb1452019-12-12 02:59:17 +0000[diff] [blame]285static const int uart_clk_ids[] = {
286 IMX8MN_CLK_UART1_ROOT,
287 IMX8MN_CLK_UART2_ROOT,
288 IMX8MN_CLK_UART3_ROOT,
289 IMX8MN_CLK_UART4_ROOT,
Anson Huangf7988ba2019-07-24 15:50:17 +0800[diff] [blame]290};
Peng Fandaeb1452019-12-12 02:59:17 +0000[diff] [blame]291static struct clk **uart_hws[ARRAY_SIZE(uart_clk_ids) + 1];
Anson Huangf7988ba2019-07-24 15:50:17 +0800[diff] [blame]292
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]293static int imx8mn_clocks_probe(struct platform_device *pdev)
294{
295 struct device *dev = &pdev->dev;
296 struct device_node *np = dev->of_node;
297 void __iomem *base;
Peng Fandaeb1452019-12-12 02:59:17 +0000[diff] [blame]298 int ret, i;
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]299
Peng Fandaeb1452019-12-12 02:59:17 +0000[diff] [blame]300 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
301 IMX8MN_CLK_END), GFP_KERNEL);
302 if (WARN_ON(!clk_hw_data))
303 return -ENOMEM;
304
305 clk_hw_data->num = IMX8MN_CLK_END;
306 hws = clk_hw_data->hws;
307
308 hws[IMX8MN_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
309 hws[IMX8MN_CLK_24M] = imx_obtain_fixed_clk_hw(np, "osc_24m");
310 hws[IMX8MN_CLK_32K] = imx_obtain_fixed_clk_hw(np, "osc_32k");
311 hws[IMX8MN_CLK_EXT1] = imx_obtain_fixed_clk_hw(np, "clk_ext1");
312 hws[IMX8MN_CLK_EXT2] = imx_obtain_fixed_clk_hw(np, "clk_ext2");
313 hws[IMX8MN_CLK_EXT3] = imx_obtain_fixed_clk_hw(np, "clk_ext3");
314 hws[IMX8MN_CLK_EXT4] = imx_obtain_fixed_clk_hw(np, "clk_ext4");
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]315
316 np = of_find_compatible_node(NULL, NULL, "fsl,imx8mn-anatop");
317 base = of_iomap(np, 0);
Anson Huangd93171b2020-02-12 19:57:36 +0800[diff] [blame]318 of_node_put(np);
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]319 if (WARN_ON(!base)) {
320 ret = -ENOMEM;
Peng Fandaeb1452019-12-12 02:59:17 +0000[diff] [blame]321 goto unregister_hws;
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]322 }
323
Peng Fandaeb1452019-12-12 02:59:17 +0000[diff] [blame]324 hws[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
325 hws[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
326 hws[IMX8MN_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
327 hws[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
328 hws[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
329 hws[IMX8MN_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
330 hws[IMX8MN_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
331 hws[IMX8MN_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]332
Peng Fandaeb1452019-12-12 02:59:17 +0000[diff] [blame]333 hws[IMX8MN_AUDIO_PLL1] = imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx_1443x_pll);
334 hws[IMX8MN_AUDIO_PLL2] = imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx_1443x_pll);
335 hws[IMX8MN_VIDEO_PLL1] = imx_clk_hw_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx_1443x_pll);
336 hws[IMX8MN_DRAM_PLL] = imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_dram_pll);
337 hws[IMX8MN_GPU_PLL] = imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx_1416x_pll);
338 hws[IMX8MN_VPU_PLL] = imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx_1416x_pll);
339 hws[IMX8MN_ARM_PLL] = imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx_1416x_pll);
340 hws[IMX8MN_SYS_PLL1] = imx_clk_hw_fixed("sys_pll1", 800000000);
341 hws[IMX8MN_SYS_PLL2] = imx_clk_hw_fixed("sys_pll2", 1000000000);
342 hws[IMX8MN_SYS_PLL3] = imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx_1416x_pll);
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]343
344 /* PLL bypass out */
Peng Fandaeb1452019-12-12 02:59:17 +0000[diff] [blame]345 hws[IMX8MN_AUDIO_PLL1_BYPASS] = imx_clk_hw_mux_flags("audio_pll1_bypass", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT);
346 hws[IMX8MN_AUDIO_PLL2_BYPASS] = imx_clk_hw_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT);
347 hws[IMX8MN_VIDEO_PLL1_BYPASS] = imx_clk_hw_mux_flags("video_pll1_bypass", base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT);
348 hws[IMX8MN_DRAM_PLL_BYPASS] = imx_clk_hw_mux_flags("dram_pll_bypass", base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT);
349 hws[IMX8MN_GPU_PLL_BYPASS] = imx_clk_hw_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
350 hws[IMX8MN_VPU_PLL_BYPASS] = imx_clk_hw_mux_flags("vpu_pll_bypass", base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
351 hws[IMX8MN_ARM_PLL_BYPASS] = imx_clk_hw_mux_flags("arm_pll_bypass", base + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT);
352 hws[IMX8MN_SYS_PLL3_BYPASS] = imx_clk_hw_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT);
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]353
354 /* PLL out gate */
Peng Fandaeb1452019-12-12 02:59:17 +0000[diff] [blame]355 hws[IMX8MN_AUDIO_PLL1_OUT] = imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", base, 13);
356 hws[IMX8MN_AUDIO_PLL2_OUT] = imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x14, 13);
357 hws[IMX8MN_VIDEO_PLL1_OUT] = imx_clk_hw_gate("video_pll1_out", "video_pll1_bypass", base + 0x28, 13);
358 hws[IMX8MN_DRAM_PLL_OUT] = imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13);
359 hws[IMX8MN_GPU_PLL_OUT] = imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 11);
360 hws[IMX8MN_VPU_PLL_OUT] = imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x74, 11);
361 hws[IMX8MN_ARM_PLL_OUT] = imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11);
362 hws[IMX8MN_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11);
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]363
Leonard Cresteze8688fe2019-10-16 11:57:40 +0000[diff] [blame]364 /* SYS PLL1 fixed output */
Peng Fandaeb1452019-12-12 02:59:17 +0000[diff] [blame]365 hws[IMX8MN_SYS_PLL1_40M_CG] = imx_clk_hw_gate("sys_pll1_40m_cg", "sys_pll1", base + 0x94, 27);
366 hws[IMX8MN_SYS_PLL1_80M_CG] = imx_clk_hw_gate("sys_pll1_80m_cg", "sys_pll1", base + 0x94, 25);
367 hws[IMX8MN_SYS_PLL1_100M_CG] = imx_clk_hw_gate("sys_pll1_100m_cg", "sys_pll1", base + 0x94, 23);
368 hws[IMX8MN_SYS_PLL1_133M_CG] = imx_clk_hw_gate("sys_pll1_133m_cg", "sys_pll1", base + 0x94, 21);
369 hws[IMX8MN_SYS_PLL1_160M_CG] = imx_clk_hw_gate("sys_pll1_160m_cg", "sys_pll1", base + 0x94, 19);
370 hws[IMX8MN_SYS_PLL1_200M_CG] = imx_clk_hw_gate("sys_pll1_200m_cg", "sys_pll1", base + 0x94, 17);
371 hws[IMX8MN_SYS_PLL1_266M_CG] = imx_clk_hw_gate("sys_pll1_266m_cg", "sys_pll1", base + 0x94, 15);
372 hws[IMX8MN_SYS_PLL1_400M_CG] = imx_clk_hw_gate("sys_pll1_400m_cg", "sys_pll1", base + 0x94, 13);
373 hws[IMX8MN_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out", "sys_pll1", base + 0x94, 11);
Leonard Cresteze8688fe2019-10-16 11:57:40 +0000[diff] [blame]374
Peng Fandaeb1452019-12-12 02:59:17 +0000[diff] [blame]375 hws[IMX8MN_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_40m_cg", 1, 20);
376 hws[IMX8MN_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_80m_cg", 1, 10);
377 hws[IMX8MN_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_100m_cg", 1, 8);
378 hws[IMX8MN_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_133m_cg", 1, 6);
379 hws[IMX8MN_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_160m_cg", 1, 5);
380 hws[IMX8MN_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_200m_cg", 1, 4);
381 hws[IMX8MN_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_266m_cg", 1, 3);
382 hws[IMX8MN_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_400m_cg", 1, 2);
383 hws[IMX8MN_SYS_PLL1_800M] = imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1);
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]384
Leonard Cresteze8688fe2019-10-16 11:57:40 +0000[diff] [blame]385 /* SYS PLL2 fixed output */
Peng Fandaeb1452019-12-12 02:59:17 +0000[diff] [blame]386 hws[IMX8MN_SYS_PLL2_50M_CG] = imx_clk_hw_gate("sys_pll2_50m_cg", "sys_pll2", base + 0x104, 27);
387 hws[IMX8MN_SYS_PLL2_100M_CG] = imx_clk_hw_gate("sys_pll2_100m_cg", "sys_pll2", base + 0x104, 25);
388 hws[IMX8MN_SYS_PLL2_125M_CG] = imx_clk_hw_gate("sys_pll2_125m_cg", "sys_pll2", base + 0x104, 23);
389 hws[IMX8MN_SYS_PLL2_166M_CG] = imx_clk_hw_gate("sys_pll2_166m_cg", "sys_pll2", base + 0x104, 21);
390 hws[IMX8MN_SYS_PLL2_200M_CG] = imx_clk_hw_gate("sys_pll2_200m_cg", "sys_pll2", base + 0x104, 19);
391 hws[IMX8MN_SYS_PLL2_250M_CG] = imx_clk_hw_gate("sys_pll2_250m_cg", "sys_pll2", base + 0x104, 17);
392 hws[IMX8MN_SYS_PLL2_333M_CG] = imx_clk_hw_gate("sys_pll2_333m_cg", "sys_pll2", base + 0x104, 15);
393 hws[IMX8MN_SYS_PLL2_500M_CG] = imx_clk_hw_gate("sys_pll2_500m_cg", "sys_pll2", base + 0x104, 13);
394 hws[IMX8MN_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2", base + 0x104, 11);
Leonard Cresteze8688fe2019-10-16 11:57:40 +0000[diff] [blame]395
Peng Fandaeb1452019-12-12 02:59:17 +0000[diff] [blame]396 hws[IMX8MN_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_50m_cg", 1, 20);
397 hws[IMX8MN_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_100m_cg", 1, 10);
398 hws[IMX8MN_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_125m_cg", 1, 8);
399 hws[IMX8MN_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_166m_cg", 1, 6);
400 hws[IMX8MN_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_200m_cg", 1, 5);
401 hws[IMX8MN_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_250m_cg", 1, 4);
402 hws[IMX8MN_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_333m_cg", 1, 3);
403 hws[IMX8MN_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
404 hws[IMX8MN_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]405
406 np = dev->of_node;
407 base = devm_platform_ioremap_resource(pdev, 0);
408 if (WARN_ON(IS_ERR(base))) {
409 ret = PTR_ERR(base);
Peng Fandaeb1452019-12-12 02:59:17 +0000[diff] [blame]410 goto unregister_hws;
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]411 }
412
413 /* CORE */
Peng Fandaeb1452019-12-12 02:59:17 +0000[diff] [blame]414 hws[IMX8MN_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mn_a53_sels, ARRAY_SIZE(imx8mn_a53_sels));
Peng Fandaeb1452019-12-12 02:59:17 +0000[diff] [blame]415 hws[IMX8MN_CLK_A53_CG] = imx_clk_hw_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28);
Peng Fandaeb1452019-12-12 02:59:17 +0000[diff] [blame]416 hws[IMX8MN_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3);
Peng Fan33db2ce2020-01-28 05:28:50 +0000[diff] [blame]417
418 hws[IMX8MN_CLK_GPU_CORE] = imx8m_clk_hw_composite_core("gpu_core", imx8mn_gpu_core_sels, base + 0x8180);
419 hws[IMX8MN_CLK_GPU_SHADER] = imx8m_clk_hw_composite_core("gpu_shader", imx8mn_gpu_shader_sels, base + 0x8200);
420
421 hws[IMX8MN_CLK_GPU_CORE_SRC] = hws[IMX8MN_CLK_GPU_CORE];
422 hws[IMX8MN_CLK_GPU_CORE_CG] = hws[IMX8MN_CLK_GPU_CORE];
423 hws[IMX8MN_CLK_GPU_CORE_DIV] = hws[IMX8MN_CLK_GPU_CORE];
424 hws[IMX8MN_CLK_GPU_SHADER_SRC] = hws[IMX8MN_CLK_GPU_SHADER];
425 hws[IMX8MN_CLK_GPU_SHADER_CG] = hws[IMX8MN_CLK_GPU_SHADER];
426 hws[IMX8MN_CLK_GPU_SHADER_DIV] = hws[IMX8MN_CLK_GPU_SHADER];
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]427
428 /* BUS */
Peng Fandaeb1452019-12-12 02:59:17 +0000[diff] [blame]429 hws[IMX8MN_CLK_MAIN_AXI] = imx8m_clk_hw_composite_critical("main_axi", imx8mn_main_axi_sels, base + 0x8800);
430 hws[IMX8MN_CLK_ENET_AXI] = imx8m_clk_hw_composite("enet_axi", imx8mn_enet_axi_sels, base + 0x8880);
431 hws[IMX8MN_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite("nand_usdhc_bus", imx8mn_nand_usdhc_sels, base + 0x8900);
432 hws[IMX8MN_CLK_DISP_AXI] = imx8m_clk_hw_composite("disp_axi", imx8mn_disp_axi_sels, base + 0x8a00);
433 hws[IMX8MN_CLK_DISP_APB] = imx8m_clk_hw_composite("disp_apb", imx8mn_disp_apb_sels, base + 0x8a80);
434 hws[IMX8MN_CLK_USB_BUS] = imx8m_clk_hw_composite("usb_bus", imx8mn_usb_bus_sels, base + 0x8b80);
435 hws[IMX8MN_CLK_GPU_AXI] = imx8m_clk_hw_composite("gpu_axi", imx8mn_gpu_axi_sels, base + 0x8c00);
436 hws[IMX8MN_CLK_GPU_AHB] = imx8m_clk_hw_composite("gpu_ahb", imx8mn_gpu_ahb_sels, base + 0x8c80);
437 hws[IMX8MN_CLK_NOC] = imx8m_clk_hw_composite_critical("noc", imx8mn_noc_sels, base + 0x8d00);
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]438
Peng Fandaeb1452019-12-12 02:59:17 +0000[diff] [blame]439 hws[IMX8MN_CLK_AHB] = imx8m_clk_hw_composite_critical("ahb", imx8mn_ahb_sels, base + 0x9000);
440 hws[IMX8MN_CLK_AUDIO_AHB] = imx8m_clk_hw_composite("audio_ahb", imx8mn_audio_ahb_sels, base + 0x9100);
441 hws[IMX8MN_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb", base + 0x9080, 0, 1);
442 hws[IMX8MN_CLK_IPG_AUDIO_ROOT] = imx_clk_hw_divider2("ipg_audio_root", "audio_ahb", base + 0x9180, 0, 1);
443 hws[IMX8MN_CLK_DRAM_CORE] = imx_clk_hw_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mn_dram_core_sels, ARRAY_SIZE(imx8mn_dram_core_sels), CLK_IS_CRITICAL);
Leonard Crestezd9ea9ca2019-11-22 23:45:00 +0200[diff] [blame]444
445 /*
446 * DRAM clocks are manipulated from TF-A outside clock framework.
447 * Mark with GET_RATE_NOCACHE to always read div value from hardware
448 */
Peng Fandaeb1452019-12-12 02:59:17 +0000[diff] [blame]449 hws[IMX8MN_CLK_DRAM_ALT] = __imx8m_clk_hw_composite("dram_alt", imx8mn_dram_alt_sels, base + 0xa000, CLK_GET_RATE_NOCACHE);
450 hws[IMX8MN_CLK_DRAM_APB] = __imx8m_clk_hw_composite("dram_apb", imx8mn_dram_apb_sels, base + 0xa080, CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE);
Leonard Crestezd9ea9ca2019-11-22 23:45:00 +0200[diff] [blame]451
Peng Fandaeb1452019-12-12 02:59:17 +0000[diff] [blame]452 hws[IMX8MN_CLK_DISP_PIXEL] = imx8m_clk_hw_composite("disp_pixel", imx8mn_disp_pixel_sels, base + 0xa500);
453 hws[IMX8MN_CLK_SAI2] = imx8m_clk_hw_composite("sai2", imx8mn_sai2_sels, base + 0xa600);
454 hws[IMX8MN_CLK_SAI3] = imx8m_clk_hw_composite("sai3", imx8mn_sai3_sels, base + 0xa680);
455 hws[IMX8MN_CLK_SAI5] = imx8m_clk_hw_composite("sai5", imx8mn_sai5_sels, base + 0xa780);
456 hws[IMX8MN_CLK_SAI6] = imx8m_clk_hw_composite("sai6", imx8mn_sai6_sels, base + 0xa800);
457 hws[IMX8MN_CLK_SPDIF1] = imx8m_clk_hw_composite("spdif1", imx8mn_spdif1_sels, base + 0xa880);
458 hws[IMX8MN_CLK_ENET_REF] = imx8m_clk_hw_composite("enet_ref", imx8mn_enet_ref_sels, base + 0xa980);
459 hws[IMX8MN_CLK_ENET_TIMER] = imx8m_clk_hw_composite("enet_timer", imx8mn_enet_timer_sels, base + 0xaa00);
460 hws[IMX8MN_CLK_ENET_PHY_REF] = imx8m_clk_hw_composite("enet_phy", imx8mn_enet_phy_sels, base + 0xaa80);
461 hws[IMX8MN_CLK_NAND] = imx8m_clk_hw_composite("nand", imx8mn_nand_sels, base + 0xab00);
462 hws[IMX8MN_CLK_QSPI] = imx8m_clk_hw_composite("qspi", imx8mn_qspi_sels, base + 0xab80);
463 hws[IMX8MN_CLK_USDHC1] = imx8m_clk_hw_composite("usdhc1", imx8mn_usdhc1_sels, base + 0xac00);
464 hws[IMX8MN_CLK_USDHC2] = imx8m_clk_hw_composite("usdhc2", imx8mn_usdhc2_sels, base + 0xac80);
465 hws[IMX8MN_CLK_I2C1] = imx8m_clk_hw_composite("i2c1", imx8mn_i2c1_sels, base + 0xad00);
466 hws[IMX8MN_CLK_I2C2] = imx8m_clk_hw_composite("i2c2", imx8mn_i2c2_sels, base + 0xad80);
467 hws[IMX8MN_CLK_I2C3] = imx8m_clk_hw_composite("i2c3", imx8mn_i2c3_sels, base + 0xae00);
468 hws[IMX8MN_CLK_I2C4] = imx8m_clk_hw_composite("i2c4", imx8mn_i2c4_sels, base + 0xae80);
469 hws[IMX8MN_CLK_UART1] = imx8m_clk_hw_composite("uart1", imx8mn_uart1_sels, base + 0xaf00);
470 hws[IMX8MN_CLK_UART2] = imx8m_clk_hw_composite("uart2", imx8mn_uart2_sels, base + 0xaf80);
471 hws[IMX8MN_CLK_UART3] = imx8m_clk_hw_composite("uart3", imx8mn_uart3_sels, base + 0xb000);
472 hws[IMX8MN_CLK_UART4] = imx8m_clk_hw_composite("uart4", imx8mn_uart4_sels, base + 0xb080);
473 hws[IMX8MN_CLK_USB_CORE_REF] = imx8m_clk_hw_composite("usb_core_ref", imx8mn_usb_core_sels, base + 0xb100);
474 hws[IMX8MN_CLK_USB_PHY_REF] = imx8m_clk_hw_composite("usb_phy_ref", imx8mn_usb_phy_sels, base + 0xb180);
475 hws[IMX8MN_CLK_GIC] = imx8m_clk_hw_composite_critical("gic", imx8mn_gic_sels, base + 0xb200);
476 hws[IMX8MN_CLK_ECSPI1] = imx8m_clk_hw_composite("ecspi1", imx8mn_ecspi1_sels, base + 0xb280);
477 hws[IMX8MN_CLK_ECSPI2] = imx8m_clk_hw_composite("ecspi2", imx8mn_ecspi2_sels, base + 0xb300);
478 hws[IMX8MN_CLK_PWM1] = imx8m_clk_hw_composite("pwm1", imx8mn_pwm1_sels, base + 0xb380);
479 hws[IMX8MN_CLK_PWM2] = imx8m_clk_hw_composite("pwm2", imx8mn_pwm2_sels, base + 0xb400);
480 hws[IMX8MN_CLK_PWM3] = imx8m_clk_hw_composite("pwm3", imx8mn_pwm3_sels, base + 0xb480);
481 hws[IMX8MN_CLK_PWM4] = imx8m_clk_hw_composite("pwm4", imx8mn_pwm4_sels, base + 0xb500);
482 hws[IMX8MN_CLK_WDOG] = imx8m_clk_hw_composite("wdog", imx8mn_wdog_sels, base + 0xb900);
483 hws[IMX8MN_CLK_WRCLK] = imx8m_clk_hw_composite("wrclk", imx8mn_wrclk_sels, base + 0xb980);
484 hws[IMX8MN_CLK_CLKO1] = imx8m_clk_hw_composite("clko1", imx8mn_clko1_sels, base + 0xba00);
485 hws[IMX8MN_CLK_CLKO2] = imx8m_clk_hw_composite("clko2", imx8mn_clko2_sels, base + 0xba80);
486 hws[IMX8MN_CLK_DSI_CORE] = imx8m_clk_hw_composite("dsi_core", imx8mn_dsi_core_sels, base + 0xbb00);
487 hws[IMX8MN_CLK_DSI_PHY_REF] = imx8m_clk_hw_composite("dsi_phy_ref", imx8mn_dsi_phy_sels, base + 0xbb80);
488 hws[IMX8MN_CLK_DSI_DBI] = imx8m_clk_hw_composite("dsi_dbi", imx8mn_dsi_dbi_sels, base + 0xbc00);
489 hws[IMX8MN_CLK_USDHC3] = imx8m_clk_hw_composite("usdhc3", imx8mn_usdhc3_sels, base + 0xbc80);
490 hws[IMX8MN_CLK_CAMERA_PIXEL] = imx8m_clk_hw_composite("camera_pixel", imx8mn_camera_pixel_sels, base + 0xbd00);
491 hws[IMX8MN_CLK_CSI1_PHY_REF] = imx8m_clk_hw_composite("csi1_phy_ref", imx8mn_csi1_phy_sels, base + 0xbd80);
492 hws[IMX8MN_CLK_CSI2_PHY_REF] = imx8m_clk_hw_composite("csi2_phy_ref", imx8mn_csi2_phy_sels, base + 0xbf00);
493 hws[IMX8MN_CLK_CSI2_ESC] = imx8m_clk_hw_composite("csi2_esc", imx8mn_csi2_esc_sels, base + 0xbf80);
494 hws[IMX8MN_CLK_ECSPI3] = imx8m_clk_hw_composite("ecspi3", imx8mn_ecspi3_sels, base + 0xc180);
495 hws[IMX8MN_CLK_PDM] = imx8m_clk_hw_composite("pdm", imx8mn_pdm_sels, base + 0xc200);
496 hws[IMX8MN_CLK_SAI7] = imx8m_clk_hw_composite("sai7", imx8mn_sai7_sels, base + 0xc300);
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]497
Peng Fandaeb1452019-12-12 02:59:17 +0000[diff] [blame]498 hws[IMX8MN_CLK_ECSPI1_ROOT] = imx_clk_hw_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0);
499 hws[IMX8MN_CLK_ECSPI2_ROOT] = imx_clk_hw_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0);
500 hws[IMX8MN_CLK_ECSPI3_ROOT] = imx_clk_hw_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0);
501 hws[IMX8MN_CLK_ENET1_ROOT] = imx_clk_hw_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0);
502 hws[IMX8MN_CLK_GPIO1_ROOT] = imx_clk_hw_gate4("gpio1_root_clk", "ipg_root", base + 0x40b0, 0);
503 hws[IMX8MN_CLK_GPIO2_ROOT] = imx_clk_hw_gate4("gpio2_root_clk", "ipg_root", base + 0x40c0, 0);
504 hws[IMX8MN_CLK_GPIO3_ROOT] = imx_clk_hw_gate4("gpio3_root_clk", "ipg_root", base + 0x40d0, 0);
505 hws[IMX8MN_CLK_GPIO4_ROOT] = imx_clk_hw_gate4("gpio4_root_clk", "ipg_root", base + 0x40e0, 0);
506 hws[IMX8MN_CLK_GPIO5_ROOT] = imx_clk_hw_gate4("gpio5_root_clk", "ipg_root", base + 0x40f0, 0);
507 hws[IMX8MN_CLK_I2C1_ROOT] = imx_clk_hw_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0);
508 hws[IMX8MN_CLK_I2C2_ROOT] = imx_clk_hw_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0);
509 hws[IMX8MN_CLK_I2C3_ROOT] = imx_clk_hw_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0);
510 hws[IMX8MN_CLK_I2C4_ROOT] = imx_clk_hw_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0);
511 hws[IMX8MN_CLK_MU_ROOT] = imx_clk_hw_gate4("mu_root_clk", "ipg_root", base + 0x4210, 0);
512 hws[IMX8MN_CLK_OCOTP_ROOT] = imx_clk_hw_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0);
513 hws[IMX8MN_CLK_PWM1_ROOT] = imx_clk_hw_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0);
514 hws[IMX8MN_CLK_PWM2_ROOT] = imx_clk_hw_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0);
515 hws[IMX8MN_CLK_PWM3_ROOT] = imx_clk_hw_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0);
516 hws[IMX8MN_CLK_PWM4_ROOT] = imx_clk_hw_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0);
517 hws[IMX8MN_CLK_QSPI_ROOT] = imx_clk_hw_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0);
518 hws[IMX8MN_CLK_NAND_ROOT] = imx_clk_hw_gate2_shared2("nand_root_clk", "nand", base + 0x4300, 0, &share_count_nand);
519 hws[IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_hw_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_bus", base + 0x4300, 0, &share_count_nand);
520 hws[IMX8MN_CLK_SAI2_ROOT] = imx_clk_hw_gate2_shared2("sai2_root_clk", "sai2", base + 0x4340, 0, &share_count_sai2);
521 hws[IMX8MN_CLK_SAI2_IPG] = imx_clk_hw_gate2_shared2("sai2_ipg_clk", "ipg_audio_root", base + 0x4340, 0, &share_count_sai2);
522 hws[IMX8MN_CLK_SAI3_ROOT] = imx_clk_hw_gate2_shared2("sai3_root_clk", "sai3", base + 0x4350, 0, &share_count_sai3);
523 hws[IMX8MN_CLK_SAI3_IPG] = imx_clk_hw_gate2_shared2("sai3_ipg_clk", "ipg_audio_root", base + 0x4350, 0, &share_count_sai3);
524 hws[IMX8MN_CLK_SAI5_ROOT] = imx_clk_hw_gate2_shared2("sai5_root_clk", "sai5", base + 0x4370, 0, &share_count_sai5);
525 hws[IMX8MN_CLK_SAI5_IPG] = imx_clk_hw_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0, &share_count_sai5);
526 hws[IMX8MN_CLK_SAI6_ROOT] = imx_clk_hw_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0, &share_count_sai6);
527 hws[IMX8MN_CLK_SAI6_IPG] = imx_clk_hw_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0, &share_count_sai6);
Horia Geantă16e71d42020-01-16 09:37:17 +0200[diff] [blame]528 hws[IMX8MN_CLK_SNVS_ROOT] = imx_clk_hw_gate4("snvs_root_clk", "ipg_root", base + 0x4470, 0);
Peng Fandaeb1452019-12-12 02:59:17 +0000[diff] [blame]529 hws[IMX8MN_CLK_UART1_ROOT] = imx_clk_hw_gate4("uart1_root_clk", "uart1", base + 0x4490, 0);
530 hws[IMX8MN_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0);
531 hws[IMX8MN_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0);
532 hws[IMX8MN_CLK_UART4_ROOT] = imx_clk_hw_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0);
533 hws[IMX8MN_CLK_USB1_CTRL_ROOT] = imx_clk_hw_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0);
Peng Fan33db2ce2020-01-28 05:28:50 +0000[diff] [blame]534 hws[IMX8MN_CLK_GPU_CORE_ROOT] = imx_clk_hw_gate4("gpu_core_root_clk", "gpu_core", base + 0x44f0, 0);
Peng Fandaeb1452019-12-12 02:59:17 +0000[diff] [blame]535 hws[IMX8MN_CLK_USDHC1_ROOT] = imx_clk_hw_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0);
536 hws[IMX8MN_CLK_USDHC2_ROOT] = imx_clk_hw_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0);
537 hws[IMX8MN_CLK_WDOG1_ROOT] = imx_clk_hw_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0);
538 hws[IMX8MN_CLK_WDOG2_ROOT] = imx_clk_hw_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0);
539 hws[IMX8MN_CLK_WDOG3_ROOT] = imx_clk_hw_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0);
540 hws[IMX8MN_CLK_GPU_BUS_ROOT] = imx_clk_hw_gate4("gpu_root_clk", "gpu_axi", base + 0x4570, 0);
541 hws[IMX8MN_CLK_ASRC_ROOT] = imx_clk_hw_gate4("asrc_root_clk", "audio_ahb", base + 0x4580, 0);
542 hws[IMX8MN_CLK_PDM_ROOT] = imx_clk_hw_gate2_shared2("pdm_root_clk", "pdm", base + 0x45b0, 0, &share_count_pdm);
543 hws[IMX8MN_CLK_PDM_IPG] = imx_clk_hw_gate2_shared2("pdm_ipg_clk", "ipg_audio_root", base + 0x45b0, 0, &share_count_pdm);
544 hws[IMX8MN_CLK_DISP_AXI_ROOT] = imx_clk_hw_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0, &share_count_disp);
545 hws[IMX8MN_CLK_DISP_APB_ROOT] = imx_clk_hw_gate2_shared2("disp_apb_root_clk", "disp_apb", base + 0x45d0, 0, &share_count_disp);
546 hws[IMX8MN_CLK_CAMERA_PIXEL_ROOT] = imx_clk_hw_gate2_shared2("camera_pixel_clk", "camera_pixel", base + 0x45d0, 0, &share_count_disp);
547 hws[IMX8MN_CLK_DISP_PIXEL_ROOT] = imx_clk_hw_gate2_shared2("disp_pixel_clk", "disp_pixel", base + 0x45d0, 0, &share_count_disp);
548 hws[IMX8MN_CLK_USDHC3_ROOT] = imx_clk_hw_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0);
549 hws[IMX8MN_CLK_TMU_ROOT] = imx_clk_hw_gate4("tmu_root_clk", "ipg_root", base + 0x4620, 0);
550 hws[IMX8MN_CLK_SDMA1_ROOT] = imx_clk_hw_gate4("sdma1_clk", "ipg_root", base + 0x43a0, 0);
551 hws[IMX8MN_CLK_SDMA2_ROOT] = imx_clk_hw_gate4("sdma2_clk", "ipg_audio_root", base + 0x43b0, 0);
552 hws[IMX8MN_CLK_SDMA3_ROOT] = imx_clk_hw_gate4("sdma3_clk", "ipg_audio_root", base + 0x45f0, 0);
553 hws[IMX8MN_CLK_SAI7_ROOT] = imx_clk_hw_gate2_shared2("sai7_root_clk", "sai7", base + 0x4650, 0, &share_count_sai7);
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]554
Peng Fandaeb1452019-12-12 02:59:17 +0000[diff] [blame]555 hws[IMX8MN_CLK_DRAM_ALT_ROOT] = imx_clk_hw_fixed_factor("dram_alt_root", "dram_alt", 1, 4);
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]556
Peng Fandaeb1452019-12-12 02:59:17 +0000[diff] [blame]557 hws[IMX8MN_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_div",
558 hws[IMX8MN_CLK_A53_DIV]->clk,
559 hws[IMX8MN_CLK_A53_SRC]->clk,
560 hws[IMX8MN_ARM_PLL_OUT]->clk,
561 hws[IMX8MN_SYS_PLL1_800M]->clk);
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]562
Peng Fandaeb1452019-12-12 02:59:17 +0000[diff] [blame]563 imx_check_clk_hws(hws, IMX8MN_CLK_END);
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]564
Peng Fandaeb1452019-12-12 02:59:17 +0000[diff] [blame]565 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]566 if (ret < 0) {
Peng Fandaeb1452019-12-12 02:59:17 +0000[diff] [blame]567 dev_err(dev, "failed to register hws for i.MX8MN\n");
568 goto unregister_hws;
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]569 }
570
Peng Fandaeb1452019-12-12 02:59:17 +0000[diff] [blame]571 for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
572 int index = uart_clk_ids[i];
573
574 uart_hws[i] = &hws[index]->clk;
575 }
576
577 imx_register_uart_clocks(uart_hws);
Anson Huangf7988ba2019-07-24 15:50:17 +0800[diff] [blame]578
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]579 return 0;
580
Peng Fandaeb1452019-12-12 02:59:17 +0000[diff] [blame]581unregister_hws:
582 imx_unregister_hw_clocks(hws, IMX8MN_CLK_END);
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]583
584 return ret;
585}
586
587static const struct of_device_id imx8mn_clk_of_match[] = {
588 { .compatible = "fsl,imx8mn-ccm" },
589 { /* Sentinel */ },
590};
591MODULE_DEVICE_TABLE(of, imx8mn_clk_of_match);
592
593static struct platform_driver imx8mn_clk_driver = {
594 .probe = imx8mn_clocks_probe,
595 .driver = {
596 .name = "imx8mn-ccm",
Leonard Crestez2ef13932019-11-21 15:52:17 +0200[diff] [blame]597 /*
598 * Disable bind attributes: clocks are not removed and
599 * reloading the driver will crash or break devices.
600 */
601 .suppress_bind_attrs = true,
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]602 .of_match_table = of_match_ptr(imx8mn_clk_of_match),
603 },
604};
605module_platform_driver(imx8mn_clk_driver);