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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / b3d08a4b1e46cd8146eaf6d6cb3779f756f0b3f3 / . / drivers / clk / imx / clk-imx8mn.c
blob: 106cc417c19bf3317b5ad42d5fcd7a4fc36a7be1 [file] [log] [blame]
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2018-2019 NXP.
4 */
5
6#include <dt-bindings/clock/imx8mn-clock.h>
7#include <linux/clk.h>
8#include <linux/err.h>
9#include <linux/init.h>
10#include <linux/io.h>
11#include <linux/module.h>
12#include <linux/of.h>
13#include <linux/of_address.h>
14#include <linux/platform_device.h>
15#include <linux/types.h>
16
17#include "clk.h"
18
19static u32 share_count_sai2;
20static u32 share_count_sai3;
21static u32 share_count_sai5;
22static u32 share_count_sai6;
23static u32 share_count_sai7;
24static u32 share_count_disp;
25static u32 share_count_pdm;
26static u32 share_count_nand;
27
28enum {
29 ARM_PLL,
30 GPU_PLL,
31 VPU_PLL,
32 SYS_PLL1,
33 SYS_PLL2,
34 SYS_PLL3,
35 DRAM_PLL,
36 AUDIO_PLL1,
37 AUDIO_PLL2,
38 VIDEO_PLL2,
39 NR_PLLS,
40};
41
42static const struct imx_pll14xx_rate_table imx8mn_pll1416x_tbl[] = {
43 PLL_1416X_RATE(1800000000U, 225, 3, 0),
44 PLL_1416X_RATE(1600000000U, 200, 3, 0),
45 PLL_1416X_RATE(1200000000U, 300, 3, 1),
46 PLL_1416X_RATE(1000000000U, 250, 3, 1),
47 PLL_1416X_RATE(800000000U, 200, 3, 1),
48 PLL_1416X_RATE(750000000U, 250, 2, 2),
49 PLL_1416X_RATE(700000000U, 350, 3, 2),
50 PLL_1416X_RATE(600000000U, 300, 3, 2),
51};
52
53static const struct imx_pll14xx_rate_table imx8mn_audiopll_tbl[] = {
54 PLL_1443X_RATE(786432000U, 655, 5, 2, 23593),
55 PLL_1443X_RATE(722534400U, 301, 5, 1, 3670),
56};
57
58static const struct imx_pll14xx_rate_table imx8mn_videopll_tbl[] = {
59 PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
60 PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
61};
62
63static const struct imx_pll14xx_rate_table imx8mn_drampll_tbl[] = {
64 PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
65};
66
67static struct imx_pll14xx_clk imx8mn_audio_pll = {
68 .type = PLL_1443X,
69 .rate_table = imx8mn_audiopll_tbl,
70};
71
72static struct imx_pll14xx_clk imx8mn_video_pll = {
73 .type = PLL_1443X,
74 .rate_table = imx8mn_videopll_tbl,
75};
76
77static struct imx_pll14xx_clk imx8mn_dram_pll = {
78 .type = PLL_1443X,
79 .rate_table = imx8mn_drampll_tbl,
80};
81
82static struct imx_pll14xx_clk imx8mn_arm_pll = {
83 .type = PLL_1416X,
84 .rate_table = imx8mn_pll1416x_tbl,
85};
86
87static struct imx_pll14xx_clk imx8mn_gpu_pll = {
88 .type = PLL_1416X,
89 .rate_table = imx8mn_pll1416x_tbl,
90};
91
92static struct imx_pll14xx_clk imx8mn_vpu_pll = {
93 .type = PLL_1416X,
94 .rate_table = imx8mn_pll1416x_tbl,
95};
96
97static struct imx_pll14xx_clk imx8mn_sys_pll = {
98 .type = PLL_1416X,
99 .rate_table = imx8mn_pll1416x_tbl,
100};
101
102static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
103static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
104static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
105static const char * const video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", };
106static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
107static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
108static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
109static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
110static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
111static const char * const sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
112static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
113
114static const char * const imx8mn_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m",
115 "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
116 "audio_pll1_out", "sys_pll3_out", };
117
118static const char * const imx8mn_gpu_core_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
119 "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
120 "video_pll1_out", "audio_pll2_out", };
121
122static const char * const imx8mn_gpu_shader_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
123 "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
124 "video_pll1_out", "audio_pll2_out", };
125
126static const char * const imx8mn_main_axi_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll1_800m",
127 "sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out",
128 "video_pll1_out", "sys_pll1_100m",};
129
130static const char * const imx8mn_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
131 "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out",
132 "video_pll1_out", "sys_pll3_out", };
133
134static const char * const imx8mn_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
135 "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out",
136 "sys_pll2_250m", "audio_pll1_out", };
137
138static const char * const imx8mn_disp_axi_sels[] = {"osc_24m", "sys_pll2_1000m", "sys_pll1_800m",
139 "sys_pll3_out", "sys_pll1_40m", "audio_pll2_out",
140 "clk_ext1", "clk_ext4", };
141
142static const char * const imx8mn_disp_apb_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll1_800m",
Leonard Crestezb3d08a4b2019-08-13 20:05:30 +0300[diff] [blame^]143 "sys_pll3_out", "sys_pll1_40m", "audio_pll2_out",
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]144 "clk_ext1", "clk_ext3", };
145
146static const char * const imx8mn_usb_bus_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m",
147 "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
148 "clk_ext4", "audio_pll2_out", };
149
150static const char * const imx8mn_gpu_axi_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out",
151 "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
152 "video_pll1_out", "audio_pll2_out", };
153
154static const char * const imx8mn_gpu_ahb_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out",
155 "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
156 "video_pll1_out", "audio_pll2_out", };
157
158static const char * const imx8mn_noc_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out",
159 "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out",
160 "video_pll1_out", "audio_pll2_out", };
161
162static const char * const imx8mn_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m",
163 "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out",
164 "audio_pll1_out", "video_pll1_out", };
165
166static const char * const imx8mn_audio_ahb_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m",
167 "sys_pll2_1000m", "sys_pll2_166m", "sys_pll3_out",
168 "audio_pll1_out", "video_pll1_out", };
169
170static const char * const imx8mn_dram_alt_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll1_100m",
171 "sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out",
172 "audio_pll1_out", "sys_pll1_266m", };
173
174static const char * const imx8mn_dram_apb_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
175 "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
176 "sys_pll2_250m", "audio_pll2_out", };
177
178static const char * const imx8mn_disp_pixel_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out",
179 "audio_pll1_out", "sys_pll1_800m", "sys_pll2_1000m",
180 "sys_pll3_out", "clk_ext4", };
181
182static const char * const imx8mn_sai2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
183 "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
184 "clk_ext3", "clk_ext4", };
185
186static const char * const imx8mn_sai3_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
187 "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
188 "clk_ext3", "clk_ext4", };
189
190static const char * const imx8mn_sai5_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
191 "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
192 "clk_ext2", "clk_ext3", };
193
194static const char * const imx8mn_sai6_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
195 "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
196 "clk_ext3", "clk_ext4", };
197
198static const char * const imx8mn_sai7_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
199 "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
200 "clk_ext3", "clk_ext4", };
201
202static const char * const imx8mn_spdif1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
203 "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
204 "clk_ext2", "clk_ext3", };
205
206static const char * const imx8mn_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m",
207 "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
208 "video_pll1_out", "clk_ext4", };
209
210static const char * const imx8mn_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
211 "clk_ext1", "clk_ext2", "clk_ext3",
212 "clk_ext4", "video_pll1_out", };
213
214static const char * const imx8mn_enet_phy_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m",
215 "sys_pll2_200m", "sys_pll2_500m", "video_pll1_out",
216 "audio_pll2_out", };
217
218static const char * const imx8mn_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out",
219 "sys_pll1_400m", "audio_pll2_out", "sys_pll3_out",
220 "sys_pll2_250m", "video_pll1_out", };
221
Leonard Crestezb3d08a4b2019-08-13 20:05:30 +0300[diff] [blame^]222static const char * const imx8mn_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m",
223 "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m",
224 "sys_pll3_out", "sys_pll1_100m", };
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]225
226static const char * const imx8mn_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
227 "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
228 "audio_pll2_out", "sys_pll1_100m", };
229
230static const char * const imx8mn_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
231 "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
232 "audio_pll2_out", "sys_pll1_100m", };
233
234static const char * const imx8mn_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
235 "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
236 "audio_pll2_out", "sys_pll1_133m", };
237
238static const char * const imx8mn_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
239 "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
240 "audio_pll2_out", "sys_pll1_133m", };
241
242static const char * const imx8mn_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
243 "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
244 "audio_pll2_out", "sys_pll1_133m", };
245
246static const char * const imx8mn_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
247 "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
248 "audio_pll2_out", "sys_pll1_133m", };
249
250static const char * const imx8mn_uart1_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
251 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
252 "clk_ext4", "audio_pll2_out", };
253
254static const char * const imx8mn_uart2_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
255 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
256 "clk_ext3", "audio_pll2_out", };
257
258static const char * const imx8mn_uart3_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
259 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
260 "clk_ext4", "audio_pll2_out", };
261
262static const char * const imx8mn_uart4_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
263 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
264 "clk_ext3", "audio_pll2_out", };
265
266static const char * const imx8mn_usb_core_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m",
267 "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
268 "clk_ext3", "audio_pll2_out", };
269
270static const char * const imx8mn_usb_phy_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m",
271 "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
272 "clk_ext3", "audio_pll2_out", };
273
274static const char * const imx8mn_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
275 "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
276 "sys_pll2_250m", "audio_pll2_out", };
277
278static const char * const imx8mn_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
279 "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
280 "sys_pll2_250m", "audio_pll2_out", };
281
282static const char * const imx8mn_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
283 "sys_pll1_40m", "sys_pll3_out", "clk_ext1",
284 "sys_pll1_80m", "video_pll1_out", };
285
286static const char * const imx8mn_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
287 "sys_pll1_40m", "sys_pll3_out", "clk_ext1",
288 "sys_pll1_80m", "video_pll1_out", };
289
290static const char * const imx8mn_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
Leonard Crestezb3d08a4b2019-08-13 20:05:30 +0300[diff] [blame^]291 "sys_pll1_40m", "sys_pll3_out", "clk_ext2",
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]292 "sys_pll1_80m", "video_pll1_out", };
293
294static const char * const imx8mn_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
295 "sys_pll1_40m", "sys_pll3_out", "clk_ext2",
296 "sys_pll1_80m", "video_pll1_out", };
297
298static const char * const imx8mn_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m",
299 "vpu_pll_out", "sys_pll2_125m", "sys_pll3_out",
300 "sys_pll1_80m", "sys_pll2_166m", };
301
302static const char * const imx8mn_wrclk_sels[] = {"osc_24m", "sys_pll1_40m", "vpu_pll_out",
303 "sys_pll3_out", "sys_pll2_200m", "sys_pll1_266m",
304 "sys_pll2_500m", "sys_pll1_100m", };
305
306static const char * const imx8mn_dsi_core_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m",
307 "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
308 "audio_pll2_out", "video_pll1_out", };
309
310static const char * const imx8mn_dsi_phy_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_100m",
311 "sys_pll1_800m", "sys_pll2_1000m", "clk_ext2",
312 "audio_pll2_out", "video_pll1_out", };
313
314static const char * const imx8mn_dsi_dbi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_100m",
315 "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
316 "audio_pll2_out", "video_pll1_out", };
317
318static const char * const imx8mn_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
319 "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
Leonard Crestezb3d08a4b2019-08-13 20:05:30 +0300[diff] [blame^]320 "audio_pll2_out", "sys_pll1_100m", };
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]321
322static const char * const imx8mn_camera_pixel_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m",
323 "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
324 "audio_pll2_out", "video_pll1_out", };
325
326static const char * const imx8mn_csi1_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m",
327 "sys_pll1_800m", "sys_pll2_1000m", "clk_ext2",
328 "audio_pll2_out", "video_pll1_out", };
329
330static const char * const imx8mn_csi2_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m",
331 "sys_pll1_800m", "sys_pll2_1000m", "clk_ext2",
332 "audio_pll2_out", "video_pll1_out", };
333
334static const char * const imx8mn_csi2_esc_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m",
335 "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
336 "clk_ext3", "audio_pll2_out", };
337
338static const char * const imx8mn_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
339 "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
340 "sys_pll2_250m", "audio_pll2_out", };
341
342static const char * const imx8mn_pdm_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
343 "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
344 "clk_ext3", "audio_pll2_out", };
345
346static const char * const imx8mn_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
347
348static const char * const imx8mn_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "osc_27m",
Leonard Crestezb3d08a4b2019-08-13 20:05:30 +0300[diff] [blame^]349 "sys_pll1_200m", "audio_pll2_out", "vpu_pll",
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]350 "sys_pll1_80m", };
351static const char * const imx8mn_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m",
352 "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out",
353 "video_pll1_out", "osc_32k", };
354
355static struct clk *clks[IMX8MN_CLK_END];
356static struct clk_onecell_data clk_data;
357
Anson Huangf7988ba2019-07-24 15:50:17 +0800[diff] [blame]358static struct clk ** const uart_clks[] = {
359 &clks[IMX8MN_CLK_UART1_ROOT],
360 &clks[IMX8MN_CLK_UART2_ROOT],
361 &clks[IMX8MN_CLK_UART3_ROOT],
362 &clks[IMX8MN_CLK_UART4_ROOT],
363 NULL
364};
365
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]366static int imx8mn_clocks_probe(struct platform_device *pdev)
367{
368 struct device *dev = &pdev->dev;
369 struct device_node *np = dev->of_node;
370 void __iomem *base;
371 int ret;
372
373 clks[IMX8MN_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
374 clks[IMX8MN_CLK_24M] = of_clk_get_by_name(np, "osc_24m");
375 clks[IMX8MN_CLK_32K] = of_clk_get_by_name(np, "osc_32k");
376 clks[IMX8MN_CLK_EXT1] = of_clk_get_by_name(np, "clk_ext1");
377 clks[IMX8MN_CLK_EXT2] = of_clk_get_by_name(np, "clk_ext2");
378 clks[IMX8MN_CLK_EXT3] = of_clk_get_by_name(np, "clk_ext3");
379 clks[IMX8MN_CLK_EXT4] = of_clk_get_by_name(np, "clk_ext4");
380
381 np = of_find_compatible_node(NULL, NULL, "fsl,imx8mn-anatop");
382 base = of_iomap(np, 0);
383 if (WARN_ON(!base)) {
384 ret = -ENOMEM;
385 goto unregister_clks;
386 }
387
388 clks[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
389 clks[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
390 clks[IMX8MN_VIDEO_PLL1_REF_SEL] = imx_clk_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
391 clks[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
392 clks[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
393 clks[IMX8MN_VPU_PLL_REF_SEL] = imx_clk_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
394 clks[IMX8MN_ARM_PLL_REF_SEL] = imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
395 clks[IMX8MN_SYS_PLL1_REF_SEL] = imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
396 clks[IMX8MN_SYS_PLL2_REF_SEL] = imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
397 clks[IMX8MN_SYS_PLL3_REF_SEL] = imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
398
399 clks[IMX8MN_AUDIO_PLL1] = imx_clk_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx8mn_audio_pll);
400 clks[IMX8MN_AUDIO_PLL2] = imx_clk_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx8mn_audio_pll);
401 clks[IMX8MN_VIDEO_PLL1] = imx_clk_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx8mn_video_pll);
402 clks[IMX8MN_DRAM_PLL] = imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx8mn_dram_pll);
403 clks[IMX8MN_GPU_PLL] = imx_clk_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx8mn_gpu_pll);
404 clks[IMX8MN_VPU_PLL] = imx_clk_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx8mn_vpu_pll);
405 clks[IMX8MN_ARM_PLL] = imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx8mn_arm_pll);
406 clks[IMX8MN_SYS_PLL1] = imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel", base + 0x94, &imx8mn_sys_pll);
407 clks[IMX8MN_SYS_PLL2] = imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel", base + 0x104, &imx8mn_sys_pll);
408 clks[IMX8MN_SYS_PLL3] = imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx8mn_sys_pll);
409
410 /* PLL bypass out */
411 clks[IMX8MN_AUDIO_PLL1_BYPASS] = imx_clk_mux_flags("audio_pll1_bypass", base, 4, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT);
412 clks[IMX8MN_AUDIO_PLL2_BYPASS] = imx_clk_mux_flags("audio_pll2_bypass", base + 0x14, 4, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT);
413 clks[IMX8MN_VIDEO_PLL1_BYPASS] = imx_clk_mux_flags("video_pll1_bypass", base + 0x28, 4, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT);
414 clks[IMX8MN_DRAM_PLL_BYPASS] = imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT);
415 clks[IMX8MN_GPU_PLL_BYPASS] = imx_clk_mux_flags("gpu_pll_bypass", base + 0x64, 4, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
416 clks[IMX8MN_VPU_PLL_BYPASS] = imx_clk_mux_flags("vpu_pll_bypass", base + 0x74, 4, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
417 clks[IMX8MN_ARM_PLL_BYPASS] = imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT);
418 clks[IMX8MN_SYS_PLL1_BYPASS] = imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT);
419 clks[IMX8MN_SYS_PLL2_BYPASS] = imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT);
420 clks[IMX8MN_SYS_PLL3_BYPASS] = imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT);
421
422 /* unbypass all the plls */
423 clk_set_parent(clks[IMX8MN_AUDIO_PLL1_BYPASS], clks[IMX8MN_AUDIO_PLL1]);
424 clk_set_parent(clks[IMX8MN_AUDIO_PLL2_BYPASS], clks[IMX8MN_AUDIO_PLL2]);
425 clk_set_parent(clks[IMX8MN_VIDEO_PLL1_BYPASS], clks[IMX8MN_VIDEO_PLL1]);
426 clk_set_parent(clks[IMX8MN_DRAM_PLL_BYPASS], clks[IMX8MN_DRAM_PLL]);
427 clk_set_parent(clks[IMX8MN_GPU_PLL_BYPASS], clks[IMX8MN_GPU_PLL]);
428 clk_set_parent(clks[IMX8MN_VPU_PLL_BYPASS], clks[IMX8MN_VPU_PLL]);
429 clk_set_parent(clks[IMX8MN_ARM_PLL_BYPASS], clks[IMX8MN_ARM_PLL]);
430 clk_set_parent(clks[IMX8MN_SYS_PLL1_BYPASS], clks[IMX8MN_SYS_PLL1]);
431 clk_set_parent(clks[IMX8MN_SYS_PLL2_BYPASS], clks[IMX8MN_SYS_PLL2]);
432 clk_set_parent(clks[IMX8MN_SYS_PLL3_BYPASS], clks[IMX8MN_SYS_PLL3]);
433
434 /* PLL out gate */
435 clks[IMX8MN_AUDIO_PLL1_OUT] = imx_clk_gate("audio_pll1_out", "audio_pll1_bypass", base, 13);
436 clks[IMX8MN_AUDIO_PLL2_OUT] = imx_clk_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x14, 13);
437 clks[IMX8MN_VIDEO_PLL1_OUT] = imx_clk_gate("video_pll1_out", "video_pll1_bypass", base + 0x28, 13);
438 clks[IMX8MN_DRAM_PLL_OUT] = imx_clk_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13);
439 clks[IMX8MN_GPU_PLL_OUT] = imx_clk_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 13);
440 clks[IMX8MN_VPU_PLL_OUT] = imx_clk_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x74, 13);
441 clks[IMX8MN_ARM_PLL_OUT] = imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 13);
442 clks[IMX8MN_SYS_PLL1_OUT] = imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", base + 0x94, 13);
443 clks[IMX8MN_SYS_PLL2_OUT] = imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", base + 0x104, 13);
444 clks[IMX8MN_SYS_PLL3_OUT] = imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 13);
445
446 /* SYS PLL fixed output */
447 clks[IMX8MN_SYS_PLL1_40M] = imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20);
448 clks[IMX8MN_SYS_PLL1_80M] = imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10);
449 clks[IMX8MN_SYS_PLL1_100M] = imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8);
450 clks[IMX8MN_SYS_PLL1_133M] = imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6);
451 clks[IMX8MN_SYS_PLL1_160M] = imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5);
452 clks[IMX8MN_SYS_PLL1_200M] = imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4);
453 clks[IMX8MN_SYS_PLL1_266M] = imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3);
454 clks[IMX8MN_SYS_PLL1_400M] = imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2);
455 clks[IMX8MN_SYS_PLL1_800M] = imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1);
456
457 clks[IMX8MN_SYS_PLL2_50M] = imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20);
458 clks[IMX8MN_SYS_PLL2_100M] = imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10);
459 clks[IMX8MN_SYS_PLL2_125M] = imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8);
460 clks[IMX8MN_SYS_PLL2_166M] = imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6);
461 clks[IMX8MN_SYS_PLL2_200M] = imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5);
462 clks[IMX8MN_SYS_PLL2_250M] = imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4);
463 clks[IMX8MN_SYS_PLL2_333M] = imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3);
464 clks[IMX8MN_SYS_PLL2_500M] = imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2);
465 clks[IMX8MN_SYS_PLL2_1000M] = imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
466
467 np = dev->of_node;
468 base = devm_platform_ioremap_resource(pdev, 0);
469 if (WARN_ON(IS_ERR(base))) {
470 ret = PTR_ERR(base);
471 goto unregister_clks;
472 }
473
474 /* CORE */
475 clks[IMX8MN_CLK_A53_SRC] = imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mn_a53_sels, ARRAY_SIZE(imx8mn_a53_sels));
476 clks[IMX8MN_CLK_GPU_CORE_SRC] = imx_clk_mux2("gpu_core_src", base + 0x8180, 24, 3, imx8mn_gpu_core_sels, ARRAY_SIZE(imx8mn_gpu_core_sels));
477 clks[IMX8MN_CLK_GPU_SHADER_SRC] = imx_clk_mux2("gpu_shader_src", base + 0x8200, 24, 3, imx8mn_gpu_shader_sels, ARRAY_SIZE(imx8mn_gpu_shader_sels));
478 clks[IMX8MN_CLK_A53_CG] = imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28);
479 clks[IMX8MN_CLK_GPU_CORE_CG] = imx_clk_gate3("gpu_core_cg", "gpu_core_src", base + 0x8180, 28);
480 clks[IMX8MN_CLK_GPU_SHADER_CG] = imx_clk_gate3("gpu_shader_cg", "gpu_shader_src", base + 0x8200, 28);
481
482 clks[IMX8MN_CLK_A53_DIV] = imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3);
483 clks[IMX8MN_CLK_GPU_CORE_DIV] = imx_clk_divider2("gpu_core_div", "gpu_core_cg", base + 0x8180, 0, 3);
484 clks[IMX8MN_CLK_GPU_SHADER_DIV] = imx_clk_divider2("gpu_shader_div", "gpu_shader_cg", base + 0x8200, 0, 3);
485
486 /* BUS */
487 clks[IMX8MN_CLK_MAIN_AXI] = imx8m_clk_composite_critical("main_axi", imx8mn_main_axi_sels, base + 0x8800);
488 clks[IMX8MN_CLK_ENET_AXI] = imx8m_clk_composite("enet_axi", imx8mn_enet_axi_sels, base + 0x8880);
489 clks[IMX8MN_CLK_NAND_USDHC_BUS] = imx8m_clk_composite("nand_usdhc_bus", imx8mn_nand_usdhc_sels, base + 0x8900);
490 clks[IMX8MN_CLK_DISP_AXI] = imx8m_clk_composite("disp_axi", imx8mn_disp_axi_sels, base + 0x8a00);
491 clks[IMX8MN_CLK_DISP_APB] = imx8m_clk_composite("disp_apb", imx8mn_disp_apb_sels, base + 0x8a80);
492 clks[IMX8MN_CLK_USB_BUS] = imx8m_clk_composite("usb_bus", imx8mn_usb_bus_sels, base + 0x8b80);
493 clks[IMX8MN_CLK_GPU_AXI] = imx8m_clk_composite("gpu_axi", imx8mn_gpu_axi_sels, base + 0x8c00);
494 clks[IMX8MN_CLK_GPU_AHB] = imx8m_clk_composite("gpu_ahb", imx8mn_gpu_ahb_sels, base + 0x8c80);
495 clks[IMX8MN_CLK_NOC] = imx8m_clk_composite_critical("noc", imx8mn_noc_sels, base + 0x8d00);
496
497 clks[IMX8MN_CLK_AHB] = imx8m_clk_composite_critical("ahb", imx8mn_ahb_sels, base + 0x9000);
498 clks[IMX8MN_CLK_AUDIO_AHB] = imx8m_clk_composite("audio_ahb", imx8mn_audio_ahb_sels, base + 0x9100);
499 clks[IMX8MN_CLK_IPG_ROOT] = imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1);
500 clks[IMX8MN_CLK_IPG_AUDIO_ROOT] = imx_clk_divider2("ipg_audio_root", "audio_ahb", base + 0x9180, 0, 1);
501 clks[IMX8MN_CLK_DRAM_CORE] = imx_clk_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mn_dram_core_sels, ARRAY_SIZE(imx8mn_dram_core_sels), CLK_IS_CRITICAL);
502 clks[IMX8MN_CLK_DRAM_ALT] = imx8m_clk_composite("dram_alt", imx8mn_dram_alt_sels, base + 0xa000);
503 clks[IMX8MN_CLK_DRAM_APB] = imx8m_clk_composite_critical("dram_apb", imx8mn_dram_apb_sels, base + 0xa080);
504 clks[IMX8MN_CLK_DISP_PIXEL] = imx8m_clk_composite("disp_pixel", imx8mn_disp_pixel_sels, base + 0xa500);
505 clks[IMX8MN_CLK_SAI2] = imx8m_clk_composite("sai2", imx8mn_sai2_sels, base + 0xa600);
506 clks[IMX8MN_CLK_SAI3] = imx8m_clk_composite("sai3", imx8mn_sai3_sels, base + 0xa680);
507 clks[IMX8MN_CLK_SAI5] = imx8m_clk_composite("sai5", imx8mn_sai5_sels, base + 0xa780);
508 clks[IMX8MN_CLK_SAI6] = imx8m_clk_composite("sai6", imx8mn_sai6_sels, base + 0xa800);
509 clks[IMX8MN_CLK_SPDIF1] = imx8m_clk_composite("spdif1", imx8mn_spdif1_sels, base + 0xa880);
510 clks[IMX8MN_CLK_ENET_REF] = imx8m_clk_composite("enet_ref", imx8mn_enet_ref_sels, base + 0xa980);
511 clks[IMX8MN_CLK_ENET_TIMER] = imx8m_clk_composite("enet_timer", imx8mn_enet_timer_sels, base + 0xaa00);
512 clks[IMX8MN_CLK_ENET_PHY_REF] = imx8m_clk_composite("enet_phy", imx8mn_enet_phy_sels, base + 0xaa80);
513 clks[IMX8MN_CLK_NAND] = imx8m_clk_composite("nand", imx8mn_nand_sels, base + 0xab00);
514 clks[IMX8MN_CLK_QSPI] = imx8m_clk_composite("qspi", imx8mn_qspi_sels, base + 0xab80);
515 clks[IMX8MN_CLK_USDHC1] = imx8m_clk_composite("usdhc1", imx8mn_usdhc1_sels, base + 0xac00);
516 clks[IMX8MN_CLK_USDHC2] = imx8m_clk_composite("usdhc2", imx8mn_usdhc2_sels, base + 0xac80);
517 clks[IMX8MN_CLK_I2C1] = imx8m_clk_composite("i2c1", imx8mn_i2c1_sels, base + 0xad00);
518 clks[IMX8MN_CLK_I2C2] = imx8m_clk_composite("i2c2", imx8mn_i2c2_sels, base + 0xad80);
519 clks[IMX8MN_CLK_I2C3] = imx8m_clk_composite("i2c3", imx8mn_i2c3_sels, base + 0xae00);
520 clks[IMX8MN_CLK_I2C4] = imx8m_clk_composite("i2c4", imx8mn_i2c4_sels, base + 0xae80);
521 clks[IMX8MN_CLK_UART1] = imx8m_clk_composite("uart1", imx8mn_uart1_sels, base + 0xaf00);
522 clks[IMX8MN_CLK_UART2] = imx8m_clk_composite("uart2", imx8mn_uart2_sels, base + 0xaf80);
523 clks[IMX8MN_CLK_UART3] = imx8m_clk_composite("uart3", imx8mn_uart3_sels, base + 0xb000);
524 clks[IMX8MN_CLK_UART4] = imx8m_clk_composite("uart4", imx8mn_uart4_sels, base + 0xb080);
525 clks[IMX8MN_CLK_USB_CORE_REF] = imx8m_clk_composite("usb_core_ref", imx8mn_usb_core_sels, base + 0xb100);
526 clks[IMX8MN_CLK_USB_PHY_REF] = imx8m_clk_composite("usb_phy_ref", imx8mn_usb_phy_sels, base + 0xb180);
527 clks[IMX8MN_CLK_ECSPI1] = imx8m_clk_composite("ecspi1", imx8mn_ecspi1_sels, base + 0xb280);
528 clks[IMX8MN_CLK_ECSPI2] = imx8m_clk_composite("ecspi2", imx8mn_ecspi2_sels, base + 0xb300);
529 clks[IMX8MN_CLK_PWM1] = imx8m_clk_composite("pwm1", imx8mn_pwm1_sels, base + 0xb380);
530 clks[IMX8MN_CLK_PWM2] = imx8m_clk_composite("pwm2", imx8mn_pwm2_sels, base + 0xb400);
531 clks[IMX8MN_CLK_PWM3] = imx8m_clk_composite("pwm3", imx8mn_pwm3_sels, base + 0xb480);
532 clks[IMX8MN_CLK_PWM4] = imx8m_clk_composite("pwm4", imx8mn_pwm4_sels, base + 0xb500);
533 clks[IMX8MN_CLK_WDOG] = imx8m_clk_composite("wdog", imx8mn_wdog_sels, base + 0xb900);
534 clks[IMX8MN_CLK_WRCLK] = imx8m_clk_composite("wrclk", imx8mn_wrclk_sels, base + 0xb980);
535 clks[IMX8MN_CLK_CLKO1] = imx8m_clk_composite("clko1", imx8mn_clko1_sels, base + 0xba00);
536 clks[IMX8MN_CLK_CLKO2] = imx8m_clk_composite("clko2", imx8mn_clko2_sels, base + 0xba80);
537 clks[IMX8MN_CLK_DSI_CORE] = imx8m_clk_composite("dsi_core", imx8mn_dsi_core_sels, base + 0xbb00);
538 clks[IMX8MN_CLK_DSI_PHY_REF] = imx8m_clk_composite("dsi_phy_ref", imx8mn_dsi_phy_sels, base + 0xbb80);
539 clks[IMX8MN_CLK_DSI_DBI] = imx8m_clk_composite("dsi_dbi", imx8mn_dsi_dbi_sels, base + 0xbc00);
540 clks[IMX8MN_CLK_USDHC3] = imx8m_clk_composite("usdhc3", imx8mn_usdhc3_sels, base + 0xbc80);
541 clks[IMX8MN_CLK_CAMERA_PIXEL] = imx8m_clk_composite("camera_pixel", imx8mn_camera_pixel_sels, base + 0xbd00);
542 clks[IMX8MN_CLK_CSI1_PHY_REF] = imx8m_clk_composite("csi1_phy_ref", imx8mn_csi1_phy_sels, base + 0xbd80);
543 clks[IMX8MN_CLK_CSI2_PHY_REF] = imx8m_clk_composite("csi2_phy_ref", imx8mn_csi2_phy_sels, base + 0xbf00);
544 clks[IMX8MN_CLK_CSI2_ESC] = imx8m_clk_composite("csi2_esc", imx8mn_csi2_esc_sels, base + 0xbf80);
545 clks[IMX8MN_CLK_ECSPI3] = imx8m_clk_composite("ecspi3", imx8mn_ecspi3_sels, base + 0xc180);
546 clks[IMX8MN_CLK_PDM] = imx8m_clk_composite("pdm", imx8mn_pdm_sels, base + 0xc200);
547 clks[IMX8MN_CLK_SAI7] = imx8m_clk_composite("sai7", imx8mn_sai7_sels, base + 0xc300);
548
549 clks[IMX8MN_CLK_ECSPI1_ROOT] = imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0);
550 clks[IMX8MN_CLK_ECSPI2_ROOT] = imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0);
551 clks[IMX8MN_CLK_ECSPI3_ROOT] = imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0);
552 clks[IMX8MN_CLK_ENET1_ROOT] = imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0);
553 clks[IMX8MN_CLK_GPIO1_ROOT] = imx_clk_gate4("gpio1_root_clk", "ipg_root", base + 0x40b0, 0);
554 clks[IMX8MN_CLK_GPIO2_ROOT] = imx_clk_gate4("gpio2_root_clk", "ipg_root", base + 0x40c0, 0);
555 clks[IMX8MN_CLK_GPIO3_ROOT] = imx_clk_gate4("gpio3_root_clk", "ipg_root", base + 0x40d0, 0);
556 clks[IMX8MN_CLK_GPIO4_ROOT] = imx_clk_gate4("gpio4_root_clk", "ipg_root", base + 0x40e0, 0);
557 clks[IMX8MN_CLK_GPIO5_ROOT] = imx_clk_gate4("gpio5_root_clk", "ipg_root", base + 0x40f0, 0);
558 clks[IMX8MN_CLK_I2C1_ROOT] = imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0);
559 clks[IMX8MN_CLK_I2C2_ROOT] = imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0);
560 clks[IMX8MN_CLK_I2C3_ROOT] = imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0);
561 clks[IMX8MN_CLK_I2C4_ROOT] = imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0);
562 clks[IMX8MN_CLK_MU_ROOT] = imx_clk_gate4("mu_root_clk", "ipg_root", base + 0x4210, 0);
563 clks[IMX8MN_CLK_OCOTP_ROOT] = imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0);
564 clks[IMX8MN_CLK_PWM1_ROOT] = imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0);
565 clks[IMX8MN_CLK_PWM2_ROOT] = imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0);
566 clks[IMX8MN_CLK_PWM3_ROOT] = imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0);
567 clks[IMX8MN_CLK_PWM4_ROOT] = imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0);
568 clks[IMX8MN_CLK_QSPI_ROOT] = imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0);
569 clks[IMX8MN_CLK_NAND_ROOT] = imx_clk_gate2_shared2("nand_root_clk", "nand", base + 0x4300, 0, &share_count_nand);
570 clks[IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_bus", base + 0x4300, 0, &share_count_nand);
571 clks[IMX8MN_CLK_SAI2_ROOT] = imx_clk_gate2_shared2("sai2_root_clk", "sai2", base + 0x4340, 0, &share_count_sai2);
572 clks[IMX8MN_CLK_SAI2_IPG] = imx_clk_gate2_shared2("sai2_ipg_clk", "ipg_audio_root", base + 0x4340, 0, &share_count_sai2);
573 clks[IMX8MN_CLK_SAI3_ROOT] = imx_clk_gate2_shared2("sai3_root_clk", "sai3", base + 0x4350, 0, &share_count_sai3);
574 clks[IMX8MN_CLK_SAI3_IPG] = imx_clk_gate2_shared2("sai3_ipg_clk", "ipg_audio_root", base + 0x4350, 0, &share_count_sai3);
575 clks[IMX8MN_CLK_SAI5_ROOT] = imx_clk_gate2_shared2("sai5_root_clk", "sai5", base + 0x4370, 0, &share_count_sai5);
576 clks[IMX8MN_CLK_SAI5_IPG] = imx_clk_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0, &share_count_sai5);
577 clks[IMX8MN_CLK_SAI6_ROOT] = imx_clk_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0, &share_count_sai6);
578 clks[IMX8MN_CLK_SAI6_IPG] = imx_clk_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0, &share_count_sai6);
579 clks[IMX8MN_CLK_UART1_ROOT] = imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0);
580 clks[IMX8MN_CLK_UART2_ROOT] = imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0);
581 clks[IMX8MN_CLK_UART3_ROOT] = imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0);
582 clks[IMX8MN_CLK_UART4_ROOT] = imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0);
583 clks[IMX8MN_CLK_USB1_CTRL_ROOT] = imx_clk_gate4("usb1_ctrl_root_clk", "usb_core_ref", base + 0x44d0, 0);
584 clks[IMX8MN_CLK_GPU_CORE_ROOT] = imx_clk_gate4("gpu_core_root_clk", "gpu_core_div", base + 0x44f0, 0);
585 clks[IMX8MN_CLK_USDHC1_ROOT] = imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0);
586 clks[IMX8MN_CLK_USDHC2_ROOT] = imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0);
587 clks[IMX8MN_CLK_WDOG1_ROOT] = imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0);
588 clks[IMX8MN_CLK_WDOG2_ROOT] = imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0);
589 clks[IMX8MN_CLK_WDOG3_ROOT] = imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0);
590 clks[IMX8MN_CLK_GPU_BUS_ROOT] = imx_clk_gate4("gpu_root_clk", "gpu_axi", base + 0x4570, 0);
591 clks[IMX8MN_CLK_ASRC_ROOT] = imx_clk_gate4("asrc_root_clk", "audio_ahb", base + 0x4580, 0);
592 clks[IMX8MN_CLK_PDM_ROOT] = imx_clk_gate2_shared2("pdm_root_clk", "pdm", base + 0x45b0, 0, &share_count_pdm);
593 clks[IMX8MN_CLK_PDM_IPG] = imx_clk_gate2_shared2("pdm_ipg_clk", "ipg_audio_root", base + 0x45b0, 0, &share_count_pdm);
594 clks[IMX8MN_CLK_DISP_AXI_ROOT] = imx_clk_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0, &share_count_disp);
595 clks[IMX8MN_CLK_DISP_APB_ROOT] = imx_clk_gate2_shared2("disp_apb_root_clk", "disp_apb", base + 0x45d0, 0, &share_count_disp);
596 clks[IMX8MN_CLK_CAMERA_PIXEL_ROOT] = imx_clk_gate2_shared2("camera_pixel_clk", "camera_pixel", base + 0x45d0, 0, &share_count_disp);
597 clks[IMX8MN_CLK_DISP_PIXEL_ROOT] = imx_clk_gate2_shared2("disp_pixel_clk", "disp_pixel", base + 0x45d0, 0, &share_count_disp);
598 clks[IMX8MN_CLK_USDHC3_ROOT] = imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0);
599 clks[IMX8MN_CLK_TMU_ROOT] = imx_clk_gate4("tmu_root_clk", "ipg_root", base + 0x4620, 0);
600 clks[IMX8MN_CLK_SDMA1_ROOT] = imx_clk_gate4("sdma1_clk", "ipg_root", base + 0x43a0, 0);
601 clks[IMX8MN_CLK_SDMA2_ROOT] = imx_clk_gate4("sdma2_clk", "ipg_audio_root", base + 0x43b0, 0);
602 clks[IMX8MN_CLK_SDMA3_ROOT] = imx_clk_gate4("sdma3_clk", "ipg_audio_root", base + 0x45f0, 0);
603 clks[IMX8MN_CLK_SAI7_ROOT] = imx_clk_gate2_shared2("sai7_root_clk", "sai7", base + 0x4650, 0, &share_count_sai7);
604
605 clks[IMX8MN_CLK_DRAM_ALT_ROOT] = imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4);
606
607 clks[IMX8MN_CLK_ARM] = imx_clk_cpu("arm", "arm_a53_div",
608 clks[IMX8MN_CLK_A53_DIV],
609 clks[IMX8MN_CLK_A53_SRC],
610 clks[IMX8MN_ARM_PLL_OUT],
611 clks[IMX8MN_CLK_24M]);
612
613 imx_check_clocks(clks, ARRAY_SIZE(clks));
614
615 clk_data.clks = clks;
616 clk_data.clk_num = ARRAY_SIZE(clks);
617 ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
618 if (ret < 0) {
619 dev_err(dev, "failed to register clks for i.MX8MN\n");
620 goto unregister_clks;
621 }
622
Anson Huangf7988ba2019-07-24 15:50:17 +0800[diff] [blame]623 imx_register_uart_clocks(uart_clks);
624
Anson Huang96d63922019-06-19 13:52:46 +0800[diff] [blame]625 return 0;
626
627unregister_clks:
628 imx_unregister_clocks(clks, ARRAY_SIZE(clks));
629
630 return ret;
631}
632
633static const struct of_device_id imx8mn_clk_of_match[] = {
634 { .compatible = "fsl,imx8mn-ccm" },
635 { /* Sentinel */ },
636};
637MODULE_DEVICE_TABLE(of, imx8mn_clk_of_match);
638
639static struct platform_driver imx8mn_clk_driver = {
640 .probe = imx8mn_clocks_probe,
641 .driver = {
642 .name = "imx8mn-ccm",
643 .of_match_table = of_match_ptr(imx8mn_clk_of_match),
644 },
645};
646module_platform_driver(imx8mn_clk_driver);