Andrew Lunn | 4a2c259 | 2019-02-06 00:16:41 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| 2 | |
| 3 | /* |
| 4 | * Device tree file for ZII's SSMB DTU board |
| 5 | * |
| 6 | * SSMB - SPU3 Switch Management Board |
| 7 | * DTU - Digital Tapping Unit |
| 8 | * |
| 9 | * Copyright (C) 2015-2019 Zodiac Inflight Innovations |
| 10 | * |
| 11 | * Based on an original 'vf610-twr.dts' which is Copyright 2015, |
| 12 | * Freescale Semiconductor, Inc. |
| 13 | */ |
| 14 | |
| 15 | /dts-v1/; |
| 16 | #include "vf610.dtsi" |
| 17 | |
| 18 | / { |
| 19 | model = "ZII VF610 SSMB DTU Board"; |
| 20 | compatible = "zii,vf610dtu", "zii,vf610dev", "fsl,vf610"; |
| 21 | |
| 22 | chosen { |
| 23 | stdout-path = &uart0; |
| 24 | }; |
| 25 | |
| 26 | memory@80000000 { |
| 27 | device_type = "memory"; |
| 28 | reg = <0x80000000 0x20000000>; |
| 29 | }; |
| 30 | |
| 31 | gpio-leds { |
| 32 | compatible = "gpio-leds"; |
| 33 | pinctrl-0 = <&pinctrl_leds_debug>; |
| 34 | pinctrl-names = "default"; |
| 35 | |
| 36 | led-debug { |
| 37 | label = "zii:green:debug1"; |
| 38 | gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; |
| 39 | linux,default-trigger = "heartbeat"; |
Andrew Lunn | 4a2c259 | 2019-02-06 00:16:41 +0100 | [diff] [blame] | 40 | }; |
| 41 | }; |
| 42 | |
| 43 | reg_vcc_3v3_mcu: regulator { |
| 44 | compatible = "regulator-fixed"; |
| 45 | regulator-name = "vcc_3v3_mcu"; |
| 46 | regulator-min-microvolt = <3300000>; |
| 47 | regulator-max-microvolt = <3300000>; |
| 48 | }; |
Andrey Smirnov | a049c96 | 2020-01-14 07:19:03 -0800 | [diff] [blame] | 49 | |
| 50 | supply-voltage-monitor { |
| 51 | compatible = "iio-hwmon"; |
| 52 | io-channels = <&adc0 8>, /* 12V_MAIN */ |
| 53 | <&adc0 9>, /* +3.3V */ |
| 54 | <&adc1 8>, /* VCC_1V5 */ |
| 55 | <&adc1 9>; /* VCC_1V2 */ |
| 56 | }; |
Andrew Lunn | 4a2c259 | 2019-02-06 00:16:41 +0100 | [diff] [blame] | 57 | }; |
| 58 | |
| 59 | &adc0 { |
| 60 | vref-supply = <®_vcc_3v3_mcu>; |
| 61 | status = "okay"; |
| 62 | }; |
| 63 | |
| 64 | &adc1 { |
| 65 | vref-supply = <®_vcc_3v3_mcu>; |
| 66 | status = "okay"; |
| 67 | }; |
| 68 | |
| 69 | &edma0 { |
| 70 | status = "okay"; |
| 71 | }; |
| 72 | |
| 73 | &edma1 { |
| 74 | status = "okay"; |
| 75 | }; |
| 76 | |
| 77 | &esdhc0 { |
| 78 | pinctrl-names = "default"; |
| 79 | pinctrl-0 = <&pinctrl_esdhc0>; |
| 80 | bus-width = <8>; |
| 81 | non-removable; |
| 82 | no-1-8-v; |
| 83 | keep-power-in-suspend; |
Chris Healy | 2b4bd73 | 2020-07-15 14:31:48 -0700 | [diff] [blame] | 84 | no-sdio; |
| 85 | no-sd; |
Andrew Lunn | 4a2c259 | 2019-02-06 00:16:41 +0100 | [diff] [blame] | 86 | status = "okay"; |
| 87 | }; |
| 88 | |
| 89 | &esdhc1 { |
| 90 | pinctrl-names = "default"; |
| 91 | pinctrl-0 = <&pinctrl_esdhc1>; |
| 92 | bus-width = <4>; |
Chris Healy | 2b4bd73 | 2020-07-15 14:31:48 -0700 | [diff] [blame] | 93 | no-sdio; |
Andrew Lunn | 4a2c259 | 2019-02-06 00:16:41 +0100 | [diff] [blame] | 94 | status = "okay"; |
| 95 | }; |
| 96 | |
| 97 | &fec1 { |
| 98 | phy-mode = "rmii"; |
| 99 | pinctrl-names = "default"; |
| 100 | pinctrl-0 = <&pinctrl_fec1>; |
| 101 | status = "okay"; |
| 102 | |
| 103 | fixed-link { |
| 104 | speed = <100>; |
| 105 | full-duplex; |
| 106 | }; |
| 107 | |
| 108 | mdio1: mdio { |
| 109 | #address-cells = <1>; |
| 110 | #size-cells = <0>; |
Chris Healy | b955387 | 2020-07-07 18:16:27 -0700 | [diff] [blame] | 111 | clock-frequency = <12500000>; |
| 112 | suppress-preamble; |
Andrew Lunn | 4a2c259 | 2019-02-06 00:16:41 +0100 | [diff] [blame] | 113 | status = "okay"; |
| 114 | |
| 115 | switch0: switch0@0 { |
| 116 | compatible = "marvell,mv88e6190"; |
| 117 | pinctrl-0 = <&pinctrl_gpio_switch0>; |
| 118 | pinctrl-names = "default"; |
| 119 | reg = <0>; |
| 120 | eeprom-length = <65536>; |
Andrew Lunn | 4a2c259 | 2019-02-06 00:16:41 +0100 | [diff] [blame] | 121 | interrupt-parent = <&gpio3>; |
| 122 | interrupts = <2 IRQ_TYPE_LEVEL_LOW>; |
| 123 | interrupt-controller; |
| 124 | #interrupt-cells = <2>; |
| 125 | |
| 126 | ports { |
| 127 | #address-cells = <1>; |
| 128 | #size-cells = <0>; |
| 129 | |
| 130 | port@0 { |
| 131 | reg = <0>; |
| 132 | label = "cpu"; |
| 133 | ethernet = <&fec1>; |
| 134 | |
| 135 | fixed-link { |
| 136 | speed = <100>; |
| 137 | full-duplex; |
| 138 | }; |
| 139 | }; |
| 140 | |
| 141 | port@1 { |
| 142 | reg = <1>; |
| 143 | label = "eth_cu_100_3"; |
| 144 | }; |
| 145 | |
| 146 | port@5 { |
| 147 | reg = <5>; |
| 148 | label = "eth_cu_1000_4"; |
| 149 | }; |
| 150 | |
| 151 | port@6 { |
| 152 | reg = <6>; |
| 153 | label = "eth_cu_1000_5"; |
| 154 | }; |
| 155 | |
| 156 | port@8 { |
| 157 | reg = <8>; |
| 158 | label = "eth_cu_1000_1"; |
| 159 | }; |
| 160 | |
| 161 | port@9 { |
| 162 | reg = <9>; |
| 163 | label = "eth_cu_1000_2"; |
| 164 | phy-handle = <&phy9>; |
| 165 | phy-mode = "sgmii"; |
| 166 | managed = "in-band-status"; |
| 167 | }; |
| 168 | }; |
| 169 | |
| 170 | mdio1 { |
| 171 | compatible = "marvell,mv88e6xxx-mdio-external"; |
| 172 | #address-cells = <1>; |
| 173 | #size-cells = <0>; |
| 174 | |
| 175 | phy9: phy9@0 { |
| 176 | compatible = "ethernet-phy-ieee802.3-c45"; |
| 177 | pinctrl-0 = <&pinctrl_gpio_phy9>; |
| 178 | pinctrl-names = "default"; |
| 179 | interrupt-parent = <&gpio2>; |
| 180 | interrupts = <30 IRQ_TYPE_LEVEL_LOW>; |
| 181 | reg = <0>; |
| 182 | }; |
| 183 | }; |
| 184 | }; |
| 185 | }; |
| 186 | }; |
| 187 | |
| 188 | &i2c0 { |
| 189 | clock-frequency = <100000>; |
| 190 | pinctrl-names = "default"; |
| 191 | pinctrl-0 = <&pinctrl_i2c0>; |
| 192 | status = "okay"; |
| 193 | |
| 194 | gpio6: gpio-expander@22 { |
| 195 | compatible = "nxp,pca9554"; |
| 196 | reg = <0x22>; |
| 197 | gpio-controller; |
| 198 | #gpio-cells = <2>; |
| 199 | }; |
| 200 | |
| 201 | /* On SSMB */ |
| 202 | temperature-sensor@48 { |
| 203 | compatible = "national,lm75"; |
| 204 | reg = <0x48>; |
| 205 | }; |
| 206 | |
| 207 | /* On DSB */ |
| 208 | temperature-sensor@4d { |
| 209 | compatible = "national,lm75"; |
| 210 | reg = <0x4d>; |
| 211 | }; |
| 212 | |
| 213 | eeprom@50 { |
| 214 | compatible = "atmel,24c04"; |
| 215 | reg = <0x50>; |
| 216 | label = "nameplate"; |
| 217 | }; |
| 218 | |
| 219 | eeprom@52 { |
| 220 | compatible = "atmel,24c04"; |
| 221 | reg = <0x52>; |
| 222 | }; |
| 223 | }; |
| 224 | |
Fabio Estevam | 8da0af5 | 2019-02-13 16:24:38 -0200 | [diff] [blame] | 225 | &snvsrtc { |
| 226 | status = "disabled"; |
| 227 | }; |
| 228 | |
Andrew Lunn | 4a2c259 | 2019-02-06 00:16:41 +0100 | [diff] [blame] | 229 | &uart0 { |
| 230 | pinctrl-names = "default"; |
| 231 | pinctrl-0 = <&pinctrl_uart0>; |
| 232 | status = "okay"; |
| 233 | }; |
| 234 | |
| 235 | &iomuxc { |
| 236 | pinctrl_dspi1: dspi1grp { |
| 237 | fsl,pins = < |
| 238 | VF610_PAD_PTD5__DSPI1_CS0 0x1182 |
| 239 | VF610_PAD_PTD4__DSPI1_CS1 0x1182 |
| 240 | VF610_PAD_PTC6__DSPI1_SIN 0x1181 |
| 241 | VF610_PAD_PTC7__DSPI1_SOUT 0x1182 |
| 242 | VF610_PAD_PTC8__DSPI1_SCK 0x1182 |
| 243 | >; |
| 244 | }; |
| 245 | |
| 246 | pinctrl_esdhc0: esdhc0grp { |
| 247 | fsl,pins = < |
| 248 | VF610_PAD_PTC0__ESDHC0_CLK 0x31ef |
| 249 | VF610_PAD_PTC1__ESDHC0_CMD 0x31ef |
| 250 | VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef |
| 251 | VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef |
| 252 | VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef |
| 253 | VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef |
| 254 | VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef |
| 255 | VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef |
| 256 | VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef |
| 257 | VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef |
| 258 | >; |
| 259 | }; |
| 260 | |
| 261 | pinctrl_esdhc1: esdhc1grp { |
| 262 | fsl,pins = < |
| 263 | VF610_PAD_PTA24__ESDHC1_CLK 0x31ef |
| 264 | VF610_PAD_PTA25__ESDHC1_CMD 0x31ef |
| 265 | VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef |
| 266 | VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef |
| 267 | VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef |
| 268 | VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef |
| 269 | >; |
| 270 | }; |
| 271 | |
| 272 | pinctrl_fec1: fec1grp { |
| 273 | fsl,pins = < |
| 274 | VF610_PAD_PTA6__RMII_CLKIN 0x30d1 |
| 275 | VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 |
| 276 | VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 |
| 277 | VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 |
| 278 | VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 |
| 279 | VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 |
| 280 | VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 |
| 281 | VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 |
| 282 | VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 |
| 283 | VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 |
| 284 | >; |
| 285 | }; |
| 286 | |
| 287 | pinctrl_gpio_phy9: pinctrl-gpio-phy9 { |
| 288 | fsl,pins = < |
| 289 | VF610_PAD_PTB24__GPIO_94 0x219d |
| 290 | >; |
| 291 | }; |
| 292 | |
| 293 | pinctrl_gpio_switch0: pinctrl-gpio-switch0 { |
| 294 | fsl,pins = < |
Andrew Lunn | 4a2c259 | 2019-02-06 00:16:41 +0100 | [diff] [blame] | 295 | VF610_PAD_PTB28__GPIO_98 0x219d |
| 296 | >; |
| 297 | }; |
| 298 | |
| 299 | pinctrl_i2c0: i2c0grp { |
| 300 | fsl,pins = < |
| 301 | VF610_PAD_PTB14__I2C0_SCL 0x37ff |
| 302 | VF610_PAD_PTB15__I2C0_SDA 0x37ff |
| 303 | >; |
| 304 | }; |
| 305 | |
| 306 | pinctrl_i2c1: i2c1grp { |
| 307 | fsl,pins = < |
| 308 | VF610_PAD_PTB16__I2C1_SCL 0x37ff |
| 309 | VF610_PAD_PTB17__I2C1_SDA 0x37ff |
| 310 | >; |
| 311 | }; |
| 312 | |
| 313 | pinctrl_leds_debug: pinctrl-leds-debug { |
| 314 | fsl,pins = < |
| 315 | VF610_PAD_PTD3__GPIO_82 0x31c2 |
| 316 | >; |
| 317 | }; |
| 318 | |
| 319 | pinctrl_uart0: uart0grp { |
| 320 | fsl,pins = < |
| 321 | VF610_PAD_PTB10__UART0_TX 0x21a2 |
| 322 | VF610_PAD_PTB11__UART0_RX 0x21a1 |
| 323 | >; |
| 324 | }; |
| 325 | }; |