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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / c5d9ae265b105d9a67575fb67bd4650a6fc08e25 / . / arch / arm / boot / dts / imx6dl-victgo.dts
blob: d37ba4ed847ddd3a7afdf59aa348b9894f567d96 [file] [log] [blame]
Oleksij Rempel7f8f6312021-01-11 11:18:55 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright (c) 2016 Protonic Holland
4 * Copyright (c) 2020 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix
5 */
6
7/dts-v1/;
8#include <dt-bindings/display/sdtv-standards.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/input/input.h>
11#include <dt-bindings/leds/common.h>
12#include <dt-bindings/media/tvp5150.h>
13#include <dt-bindings/sound/fsl-imx-audmux.h>
14#include "imx6dl.dtsi"
15
16/ {
17 model = "Kverneland TGO";
18 compatible = "kvg,victgo", "fsl,imx6dl";
19
20 chosen {
21 stdout-path = &uart4;
22 };
23
24 backlight: backlight {
25 compatible = "pwm-backlight";
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_backlight>;
28 pwms = <&pwm1 0 5000000 0>;
29 brightness-levels = <0 16 64 255>;
30 num-interpolated-steps = <16>;
31 default-brightness-level = <1>;
32 power-supply = <&reg_3v3>;
33 enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
34 };
35
36 connector {
37 compatible = "composite-video-connector";
38 label = "Composite0";
39 sdtv-standards = <SDTV_STD_PAL_B>;
40
41 port {
42 comp0_out: endpoint {
43 remote-endpoint = <&tvp5150_comp0_in>;
44 };
45 };
46 };
47
48 gpio-keys {
49 compatible = "gpio-keys";
50 pinctrl-names = "default";
51 pinctrl-0 = <&pinctrl_gpiokeys>;
52 autorepeat;
53
54 power {
55 label = "Power Button";
56 gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
57 linux,code = <KEY_POWER>;
58 wakeup-source;
59 };
60
61 enter {
62 label = "Rotary Key";
63 gpios = <&gpio2 05 GPIO_ACTIVE_LOW>;
64 linux,code = <KEY_ENTER>;
65 wakeup-source;
66 };
67 };
68
69 leds {
70 compatible = "gpio-leds";
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_leds>;
73
74 led-0 {
75 label = "debug0";
76 function = LED_FUNCTION_HEARTBEAT;
77 gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
78 linux,default-trigger = "heartbeat";
79 };
80
81 led-1 {
82 label = "debug1";
83 function = LED_FUNCTION_DISK;
84 gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
85 linux,default-trigger = "disk-activity";
86 };
87
88 led-2 {
89 label = "power_led";
90 function = LED_FUNCTION_POWER;
91 gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>;
92 default-state = "on";
93 };
94 };
95
96 panel {
97 compatible = "kyo,tcg121xglp";
98 backlight = <&backlight>;
99 power-supply = <&reg_3v3>;
100
101 port {
102 panel_in: endpoint {
103 remote-endpoint = <&lvds0_out>;
104 };
105 };
106 };
107
108 clk50m_phy: phy-clock {
109 compatible = "fixed-clock";
110 #clock-cells = <0>;
111 clock-frequency = <50000000>;
112 };
113
114 reg_1v8: regulator-1v8 {
115 compatible = "regulator-fixed";
116 regulator-name = "1v8";
117 regulator-min-microvolt = <1800000>;
118 regulator-max-microvolt = <1800000>;
119 };
120
121 reg_3v3: regulator-3v3 {
122 compatible = "regulator-fixed";
123 regulator-name = "3v3";
124 regulator-min-microvolt = <3300000>;
125 regulator-max-microvolt = <3300000>;
126 };
127
128 reg_h1_vbus: regulator-h1-vbus {
129 compatible = "regulator-fixed";
130 regulator-name = "h1-vbus";
131 regulator-min-microvolt = <5000000>;
132 regulator-max-microvolt = <5000000>;
133 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
134 enable-active-high;
135 };
136
137 reg_otg_vbus: regulator-otg-vbus {
138 compatible = "regulator-fixed";
139 regulator-name = "otg-vbus";
140 regulator-min-microvolt = <5000000>;
141 regulator-max-microvolt = <5000000>;
142 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
143 enable-active-high;
144 };
145
146 rotary-encoder {
147 compatible = "rotary-encoder";
148 pinctrl-0 = <&pinctrl_rotary_ch>;
149 gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>,
150 <&gpio2 4 GPIO_ACTIVE_HIGH>;
151 linux,axis = <REL_WHEEL>;
152 rotary-encoder,steps-per-period = <4>;
153 rotary-encoder,relative-axis;
154 rotary-encoder,rollover;
155 wakeup-source;
156 };
157
158 sound {
159 compatible = "simple-audio-card";
160 simple-audio-card,name = "prti6q-sgtl5000";
161 simple-audio-card,format = "i2s";
162 simple-audio-card,widgets =
163 "Microphone", "Microphone Jack",
164 "Line", "Line In Jack",
165 "Headphone", "Headphone Jack",
166 "Speaker", "External Speaker";
167 simple-audio-card,routing =
168 "MIC_IN", "Microphone Jack",
169 "LINE_IN", "Line In Jack",
170 "Headphone Jack", "HP_OUT",
171 "External Speaker", "LINE_OUT";
172
173 simple-audio-card,cpu {
174 sound-dai = <&ssi1>;
175 system-clock-frequency = <0>;
176 };
177
178 simple-audio-card,codec {
179 sound-dai = <&codec>;
180 bitclock-master;
181 frame-master;
182 };
183 };
184};
185
186&audmux {
187 pinctrl-names = "default";
188 pinctrl-0 = <&pinctrl_audmux>;
189 status = "okay";
190
191 mux-ssi1 {
192 fsl,audmux-port = <0>;
193 fsl,port-config = <
194 IMX_AUDMUX_V2_PTCR_SYN 0
195 IMX_AUDMUX_V2_PTCR_TFSEL(2) 0
196 IMX_AUDMUX_V2_PTCR_TCSEL(2) 0
197 IMX_AUDMUX_V2_PTCR_TFSDIR 0
198 IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2)
199 >;
200 };
201
202 mux-pins3 {
203 fsl,audmux-port = <2>;
204 fsl,port-config = <
205 IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0)
206 0 IMX_AUDMUX_V2_PDCR_TXRXEN
207 >;
208 };
209};
210
211&can1 {
212 pinctrl-names = "default";
213 pinctrl-0 = <&pinctrl_can1>;
214 status = "okay";
215};
216
217&can2 {
218 pinctrl-names = "default";
219 pinctrl-0 = <&pinctrl_can2>;
220 status = "okay";
221};
222
223&clks {
224 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>;
225 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
226};
227
228&ecspi1 {
229 cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
230 pinctrl-names = "default";
231 pinctrl-0 = <&pinctrl_ecspi1>;
232 status = "okay";
233
234 flash@0 {
235 compatible = "jedec,spi-nor";
236 reg = <0>;
237 spi-max-frequency = <20000000>;
238 };
239};
240
241&ecspi2 {
242 cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
243 pinctrl-names = "default";
244 pinctrl-0 = <&pinctrl_ecspi2>;
245 status = "okay";
246
247 touchscreen@0 {
248 compatible = "ti,tsc2046";
249 reg = <0>;
250 pinctrl-names = "default";
251 pinctrl-0 = <&pinctrl_touchscreen>;
252 spi-max-frequency = <200000>;
253 interrupts-extended = <&gpio5 8 IRQ_TYPE_EDGE_FALLING>;
254 pendown-gpio = <&gpio5 8 GPIO_ACTIVE_LOW>;
255 touchscreen-size-x = <800>;
256 touchscreen-size-y = <480>;
257 touchscreen-inverted-y;
258 touchscreen-max-pressure = <4095>;
259 ti,vref-delay-usecs = /bits/ 16 <100>;
260 ti,x-plate-ohms = /bits/ 16 <800>;
261 ti,y-plate-ohms = /bits/ 16 <300>;
262 wakeup-source;
263 };
264};
265
266&fec {
267 pinctrl-names = "default";
268 pinctrl-0 = <&pinctrl_enet>;
269 phy-mode = "rmii";
270 clocks = <&clks IMX6QDL_CLK_ENET>,
271 <&clks IMX6QDL_CLK_ENET>,
272 <&clk50m_phy>;
273 clock-names = "ipg", "ahb", "ptp";
274 phy-handle = <&rmii_phy>;
275 status = "okay";
276
277 mdio {
278 #address-cells = <1>;
279 #size-cells = <0>;
280
281 /* Microchip KSZ8081RNA PHY */
282 rmii_phy: ethernet-phy@0 {
283 reg = <0>;
284 interrupts-extended = <&gpio4 30 IRQ_TYPE_LEVEL_LOW>;
285 reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
286 reset-assert-us = <10000>;
287 reset-deassert-us = <300>;
288 };
289 };
290};
291
292&gpio1 {
293 gpio-line-names =
294 "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR",
295 "CAM2_MIRROR", "", "", "SMBALERT",
296 "DEBUG_0", "DEBUG_1", "", "", "", "", "", "",
297 "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK",
298 "SD1_DATA3", "", "",
299 "", "", "", "", "", "", "", "";
300};
301
302&gpio2 {
303 gpio-line-names =
304 "", "", "", "", "", "", "", "",
305 "REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "REV_ID4",
306 "BOARD_ID0", "BOARD_ID1", "BOARD_ID2",
307 "", "", "", "", "", "", "ISB_IN1", "ON_SWITCH",
308 "POWER_LED", "", "", "", "", "", "", "";
309};
310
311&gpio3 {
312 gpio-line-names =
313 "", "", "", "", "", "", "", "",
314 "", "", "", "", "", "", "", "",
315 "ECSPI1_SCLK", "ECSPI1_MISO", "ECSPI1_MOSI", "ECSPI1_SS1",
316 "CPU_ON1_FB", "USB_EXT1_OC", "USB_EXT1_PWR", "YACO_IRQ",
317 "TSS_TXD", "TSS_RXD", "", "", "", "", "YACO_BOOT0",
318 "YACO_RESET";
319};
320
321&gpio4 {
322 gpio-line-names =
323 "", "", "", "", "", "", "", "",
324 "", "", "", "", "CAN1_SR", "CAN2_SR", "CAN2_TX", "CAN2_RX",
325 "", "", "DIP1_FB", "", "VCAM_EN", "", "", "",
326 "CPU_LIGHT_ON", "", "ETH_RESET", "CPU_CONTACT_IN", "BL_EN",
327 "BL_PWM", "ETH_INTRP", "ISB_LED";
328};
329
330&gpio5 {
331 gpio-line-names =
332 "", "", "", "", "", "", "", "",
333 "TSC_PENIRQ", "TSC_BUSY", "ECSPI2_MOSI", "ECSPI2_MISO",
334 "ECSPI2_SS0", "ECSPI2_SCLK", "", "",
335 "", "", "", "", "", "", "", "",
336 "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX",
337 "YACO_AUX_TX", "ITU656_D0", "ITU656_D1";
338};
339
340&i2c1 {
341 clock-frequency = <100000>;
342 pinctrl-names = "default";
343 pinctrl-0 = <&pinctrl_i2c1>;
344 status = "okay";
345
346 codec: audio-codec@a {
347 compatible = "fsl,sgtl5000";
348 reg = <0xa>;
349 #sound-dai-cells = <0>;
350 clocks = <&clks 201>;
351 VDDA-supply = <&reg_3v3>;
352 VDDIO-supply = <&reg_3v3>;
353 VDDD-supply = <&reg_1v8>;
354 };
355
356 video-decoder@5c {
357 compatible = "ti,tvp5150";
358 reg = <0x5c>;
359 #address-cells = <1>;
360 #size-cells = <0>;
361
362 port@0 {
363 reg = <0>;
364
365 tvp5150_comp0_in: endpoint {
366 remote-endpoint = <&comp0_out>;
367 };
368 };
369
370 /* Output port 2 is video output pad */
371 port@2 {
372 reg = <2>;
373
374 tvp5151_to_ipu1_csi0_mux: endpoint {
375 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
376 };
377 };
378 };
379
380 keypad@70 {
381 compatible = "holtek,ht16k33";
382 pinctrl-names = "default";
383 pinctrl-0 = <&pinctrl_keypad>;
384 reg = <0x70>;
385 refresh-rate-hz = <20>;
386 debounce-delay-ms = <50>;
387 interrupts-extended = <&gpio4 5 (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)>;
388 keypad,num-rows = <12>;
389 keypad,num-columns = <3>;
390 linux,keymap = <
391 MATRIX_KEY(2, 0, KEY_F6)
392 MATRIX_KEY(3, 0, KEY_F8)
393 MATRIX_KEY(4, 0, KEY_F10)
394 MATRIX_KEY(5, 0, KEY_F4)
395 MATRIX_KEY(6, 0, KEY_F2)
396 MATRIX_KEY(2, 1, KEY_F5)
397 MATRIX_KEY(3, 1, KEY_F7)
398 MATRIX_KEY(4, 1, KEY_F9)
399 MATRIX_KEY(5, 1, KEY_F3)
400 MATRIX_KEY(6, 1, KEY_F1)
401 >;
402 };
403
404 /* additional i2c devices are added automatically by the boot loader */
405};
406
407&i2c3 {
408 clock-frequency = <100000>;
409 pinctrl-names = "default";
410 pinctrl-0 = <&pinctrl_i2c3>;
411 status = "okay";
412
413 adc@49 {
414 compatible = "ti,ads1015";
415 reg = <0x49>;
416 #address-cells = <1>;
417 #size-cells = <0>;
418
419 channel@4 {
420 reg = <4>;
421 ti,gain = <3>;
422 ti,datarate = <3>;
423 };
424
425 channel@5 {
426 reg = <5>;
427 ti,gain = <3>;
428 ti,datarate = <3>;
429 };
430
431 channel@6 {
432 reg = <6>;
433 ti,gain = <3>;
434 ti,datarate = <3>;
435 };
436
437 channel@7 {
438 reg = <7>;
439 ti,gain = <3>;
440 ti,datarate = <3>;
441 };
442 };
443
444 rtc@51 {
445 compatible = "nxp,pcf8563";
446 reg = <0x51>;
447 };
448
449 temperature-sensor@70 {
450 compatible = "ti,tmp103";
451 reg = <0x70>;
452 };
453};
454
455&ipu1_csi0 {
456 pinctrl-names = "default";
457 pinctrl-0 = <&pinctrl_ipu1_csi0>;
458 status = "okay";
459};
460
461&ipu1_csi0_mux_from_parallel_sensor {
462 remote-endpoint = <&tvp5151_to_ipu1_csi0_mux>;
463};
464
465&ldb {
466 status = "okay";
467
468 lvds-channel@0 {
469 status = "okay";
470
471 port@4 {
472 reg = <4>;
473
474 lvds0_out: endpoint {
475 remote-endpoint = <&panel_in>;
476 };
477 };
478 };
479};
480
481&pwm1 {
482 pinctrl-names = "default";
483 pinctrl-0 = <&pinctrl_pwm1>;
484 status = "okay";
485};
486
487&pwm3 {
488 pinctrl-names = "default";
489 pinctrl-0 = <&pinctrl_pwm3>;
490 status = "okay";
491};
492
493&ssi1 {
494 #sound-dai-cells = <0>;
495 fsl,mode = "ac97-slave";
496 status = "okay";
497};
498
499&uart1 {
500 pinctrl-names = "default";
501 pinctrl-0 = <&pinctrl_uart1>;
502 status = "okay";
503};
504
505&uart2 {
506 pinctrl-names = "default";
507 pinctrl-0 = <&pinctrl_uart2>;
508 status = "okay";
509};
510
511&uart3 {
512 pinctrl-names = "default";
513 pinctrl-0 = <&pinctrl_uart3>;
514 status = "okay";
515};
516
517&uart4 {
518 pinctrl-names = "default";
519 pinctrl-0 = <&pinctrl_uart4>;
520 status = "okay";
521};
522
523&uart5 {
524 pinctrl-names = "default";
525 pinctrl-0 = <&pinctrl_uart5>;
526 status = "okay";
527};
528
529&usbh1 {
530 vbus-supply = <&reg_h1_vbus>;
531 pinctrl-names = "default";
532 phy_type = "utmi";
533 dr_mode = "host";
534 status = "okay";
535};
536
537&usbotg {
538 vbus-supply = <&reg_otg_vbus>;
539 pinctrl-names = "default";
540 pinctrl-0 = <&pinctrl_usbotg>;
541 phy_type = "utmi";
542 dr_mode = "host";
543 disable-over-current;
544 status = "okay";
545};
546
547&usdhc1 {
548 pinctrl-names = "default";
549 pinctrl-0 = <&pinctrl_usdhc1>;
550 cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
551 no-1-8-v;
552 disable-wp;
553 cap-sd-highspeed;
554 no-mmc;
555 no-sdio;
556 status = "okay";
557};
558
559&usdhc3 {
560 pinctrl-names = "default";
561 pinctrl-0 = <&pinctrl_usdhc3>;
562 bus-width = <8>;
563 no-1-8-v;
564 non-removable;
565 no-sd;
566 no-sdio;
567 status = "okay";
568};
569
570&iomuxc {
571 pinctrl-names = "default";
572 pinctrl-0 = <&pinctrl_hog>;
573
574 pinctrl_audmux: audmuxgrp {
575 fsl,pins = <
576 /* SGTL5000 sys_mclk */
577 MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0
578 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
579 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
580 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
581 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
582 >;
583 };
584
585 pinctrl_backlight: backlightgrp {
586 fsl,pins = <
587 MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0
588 >;
589 };
590
591 pinctrl_can1: can1grp {
592 fsl,pins = <
593 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000
594 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008
595 /* CAN1_SR */
596 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008
597 /* CAN1_TERM */
598 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b088
599 >;
600 };
601
602 pinctrl_can2: can2grp {
603 fsl,pins = <
604 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000
605 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008
606 /* CAN2_SR */
607 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13008
608 >;
609 };
610
611 pinctrl_ecspi1: ecspi1grp {
612 fsl,pins = <
613 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
614 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
615 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
616 /* CS */
617 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1
618 >;
619 };
620
621 pinctrl_ecspi2: ecspi2grp {
622 fsl,pins = <
623 MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1
624 MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1
625 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1
626 MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1
627 >;
628 };
629
630 pinctrl_enet: enetgrp {
631 fsl,pins = <
632 /* MX6QDL_ENET_PINGRP4 */
633 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
634 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
635 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
636 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
637 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
638 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
639 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
640 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
641 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
642 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0
643 /* Phy reset */
644 MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0
645 /* nINTRP */
646 MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0
647 >;
648 };
649
650 pinctrl_gpiokeys: gpiokeygrp {
651 fsl,pins = <
652 /* ROTARY_BTN */
653 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b0
654 /* nON_SWITCH */
655 MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0
656 >;
657 };
658
659 pinctrl_hog: hoggrp {
660 fsl,pins = <
661 /* ITU656_nRESET */
662 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
663 /* CAM1_MIRROR */
664 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x130b0
665 /* CAM2_MIRROR */
666 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0
667 /* CAM_nDETECT */
668 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
669 /* ISB_IN1 */
670 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0
671 /* ISB_nIN2 */
672 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0
673 /* WARN_LIGHT */
674 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x100b0
675 /* ON2_FB */
676 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0
677 /* YACO_nIRQ */
678 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0
679 /* YACO_BOOT0 */
680 MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x130b0
681 /* YACO_nRESET */
682 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0
683 /* FORCE_ON1 */
684 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
685 /* AUDIO_nRESET */
686 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0
687 /* ITU656_nPDN */
688 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0
689
690 /* HW revision detect */
691 /* REV_ID0 */
692 MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0
693 /* REV_ID1 is shared with PWM3 */
694 /* REV_ID2 */
695 MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0
696 /* REV_ID3 */
697 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0
698 /* REV_ID4 */
699 MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0
700
701 /* New in HW revision 1 */
702 /* ON1_FB */
703 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0
704 /* DIP1_FB */
705 MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0
706 >;
707 };
708
709 pinctrl_i2c1: i2c1grp {
710 fsl,pins = <
711 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1
712 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1
713 >;
714 };
715
716 pinctrl_i2c3: i2c3grp {
717 fsl,pins = <
718 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
719 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
720 >;
721 };
722
723 pinctrl_ipu1_csi0: ipu1csi0grp {
724 fsl,pins = <
725 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
726 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
727 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
728 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
729 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
730 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
731 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
732 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
733 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
734 >;
735 };
736
737 pinctrl_keypad: keypadgrp {
738 fsl,pins = <
739 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
740 >;
741 };
742
743 pinctrl_leds: ledsgrp {
744 fsl,pins = <
745 /* DEBUG0 */
746 MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b0
747 /* DEBUG1 */
748 MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b0
749 /* POWER_LED */
750 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0
751 >;
752 };
753
754 pinctrl_pwm1: pwm1grp {
755 fsl,pins = <
756 MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0
757 >;
758 };
759
760 pinctrl_pwm3: pwm3grp {
761 fsl,pins = <
762 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b0
763 >;
764 };
765
766 pinctrl_rotary_ch: rotarychgrp {
767 fsl,pins = <
768 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
769 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
770 >;
771 };
772
773 pinctrl_touchscreen: touchscreengrp {
774 fsl,pins = <
775 MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b0
776 MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b0
777 >;
778 };
779
780 /* YaCO AUX Uart */
781 pinctrl_uart1: uart1grp {
782 fsl,pins = <
783 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
784 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
785 >;
786 };
787
788 pinctrl_uart2: uart2grp {
789 fsl,pins = <
790 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
791 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
792 >;
793 };
794
795 /* YaCO Touchscreen UART */
796 pinctrl_uart3: uart3grp {
797 fsl,pins = <
798 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
799 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
800 >;
801 };
802
803 pinctrl_uart4: uart4grp {
804 fsl,pins = <
805 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
806 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
807 >;
808 };
809
810 pinctrl_uart5: uart5grp {
811 fsl,pins = <
812 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
813 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
814 >;
815 };
816
817 pinctrl_usbotg: usbotggrp {
818 fsl,pins = <
819 MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0
820 /* power enable, high active */
821 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
822 >;
823 };
824
825 pinctrl_usdhc1: usdhc1grp {
826 fsl,pins = <
827 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9
828 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9
829 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
830 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
831 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
832 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
833 MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0
834 >;
835 };
836
837 pinctrl_usdhc3: usdhc3grp {
838 fsl,pins = <
839 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099
840 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099
841 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099
842 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099
843 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099
844 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099
845 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099
846 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099
847 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099
848 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099
849 MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1
850 >;
851 };
852};