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Vincent Chen6f4eea92021-03-22 22:26:03 +08001menu "CPU errata selection"
2
3config RISCV_ERRATA_ALTERNATIVE
4 bool "RISC-V alternative scheme"
5 default y
6 help
7 This Kconfig allows the kernel to automatically patch the
8 errata required by the execution platform at run time. The
9 code patching is performed once in the boot stages. It means
10 that the overhead from this mechanism is just taken once.
11
Vincent Chen1a0e5db2021-03-22 22:26:04 +080012config ERRATA_SIFIVE
13 bool "SiFive errata"
14 depends on RISCV_ERRATA_ALTERNATIVE
15 help
16 All SiFive errata Kconfig depend on this Kconfig. Disabling
17 this Kconfig will disable all SiFive errata. Please say "Y"
18 here if your platform uses SiFive CPU cores.
19
20 Otherwise, please say "N" here to avoid unnecessary overhead.
21
Vincent Chen800149a2021-03-22 22:26:05 +080022config ERRATA_SIFIVE_CIP_453
23 bool "Apply SiFive errata CIP-453"
Vincent Chen0e0d4992021-04-29 00:58:36 -070024 depends on ERRATA_SIFIVE && 64BIT
Vincent Chen800149a2021-03-22 22:26:05 +080025 default y
26 help
27 This will apply the SiFive CIP-453 errata to add sign extension
28 to the $badaddr when exception type is instruction page fault
29 and instruction access fault.
30
31 If you don't know what to do here, say "Y".
32
Vincent Chenbff3ff52021-03-22 22:26:06 +080033config ERRATA_SIFIVE_CIP_1200
34 bool "Apply SiFive errata CIP-1200"
Vincent Chen0e0d4992021-04-29 00:58:36 -070035 depends on ERRATA_SIFIVE && 64BIT
Vincent Chenbff3ff52021-03-22 22:26:06 +080036 default y
37 help
38 This will apply the SiFive CIP-1200 errata to repalce all
39 "sfence.vma addr" with "sfence.vma" to ensure that the addr
40 has been flushed from TLB.
41
42 If you don't know what to do here, say "Y".
43
Vincent Chen6f4eea92021-03-22 22:26:03 +080044endmenu