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Adam Baker630300d2016-03-05 15:34:56 +00001Kernel driver nsa320_hwmon
2==========================
3
4Supported chips:
Mauro Carvalho Chehabb04f2f72019-04-17 06:46:28 -03005
Adam Baker630300d2016-03-05 15:34:56 +00006 * Holtek HT46R065 microcontroller with onboard firmware that configures
Mauro Carvalho Chehabb04f2f72019-04-17 06:46:28 -03007
Adam Baker630300d2016-03-05 15:34:56 +00008 it to act as a hardware monitor.
Mauro Carvalho Chehabb04f2f72019-04-17 06:46:28 -03009
Adam Baker630300d2016-03-05 15:34:56 +000010 Prefix: 'nsa320'
Mauro Carvalho Chehabb04f2f72019-04-17 06:46:28 -030011
Adam Baker630300d2016-03-05 15:34:56 +000012 Addresses scanned: none
Mauro Carvalho Chehabb04f2f72019-04-17 06:46:28 -030013
Adam Baker630300d2016-03-05 15:34:56 +000014 Datasheet: Not available, driver was reverse engineered based upon the
Mauro Carvalho Chehabb04f2f72019-04-17 06:46:28 -030015
Adam Baker630300d2016-03-05 15:34:56 +000016 Zyxel kernel source
17
Mauro Carvalho Chehabb04f2f72019-04-17 06:46:28 -030018
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Adam Baker630300d2016-03-05 15:34:56 +000020Author:
Mauro Carvalho Chehabb04f2f72019-04-17 06:46:28 -030021
Adam Baker630300d2016-03-05 15:34:56 +000022 Adam Baker <linux@baker-net.org.uk>
23
24Description
25-----------
26
27This chip is known to be used in the Zyxel NSA320 and NSA325 NAS Units and
28also in some variants of the NSA310 but the driver has only been tested
29on the NSA320. In all of these devices it is connected to the same 3 GPIO
30lines which are used to provide chip select, clock and data lines. The
31interface behaves similarly to SPI but at much lower speeds than are normally
32used for SPI.
33
34Following each chip select pulse the chip will generate a single 32 bit word
35that contains 0x55 as a marker to indicate that data is being read correctly,
36followed by an 8 bit fan speed in 100s of RPM and a 16 bit temperature in
37tenths of a degree.
38
39
40sysfs-Interface
41---------------
42
Mauro Carvalho Chehabb04f2f72019-04-17 06:46:28 -030043============= =================
44temp1_input temperature input
45fan1_input fan speed
46============= =================
Adam Baker630300d2016-03-05 15:34:56 +000047
48Notes
49-----
50
51The access timings used in the driver are the same as used in the Zyxel
52provided kernel. Testing has shown that if the delay between chip select and
53the first clock pulse is reduced from 100 ms to just under 10ms then the chip
54will not produce any output. If the duration of either phase of the clock
55is reduced from 100 us to less than 15 us then data pulses are likely to be
56read twice corrupting the output. The above analysis is based upon a sample
57of one unit but suggests that the Zyxel provided delay values include a
58reasonable tolerance.
59
60The driver incorporates a limit that it will not check for updated values
61faster than once a second. This is because the hardware takes a relatively long
62time to read the data from the device and when it does it reads both temp and
63fan speed. As the most likely case for two accesses in quick succession is
64to read both of these values avoiding a second read delay is desirable.