Adam Baker | 630300d | 2016-03-05 15:34:56 +0000 | [diff] [blame] | 1 | Kernel driver nsa320_hwmon |
| 2 | ========================== |
| 3 | |
| 4 | Supported chips: |
Mauro Carvalho Chehab | b04f2f7 | 2019-04-17 06:46:28 -0300 | [diff] [blame] | 5 | |
Adam Baker | 630300d | 2016-03-05 15:34:56 +0000 | [diff] [blame] | 6 | * Holtek HT46R065 microcontroller with onboard firmware that configures |
Mauro Carvalho Chehab | b04f2f7 | 2019-04-17 06:46:28 -0300 | [diff] [blame] | 7 | |
Adam Baker | 630300d | 2016-03-05 15:34:56 +0000 | [diff] [blame] | 8 | it to act as a hardware monitor. |
Mauro Carvalho Chehab | b04f2f7 | 2019-04-17 06:46:28 -0300 | [diff] [blame] | 9 | |
Adam Baker | 630300d | 2016-03-05 15:34:56 +0000 | [diff] [blame] | 10 | Prefix: 'nsa320' |
Mauro Carvalho Chehab | b04f2f7 | 2019-04-17 06:46:28 -0300 | [diff] [blame] | 11 | |
Adam Baker | 630300d | 2016-03-05 15:34:56 +0000 | [diff] [blame] | 12 | Addresses scanned: none |
Mauro Carvalho Chehab | b04f2f7 | 2019-04-17 06:46:28 -0300 | [diff] [blame] | 13 | |
Adam Baker | 630300d | 2016-03-05 15:34:56 +0000 | [diff] [blame] | 14 | Datasheet: Not available, driver was reverse engineered based upon the |
Mauro Carvalho Chehab | b04f2f7 | 2019-04-17 06:46:28 -0300 | [diff] [blame] | 15 | |
Adam Baker | 630300d | 2016-03-05 15:34:56 +0000 | [diff] [blame] | 16 | Zyxel kernel source |
| 17 | |
Mauro Carvalho Chehab | b04f2f7 | 2019-04-17 06:46:28 -0300 | [diff] [blame] | 18 | |
| 19 | |
Adam Baker | 630300d | 2016-03-05 15:34:56 +0000 | [diff] [blame] | 20 | Author: |
Mauro Carvalho Chehab | b04f2f7 | 2019-04-17 06:46:28 -0300 | [diff] [blame] | 21 | |
Adam Baker | 630300d | 2016-03-05 15:34:56 +0000 | [diff] [blame] | 22 | Adam Baker <linux@baker-net.org.uk> |
| 23 | |
| 24 | Description |
| 25 | ----------- |
| 26 | |
| 27 | This chip is known to be used in the Zyxel NSA320 and NSA325 NAS Units and |
| 28 | also in some variants of the NSA310 but the driver has only been tested |
| 29 | on the NSA320. In all of these devices it is connected to the same 3 GPIO |
| 30 | lines which are used to provide chip select, clock and data lines. The |
| 31 | interface behaves similarly to SPI but at much lower speeds than are normally |
| 32 | used for SPI. |
| 33 | |
| 34 | Following each chip select pulse the chip will generate a single 32 bit word |
| 35 | that contains 0x55 as a marker to indicate that data is being read correctly, |
| 36 | followed by an 8 bit fan speed in 100s of RPM and a 16 bit temperature in |
| 37 | tenths of a degree. |
| 38 | |
| 39 | |
| 40 | sysfs-Interface |
| 41 | --------------- |
| 42 | |
Mauro Carvalho Chehab | b04f2f7 | 2019-04-17 06:46:28 -0300 | [diff] [blame] | 43 | ============= ================= |
| 44 | temp1_input temperature input |
| 45 | fan1_input fan speed |
| 46 | ============= ================= |
Adam Baker | 630300d | 2016-03-05 15:34:56 +0000 | [diff] [blame] | 47 | |
| 48 | Notes |
| 49 | ----- |
| 50 | |
| 51 | The access timings used in the driver are the same as used in the Zyxel |
| 52 | provided kernel. Testing has shown that if the delay between chip select and |
| 53 | the first clock pulse is reduced from 100 ms to just under 10ms then the chip |
| 54 | will not produce any output. If the duration of either phase of the clock |
| 55 | is reduced from 100 us to less than 15 us then data pulses are likely to be |
| 56 | read twice corrupting the output. The above analysis is based upon a sample |
| 57 | of one unit but suggests that the Zyxel provided delay values include a |
| 58 | reasonable tolerance. |
| 59 | |
| 60 | The driver incorporates a limit that it will not check for updated values |
| 61 | faster than once a second. This is because the hardware takes a relatively long |
| 62 | time to read the data from the device and when it does it reads both temp and |
| 63 | fan speed. As the most likely case for two accesses in quick succession is |
| 64 | to read both of these values avoiding a second read delay is desirable. |