Bjorn Helgaas | 8cfab3c | 2018-01-26 12:50:27 -0600 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 2 | /** |
Bjorn Helgaas | 96291d5 | 2017-09-01 16:35:50 -0500 | [diff] [blame] | 3 | * Synopsys DesignWare PCIe Endpoint controller driver |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 4 | * |
| 5 | * Copyright (C) 2017 Texas Instruments |
| 6 | * Author: Kishon Vijay Abraham I <kishon@ti.com> |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #include <linux/of.h> |
| 10 | |
| 11 | #include "pcie-designware.h" |
| 12 | #include <linux/pci-epc.h> |
| 13 | #include <linux/pci-epf.h> |
| 14 | |
| 15 | void dw_pcie_ep_linkup(struct dw_pcie_ep *ep) |
| 16 | { |
| 17 | struct pci_epc *epc = ep->epc; |
| 18 | |
| 19 | pci_epc_linkup(epc); |
| 20 | } |
| 21 | |
Niklas Cassel | 77d08db | 2018-03-28 13:50:14 +0200 | [diff] [blame] | 22 | static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar, |
| 23 | int flags) |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 24 | { |
| 25 | u32 reg; |
| 26 | |
| 27 | reg = PCI_BASE_ADDRESS_0 + (4 * bar); |
Niklas Cassel | 1cab826 | 2017-12-20 00:29:24 +0100 | [diff] [blame] | 28 | dw_pcie_dbi_ro_wr_en(pci); |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 29 | dw_pcie_writel_dbi2(pci, reg, 0x0); |
| 30 | dw_pcie_writel_dbi(pci, reg, 0x0); |
Niklas Cassel | 96a3be4 | 2018-03-28 13:50:16 +0200 | [diff] [blame] | 31 | if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) { |
| 32 | dw_pcie_writel_dbi2(pci, reg + 4, 0x0); |
| 33 | dw_pcie_writel_dbi(pci, reg + 4, 0x0); |
| 34 | } |
Niklas Cassel | 1cab826 | 2017-12-20 00:29:24 +0100 | [diff] [blame] | 35 | dw_pcie_dbi_ro_wr_dis(pci); |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 36 | } |
| 37 | |
Niklas Cassel | 77d08db | 2018-03-28 13:50:14 +0200 | [diff] [blame] | 38 | void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar) |
| 39 | { |
| 40 | __dw_pcie_ep_reset_bar(pci, bar, 0); |
| 41 | } |
| 42 | |
Gustavo Pimentel | beb4641 | 2018-07-19 10:32:14 +0200 | [diff] [blame] | 43 | static u8 __dw_pcie_ep_find_next_cap(struct dw_pcie *pci, u8 cap_ptr, |
| 44 | u8 cap) |
| 45 | { |
| 46 | u8 cap_id, next_cap_ptr; |
| 47 | u16 reg; |
| 48 | |
| 49 | reg = dw_pcie_readw_dbi(pci, cap_ptr); |
| 50 | next_cap_ptr = (reg & 0xff00) >> 8; |
| 51 | cap_id = (reg & 0x00ff); |
| 52 | |
| 53 | if (!next_cap_ptr || cap_id > PCI_CAP_ID_MAX) |
| 54 | return 0; |
| 55 | |
| 56 | if (cap_id == cap) |
| 57 | return cap_ptr; |
| 58 | |
| 59 | return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap); |
| 60 | } |
| 61 | |
| 62 | static u8 dw_pcie_ep_find_capability(struct dw_pcie *pci, u8 cap) |
| 63 | { |
| 64 | u8 next_cap_ptr; |
| 65 | u16 reg; |
| 66 | |
| 67 | reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST); |
| 68 | next_cap_ptr = (reg & 0x00ff); |
| 69 | |
| 70 | if (!next_cap_ptr) |
| 71 | return 0; |
| 72 | |
| 73 | return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap); |
| 74 | } |
| 75 | |
Cyrille Pitchen | 4494738 | 2018-01-30 21:56:56 +0100 | [diff] [blame] | 76 | static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no, |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 77 | struct pci_epf_header *hdr) |
| 78 | { |
| 79 | struct dw_pcie_ep *ep = epc_get_drvdata(epc); |
| 80 | struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
| 81 | |
Niklas Cassel | 1cab826 | 2017-12-20 00:29:24 +0100 | [diff] [blame] | 82 | dw_pcie_dbi_ro_wr_en(pci); |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 83 | dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, hdr->vendorid); |
| 84 | dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, hdr->deviceid); |
| 85 | dw_pcie_writeb_dbi(pci, PCI_REVISION_ID, hdr->revid); |
| 86 | dw_pcie_writeb_dbi(pci, PCI_CLASS_PROG, hdr->progif_code); |
| 87 | dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE, |
| 88 | hdr->subclass_code | hdr->baseclass_code << 8); |
| 89 | dw_pcie_writeb_dbi(pci, PCI_CACHE_LINE_SIZE, |
| 90 | hdr->cache_line_size); |
| 91 | dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_VENDOR_ID, |
| 92 | hdr->subsys_vendor_id); |
| 93 | dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_ID, hdr->subsys_id); |
| 94 | dw_pcie_writeb_dbi(pci, PCI_INTERRUPT_PIN, |
| 95 | hdr->interrupt_pin); |
Niklas Cassel | 1cab826 | 2017-12-20 00:29:24 +0100 | [diff] [blame] | 96 | dw_pcie_dbi_ro_wr_dis(pci); |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 97 | |
| 98 | return 0; |
| 99 | } |
| 100 | |
| 101 | static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, enum pci_barno bar, |
| 102 | dma_addr_t cpu_addr, |
| 103 | enum dw_pcie_as_type as_type) |
| 104 | { |
| 105 | int ret; |
| 106 | u32 free_win; |
| 107 | struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
| 108 | |
Niklas Cassel | ad4a5be | 2017-12-14 14:01:44 +0100 | [diff] [blame] | 109 | free_win = find_first_zero_bit(ep->ib_window_map, ep->num_ib_windows); |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 110 | if (free_win >= ep->num_ib_windows) { |
Gustavo Pimentel | b4a8a51 | 2018-05-14 16:09:48 +0100 | [diff] [blame] | 111 | dev_err(pci->dev, "No free inbound window\n"); |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 112 | return -EINVAL; |
| 113 | } |
| 114 | |
| 115 | ret = dw_pcie_prog_inbound_atu(pci, free_win, bar, cpu_addr, |
| 116 | as_type); |
| 117 | if (ret < 0) { |
| 118 | dev_err(pci->dev, "Failed to program IB window\n"); |
| 119 | return ret; |
| 120 | } |
| 121 | |
| 122 | ep->bar_to_atu[bar] = free_win; |
Niklas Cassel | ad4a5be | 2017-12-14 14:01:44 +0100 | [diff] [blame] | 123 | set_bit(free_win, ep->ib_window_map); |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 124 | |
| 125 | return 0; |
| 126 | } |
| 127 | |
| 128 | static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, phys_addr_t phys_addr, |
| 129 | u64 pci_addr, size_t size) |
| 130 | { |
| 131 | u32 free_win; |
| 132 | struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
| 133 | |
Niklas Cassel | ad4a5be | 2017-12-14 14:01:44 +0100 | [diff] [blame] | 134 | free_win = find_first_zero_bit(ep->ob_window_map, ep->num_ob_windows); |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 135 | if (free_win >= ep->num_ob_windows) { |
Gustavo Pimentel | b4a8a51 | 2018-05-14 16:09:48 +0100 | [diff] [blame] | 136 | dev_err(pci->dev, "No free outbound window\n"); |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 137 | return -EINVAL; |
| 138 | } |
| 139 | |
| 140 | dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM, |
| 141 | phys_addr, pci_addr, size); |
| 142 | |
Niklas Cassel | ad4a5be | 2017-12-14 14:01:44 +0100 | [diff] [blame] | 143 | set_bit(free_win, ep->ob_window_map); |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 144 | ep->outbound_addr[free_win] = phys_addr; |
| 145 | |
| 146 | return 0; |
| 147 | } |
| 148 | |
Cyrille Pitchen | 4494738 | 2018-01-30 21:56:56 +0100 | [diff] [blame] | 149 | static void dw_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no, |
Niklas Cassel | 77d08db | 2018-03-28 13:50:14 +0200 | [diff] [blame] | 150 | struct pci_epf_bar *epf_bar) |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 151 | { |
| 152 | struct dw_pcie_ep *ep = epc_get_drvdata(epc); |
| 153 | struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
Niklas Cassel | 77d08db | 2018-03-28 13:50:14 +0200 | [diff] [blame] | 154 | enum pci_barno bar = epf_bar->barno; |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 155 | u32 atu_index = ep->bar_to_atu[bar]; |
| 156 | |
Niklas Cassel | 77d08db | 2018-03-28 13:50:14 +0200 | [diff] [blame] | 157 | __dw_pcie_ep_reset_bar(pci, bar, epf_bar->flags); |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 158 | |
| 159 | dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_INBOUND); |
Niklas Cassel | ad4a5be | 2017-12-14 14:01:44 +0100 | [diff] [blame] | 160 | clear_bit(atu_index, ep->ib_window_map); |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 161 | } |
| 162 | |
Cyrille Pitchen | 4494738 | 2018-01-30 21:56:56 +0100 | [diff] [blame] | 163 | static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, |
Niklas Cassel | bc4a489 | 2018-03-28 13:50:07 +0200 | [diff] [blame] | 164 | struct pci_epf_bar *epf_bar) |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 165 | { |
| 166 | int ret; |
| 167 | struct dw_pcie_ep *ep = epc_get_drvdata(epc); |
| 168 | struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
Niklas Cassel | bc4a489 | 2018-03-28 13:50:07 +0200 | [diff] [blame] | 169 | enum pci_barno bar = epf_bar->barno; |
| 170 | size_t size = epf_bar->size; |
| 171 | int flags = epf_bar->flags; |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 172 | enum dw_pcie_as_type as_type; |
| 173 | u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar); |
| 174 | |
| 175 | if (!(flags & PCI_BASE_ADDRESS_SPACE)) |
| 176 | as_type = DW_PCIE_AS_MEM; |
| 177 | else |
| 178 | as_type = DW_PCIE_AS_IO; |
| 179 | |
Niklas Cassel | bc4a489 | 2018-03-28 13:50:07 +0200 | [diff] [blame] | 180 | ret = dw_pcie_ep_inbound_atu(ep, bar, epf_bar->phys_addr, as_type); |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 181 | if (ret) |
| 182 | return ret; |
| 183 | |
Niklas Cassel | 1cab826 | 2017-12-20 00:29:24 +0100 | [diff] [blame] | 184 | dw_pcie_dbi_ro_wr_en(pci); |
Niklas Cassel | d28810b | 2018-03-28 13:50:11 +0200 | [diff] [blame] | 185 | |
| 186 | dw_pcie_writel_dbi2(pci, reg, lower_32_bits(size - 1)); |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 187 | dw_pcie_writel_dbi(pci, reg, flags); |
Niklas Cassel | d28810b | 2018-03-28 13:50:11 +0200 | [diff] [blame] | 188 | |
| 189 | if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) { |
| 190 | dw_pcie_writel_dbi2(pci, reg + 4, upper_32_bits(size - 1)); |
| 191 | dw_pcie_writel_dbi(pci, reg + 4, 0); |
| 192 | } |
| 193 | |
Niklas Cassel | 1cab826 | 2017-12-20 00:29:24 +0100 | [diff] [blame] | 194 | dw_pcie_dbi_ro_wr_dis(pci); |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 195 | |
| 196 | return 0; |
| 197 | } |
| 198 | |
| 199 | static int dw_pcie_find_index(struct dw_pcie_ep *ep, phys_addr_t addr, |
| 200 | u32 *atu_index) |
| 201 | { |
| 202 | u32 index; |
| 203 | |
| 204 | for (index = 0; index < ep->num_ob_windows; index++) { |
| 205 | if (ep->outbound_addr[index] != addr) |
| 206 | continue; |
| 207 | *atu_index = index; |
| 208 | return 0; |
| 209 | } |
| 210 | |
| 211 | return -EINVAL; |
| 212 | } |
| 213 | |
Cyrille Pitchen | 4494738 | 2018-01-30 21:56:56 +0100 | [diff] [blame] | 214 | static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, u8 func_no, |
| 215 | phys_addr_t addr) |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 216 | { |
| 217 | int ret; |
| 218 | u32 atu_index; |
| 219 | struct dw_pcie_ep *ep = epc_get_drvdata(epc); |
| 220 | struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
| 221 | |
| 222 | ret = dw_pcie_find_index(ep, addr, &atu_index); |
| 223 | if (ret < 0) |
| 224 | return; |
| 225 | |
| 226 | dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_OUTBOUND); |
Niklas Cassel | ad4a5be | 2017-12-14 14:01:44 +0100 | [diff] [blame] | 227 | clear_bit(atu_index, ep->ob_window_map); |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 228 | } |
| 229 | |
Cyrille Pitchen | 4494738 | 2018-01-30 21:56:56 +0100 | [diff] [blame] | 230 | static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, |
| 231 | phys_addr_t addr, |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 232 | u64 pci_addr, size_t size) |
| 233 | { |
| 234 | int ret; |
| 235 | struct dw_pcie_ep *ep = epc_get_drvdata(epc); |
| 236 | struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
| 237 | |
| 238 | ret = dw_pcie_ep_outbound_atu(ep, addr, pci_addr, size); |
| 239 | if (ret) { |
Gustavo Pimentel | b4a8a51 | 2018-05-14 16:09:48 +0100 | [diff] [blame] | 240 | dev_err(pci->dev, "Failed to enable address\n"); |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 241 | return ret; |
| 242 | } |
| 243 | |
| 244 | return 0; |
| 245 | } |
| 246 | |
Cyrille Pitchen | 4494738 | 2018-01-30 21:56:56 +0100 | [diff] [blame] | 247 | static int dw_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no) |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 248 | { |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 249 | struct dw_pcie_ep *ep = epc_get_drvdata(epc); |
| 250 | struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
Gustavo Pimentel | 3920a5d | 2018-07-19 10:32:15 +0200 | [diff] [blame] | 251 | u32 val, reg; |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 252 | |
Gustavo Pimentel | 3920a5d | 2018-07-19 10:32:15 +0200 | [diff] [blame] | 253 | if (!ep->msi_cap) |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 254 | return -EINVAL; |
| 255 | |
Gustavo Pimentel | 3920a5d | 2018-07-19 10:32:15 +0200 | [diff] [blame] | 256 | reg = ep->msi_cap + PCI_MSI_FLAGS; |
| 257 | val = dw_pcie_readw_dbi(pci, reg); |
| 258 | if (!(val & PCI_MSI_FLAGS_ENABLE)) |
| 259 | return -EINVAL; |
| 260 | |
| 261 | val = (val & PCI_MSI_FLAGS_QSIZE) >> 4; |
| 262 | |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 263 | return val; |
| 264 | } |
| 265 | |
Gustavo Pimentel | 3920a5d | 2018-07-19 10:32:15 +0200 | [diff] [blame] | 266 | static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts) |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 267 | { |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 268 | struct dw_pcie_ep *ep = epc_get_drvdata(epc); |
| 269 | struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
Gustavo Pimentel | 3920a5d | 2018-07-19 10:32:15 +0200 | [diff] [blame] | 270 | u32 val, reg; |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 271 | |
Gustavo Pimentel | 3920a5d | 2018-07-19 10:32:15 +0200 | [diff] [blame] | 272 | if (!ep->msi_cap) |
| 273 | return -EINVAL; |
| 274 | |
| 275 | reg = ep->msi_cap + PCI_MSI_FLAGS; |
| 276 | val = dw_pcie_readw_dbi(pci, reg); |
| 277 | val &= ~PCI_MSI_FLAGS_QMASK; |
| 278 | val |= (interrupts << 1) & PCI_MSI_FLAGS_QMASK; |
Niklas Cassel | 1cab826 | 2017-12-20 00:29:24 +0100 | [diff] [blame] | 279 | dw_pcie_dbi_ro_wr_en(pci); |
Gustavo Pimentel | 3920a5d | 2018-07-19 10:32:15 +0200 | [diff] [blame] | 280 | dw_pcie_writew_dbi(pci, reg, val); |
Niklas Cassel | 1cab826 | 2017-12-20 00:29:24 +0100 | [diff] [blame] | 281 | dw_pcie_dbi_ro_wr_dis(pci); |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 282 | |
| 283 | return 0; |
| 284 | } |
| 285 | |
Gustavo Pimentel | beb4641 | 2018-07-19 10:32:14 +0200 | [diff] [blame] | 286 | static int dw_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no) |
| 287 | { |
| 288 | struct dw_pcie_ep *ep = epc_get_drvdata(epc); |
| 289 | struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
| 290 | u32 val, reg; |
| 291 | |
| 292 | if (!ep->msix_cap) |
| 293 | return -EINVAL; |
| 294 | |
| 295 | reg = ep->msix_cap + PCI_MSIX_FLAGS; |
| 296 | val = dw_pcie_readw_dbi(pci, reg); |
| 297 | if (!(val & PCI_MSIX_FLAGS_ENABLE)) |
| 298 | return -EINVAL; |
| 299 | |
| 300 | val &= PCI_MSIX_FLAGS_QSIZE; |
| 301 | |
| 302 | return val; |
| 303 | } |
| 304 | |
| 305 | static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts) |
| 306 | { |
| 307 | struct dw_pcie_ep *ep = epc_get_drvdata(epc); |
| 308 | struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
| 309 | u32 val, reg; |
| 310 | |
| 311 | if (!ep->msix_cap) |
| 312 | return -EINVAL; |
| 313 | |
| 314 | reg = ep->msix_cap + PCI_MSIX_FLAGS; |
| 315 | val = dw_pcie_readw_dbi(pci, reg); |
| 316 | val &= ~PCI_MSIX_FLAGS_QSIZE; |
| 317 | val |= interrupts; |
| 318 | dw_pcie_dbi_ro_wr_en(pci); |
| 319 | dw_pcie_writew_dbi(pci, reg, val); |
| 320 | dw_pcie_dbi_ro_wr_dis(pci); |
| 321 | |
| 322 | return 0; |
| 323 | } |
| 324 | |
Cyrille Pitchen | 4494738 | 2018-01-30 21:56:56 +0100 | [diff] [blame] | 325 | static int dw_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no, |
Gustavo Pimentel | d3c70a9 | 2018-07-19 10:32:13 +0200 | [diff] [blame] | 326 | enum pci_epc_irq_type type, u16 interrupt_num) |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 327 | { |
| 328 | struct dw_pcie_ep *ep = epc_get_drvdata(epc); |
| 329 | |
| 330 | if (!ep->ops->raise_irq) |
| 331 | return -EINVAL; |
| 332 | |
Bjorn Helgaas | 1609336 | 2018-02-01 11:36:07 -0600 | [diff] [blame] | 333 | return ep->ops->raise_irq(ep, func_no, type, interrupt_num); |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 334 | } |
| 335 | |
| 336 | static void dw_pcie_ep_stop(struct pci_epc *epc) |
| 337 | { |
| 338 | struct dw_pcie_ep *ep = epc_get_drvdata(epc); |
| 339 | struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
| 340 | |
| 341 | if (!pci->ops->stop_link) |
| 342 | return; |
| 343 | |
| 344 | pci->ops->stop_link(pci); |
| 345 | } |
| 346 | |
| 347 | static int dw_pcie_ep_start(struct pci_epc *epc) |
| 348 | { |
| 349 | struct dw_pcie_ep *ep = epc_get_drvdata(epc); |
| 350 | struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
| 351 | |
| 352 | if (!pci->ops->start_link) |
| 353 | return -EINVAL; |
| 354 | |
| 355 | return pci->ops->start_link(pci); |
| 356 | } |
| 357 | |
Kishon Vijay Abraham I | fee35cb | 2019-01-14 16:45:00 +0530 | [diff] [blame] | 358 | static const struct pci_epc_features* |
| 359 | dw_pcie_ep_get_features(struct pci_epc *epc, u8 func_no) |
| 360 | { |
| 361 | struct dw_pcie_ep *ep = epc_get_drvdata(epc); |
| 362 | |
| 363 | if (!ep->ops->get_features) |
| 364 | return NULL; |
| 365 | |
| 366 | return ep->ops->get_features(ep); |
| 367 | } |
| 368 | |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 369 | static const struct pci_epc_ops epc_ops = { |
| 370 | .write_header = dw_pcie_ep_write_header, |
| 371 | .set_bar = dw_pcie_ep_set_bar, |
| 372 | .clear_bar = dw_pcie_ep_clear_bar, |
| 373 | .map_addr = dw_pcie_ep_map_addr, |
| 374 | .unmap_addr = dw_pcie_ep_unmap_addr, |
| 375 | .set_msi = dw_pcie_ep_set_msi, |
| 376 | .get_msi = dw_pcie_ep_get_msi, |
Gustavo Pimentel | beb4641 | 2018-07-19 10:32:14 +0200 | [diff] [blame] | 377 | .set_msix = dw_pcie_ep_set_msix, |
| 378 | .get_msix = dw_pcie_ep_get_msix, |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 379 | .raise_irq = dw_pcie_ep_raise_irq, |
| 380 | .start = dw_pcie_ep_start, |
| 381 | .stop = dw_pcie_ep_stop, |
Kishon Vijay Abraham I | fee35cb | 2019-01-14 16:45:00 +0530 | [diff] [blame] | 382 | .get_features = dw_pcie_ep_get_features, |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 383 | }; |
| 384 | |
Gustavo Pimentel | cb22d40 | 2018-07-19 10:32:16 +0200 | [diff] [blame] | 385 | int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no) |
| 386 | { |
| 387 | struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
| 388 | struct device *dev = pci->dev; |
| 389 | |
| 390 | dev_err(dev, "EP cannot trigger legacy IRQs\n"); |
| 391 | |
| 392 | return -EINVAL; |
| 393 | } |
| 394 | |
Bjorn Helgaas | 1609336 | 2018-02-01 11:36:07 -0600 | [diff] [blame] | 395 | int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, |
Niklas Cassel | 6f6d787 | 2017-12-20 00:29:27 +0100 | [diff] [blame] | 396 | u8 interrupt_num) |
| 397 | { |
| 398 | struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
| 399 | struct pci_epc *epc = ep->epc; |
| 400 | u16 msg_ctrl, msg_data; |
Gustavo Pimentel | 3920a5d | 2018-07-19 10:32:15 +0200 | [diff] [blame] | 401 | u32 msg_addr_lower, msg_addr_upper, reg; |
Niklas Cassel | 6f6d787 | 2017-12-20 00:29:27 +0100 | [diff] [blame] | 402 | u64 msg_addr; |
| 403 | bool has_upper; |
| 404 | int ret; |
| 405 | |
Gustavo Pimentel | 3920a5d | 2018-07-19 10:32:15 +0200 | [diff] [blame] | 406 | if (!ep->msi_cap) |
| 407 | return -EINVAL; |
| 408 | |
Niklas Cassel | 6f6d787 | 2017-12-20 00:29:27 +0100 | [diff] [blame] | 409 | /* Raise MSI per the PCI Local Bus Specification Revision 3.0, 6.8.1. */ |
Gustavo Pimentel | 3920a5d | 2018-07-19 10:32:15 +0200 | [diff] [blame] | 410 | reg = ep->msi_cap + PCI_MSI_FLAGS; |
| 411 | msg_ctrl = dw_pcie_readw_dbi(pci, reg); |
Niklas Cassel | 6f6d787 | 2017-12-20 00:29:27 +0100 | [diff] [blame] | 412 | has_upper = !!(msg_ctrl & PCI_MSI_FLAGS_64BIT); |
Gustavo Pimentel | 3920a5d | 2018-07-19 10:32:15 +0200 | [diff] [blame] | 413 | reg = ep->msi_cap + PCI_MSI_ADDRESS_LO; |
| 414 | msg_addr_lower = dw_pcie_readl_dbi(pci, reg); |
Niklas Cassel | 6f6d787 | 2017-12-20 00:29:27 +0100 | [diff] [blame] | 415 | if (has_upper) { |
Gustavo Pimentel | 3920a5d | 2018-07-19 10:32:15 +0200 | [diff] [blame] | 416 | reg = ep->msi_cap + PCI_MSI_ADDRESS_HI; |
| 417 | msg_addr_upper = dw_pcie_readl_dbi(pci, reg); |
| 418 | reg = ep->msi_cap + PCI_MSI_DATA_64; |
| 419 | msg_data = dw_pcie_readw_dbi(pci, reg); |
Niklas Cassel | 6f6d787 | 2017-12-20 00:29:27 +0100 | [diff] [blame] | 420 | } else { |
| 421 | msg_addr_upper = 0; |
Gustavo Pimentel | 3920a5d | 2018-07-19 10:32:15 +0200 | [diff] [blame] | 422 | reg = ep->msi_cap + PCI_MSI_DATA_32; |
| 423 | msg_data = dw_pcie_readw_dbi(pci, reg); |
Niklas Cassel | 6f6d787 | 2017-12-20 00:29:27 +0100 | [diff] [blame] | 424 | } |
| 425 | msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower; |
Bjorn Helgaas | 1609336 | 2018-02-01 11:36:07 -0600 | [diff] [blame] | 426 | ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr, |
Niklas Cassel | 6f6d787 | 2017-12-20 00:29:27 +0100 | [diff] [blame] | 427 | epc->mem->page_size); |
| 428 | if (ret) |
| 429 | return ret; |
| 430 | |
| 431 | writel(msg_data | (interrupt_num - 1), ep->msi_mem); |
| 432 | |
Bjorn Helgaas | 1609336 | 2018-02-01 11:36:07 -0600 | [diff] [blame] | 433 | dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys); |
Niklas Cassel | 6f6d787 | 2017-12-20 00:29:27 +0100 | [diff] [blame] | 434 | |
| 435 | return 0; |
| 436 | } |
| 437 | |
Gustavo Pimentel | beb4641 | 2018-07-19 10:32:14 +0200 | [diff] [blame] | 438 | int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, |
| 439 | u16 interrupt_num) |
| 440 | { |
| 441 | struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
| 442 | struct pci_epc *epc = ep->epc; |
| 443 | u16 tbl_offset, bir; |
| 444 | u32 bar_addr_upper, bar_addr_lower; |
| 445 | u32 msg_addr_upper, msg_addr_lower; |
| 446 | u32 reg, msg_data, vec_ctrl; |
| 447 | u64 tbl_addr, msg_addr, reg_u64; |
| 448 | void __iomem *msix_tbl; |
| 449 | int ret; |
| 450 | |
| 451 | reg = ep->msix_cap + PCI_MSIX_TABLE; |
| 452 | tbl_offset = dw_pcie_readl_dbi(pci, reg); |
| 453 | bir = (tbl_offset & PCI_MSIX_TABLE_BIR); |
| 454 | tbl_offset &= PCI_MSIX_TABLE_OFFSET; |
Gustavo Pimentel | beb4641 | 2018-07-19 10:32:14 +0200 | [diff] [blame] | 455 | |
| 456 | reg = PCI_BASE_ADDRESS_0 + (4 * bir); |
| 457 | bar_addr_upper = 0; |
| 458 | bar_addr_lower = dw_pcie_readl_dbi(pci, reg); |
| 459 | reg_u64 = (bar_addr_lower & PCI_BASE_ADDRESS_MEM_TYPE_MASK); |
| 460 | if (reg_u64 == PCI_BASE_ADDRESS_MEM_TYPE_64) |
| 461 | bar_addr_upper = dw_pcie_readl_dbi(pci, reg + 4); |
| 462 | |
| 463 | tbl_addr = ((u64) bar_addr_upper) << 32 | bar_addr_lower; |
| 464 | tbl_addr += (tbl_offset + ((interrupt_num - 1) * PCI_MSIX_ENTRY_SIZE)); |
| 465 | tbl_addr &= PCI_BASE_ADDRESS_MEM_MASK; |
| 466 | |
| 467 | msix_tbl = ioremap_nocache(ep->phys_base + tbl_addr, |
| 468 | PCI_MSIX_ENTRY_SIZE); |
| 469 | if (!msix_tbl) |
| 470 | return -EINVAL; |
| 471 | |
| 472 | msg_addr_lower = readl(msix_tbl + PCI_MSIX_ENTRY_LOWER_ADDR); |
| 473 | msg_addr_upper = readl(msix_tbl + PCI_MSIX_ENTRY_UPPER_ADDR); |
| 474 | msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower; |
| 475 | msg_data = readl(msix_tbl + PCI_MSIX_ENTRY_DATA); |
| 476 | vec_ctrl = readl(msix_tbl + PCI_MSIX_ENTRY_VECTOR_CTRL); |
| 477 | |
| 478 | iounmap(msix_tbl); |
| 479 | |
Gustavo Pimentel | 0380cf8 | 2018-12-07 18:24:37 +0100 | [diff] [blame] | 480 | if (vec_ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT) { |
| 481 | dev_dbg(pci->dev, "MSI-X entry ctrl set\n"); |
Gustavo Pimentel | beb4641 | 2018-07-19 10:32:14 +0200 | [diff] [blame] | 482 | return -EPERM; |
Gustavo Pimentel | 0380cf8 | 2018-12-07 18:24:37 +0100 | [diff] [blame] | 483 | } |
Gustavo Pimentel | beb4641 | 2018-07-19 10:32:14 +0200 | [diff] [blame] | 484 | |
| 485 | ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr, |
| 486 | epc->mem->page_size); |
| 487 | if (ret) |
| 488 | return ret; |
| 489 | |
| 490 | writel(msg_data, ep->msi_mem); |
| 491 | |
| 492 | dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys); |
| 493 | |
| 494 | return 0; |
| 495 | } |
| 496 | |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 497 | void dw_pcie_ep_exit(struct dw_pcie_ep *ep) |
| 498 | { |
| 499 | struct pci_epc *epc = ep->epc; |
| 500 | |
Niklas Cassel | 2fd0c9d | 2017-12-20 00:29:25 +0100 | [diff] [blame] | 501 | pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem, |
| 502 | epc->mem->page_size); |
| 503 | |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 504 | pci_epc_mem_exit(epc); |
| 505 | } |
| 506 | |
| 507 | int dw_pcie_ep_init(struct dw_pcie_ep *ep) |
| 508 | { |
| 509 | int ret; |
| 510 | void *addr; |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 511 | struct pci_epc *epc; |
| 512 | struct dw_pcie *pci = to_dw_pcie_from_ep(ep); |
| 513 | struct device *dev = pci->dev; |
| 514 | struct device_node *np = dev->of_node; |
| 515 | |
| 516 | if (!pci->dbi_base || !pci->dbi_base2) { |
Niklas Cassel | ae15d86 | 2018-02-01 15:02:23 +0100 | [diff] [blame] | 517 | dev_err(dev, "dbi_base/dbi_base2 is not populated\n"); |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 518 | return -EINVAL; |
| 519 | } |
Stephen Warren | 6d6b05e | 2018-11-30 11:37:19 -0700 | [diff] [blame] | 520 | if (pci->iatu_unroll_enabled && !pci->atu_base) { |
| 521 | dev_err(dev, "atu_base is not populated\n"); |
| 522 | return -EINVAL; |
| 523 | } |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 524 | |
| 525 | ret = of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows); |
| 526 | if (ret < 0) { |
Gustavo Pimentel | b4a8a51 | 2018-05-14 16:09:48 +0100 | [diff] [blame] | 527 | dev_err(dev, "Unable to read *num-ib-windows* property\n"); |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 528 | return ret; |
| 529 | } |
Niklas Cassel | ad4a5be | 2017-12-14 14:01:44 +0100 | [diff] [blame] | 530 | if (ep->num_ib_windows > MAX_IATU_IN) { |
Gustavo Pimentel | b4a8a51 | 2018-05-14 16:09:48 +0100 | [diff] [blame] | 531 | dev_err(dev, "Invalid *num-ib-windows*\n"); |
Niklas Cassel | ad4a5be | 2017-12-14 14:01:44 +0100 | [diff] [blame] | 532 | return -EINVAL; |
| 533 | } |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 534 | |
| 535 | ret = of_property_read_u32(np, "num-ob-windows", &ep->num_ob_windows); |
| 536 | if (ret < 0) { |
Gustavo Pimentel | b4a8a51 | 2018-05-14 16:09:48 +0100 | [diff] [blame] | 537 | dev_err(dev, "Unable to read *num-ob-windows* property\n"); |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 538 | return ret; |
| 539 | } |
Niklas Cassel | ad4a5be | 2017-12-14 14:01:44 +0100 | [diff] [blame] | 540 | if (ep->num_ob_windows > MAX_IATU_OUT) { |
Gustavo Pimentel | b4a8a51 | 2018-05-14 16:09:48 +0100 | [diff] [blame] | 541 | dev_err(dev, "Invalid *num-ob-windows*\n"); |
Niklas Cassel | ad4a5be | 2017-12-14 14:01:44 +0100 | [diff] [blame] | 542 | return -EINVAL; |
| 543 | } |
| 544 | |
Kees Cook | a86854d | 2018-06-12 14:07:58 -0700 | [diff] [blame] | 545 | ep->ib_window_map = devm_kcalloc(dev, |
Niklas Cassel | ad4a5be | 2017-12-14 14:01:44 +0100 | [diff] [blame] | 546 | BITS_TO_LONGS(ep->num_ib_windows), |
Kees Cook | a86854d | 2018-06-12 14:07:58 -0700 | [diff] [blame] | 547 | sizeof(long), |
Niklas Cassel | ad4a5be | 2017-12-14 14:01:44 +0100 | [diff] [blame] | 548 | GFP_KERNEL); |
| 549 | if (!ep->ib_window_map) |
| 550 | return -ENOMEM; |
| 551 | |
Kees Cook | a86854d | 2018-06-12 14:07:58 -0700 | [diff] [blame] | 552 | ep->ob_window_map = devm_kcalloc(dev, |
Niklas Cassel | ad4a5be | 2017-12-14 14:01:44 +0100 | [diff] [blame] | 553 | BITS_TO_LONGS(ep->num_ob_windows), |
Kees Cook | a86854d | 2018-06-12 14:07:58 -0700 | [diff] [blame] | 554 | sizeof(long), |
Niklas Cassel | ad4a5be | 2017-12-14 14:01:44 +0100 | [diff] [blame] | 555 | GFP_KERNEL); |
| 556 | if (!ep->ob_window_map) |
| 557 | return -ENOMEM; |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 558 | |
Kees Cook | a86854d | 2018-06-12 14:07:58 -0700 | [diff] [blame] | 559 | addr = devm_kcalloc(dev, ep->num_ob_windows, sizeof(phys_addr_t), |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 560 | GFP_KERNEL); |
| 561 | if (!addr) |
| 562 | return -ENOMEM; |
| 563 | ep->outbound_addr = addr; |
| 564 | |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 565 | epc = devm_pci_epc_create(dev, &epc_ops); |
| 566 | if (IS_ERR(epc)) { |
Gustavo Pimentel | b4a8a51 | 2018-05-14 16:09:48 +0100 | [diff] [blame] | 567 | dev_err(dev, "Failed to create epc device\n"); |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 568 | return PTR_ERR(epc); |
| 569 | } |
| 570 | |
Gustavo Pimentel | 4e965ed | 2018-07-19 10:32:11 +0200 | [diff] [blame] | 571 | ep->epc = epc; |
| 572 | epc_set_drvdata(epc, ep); |
| 573 | |
| 574 | if (ep->ops->ep_init) |
| 575 | ep->ops->ep_init(ep); |
| 576 | |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 577 | ret = of_property_read_u8(np, "max-functions", &epc->max_functions); |
| 578 | if (ret < 0) |
| 579 | epc->max_functions = 1; |
| 580 | |
Kishon Vijay Abraham I | a937fe0 | 2017-08-18 20:28:02 +0530 | [diff] [blame] | 581 | ret = __pci_epc_mem_init(epc, ep->phys_base, ep->addr_size, |
| 582 | ep->page_size); |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 583 | if (ret < 0) { |
| 584 | dev_err(dev, "Failed to initialize address space\n"); |
| 585 | return ret; |
| 586 | } |
| 587 | |
Niklas Cassel | 2fd0c9d | 2017-12-20 00:29:25 +0100 | [diff] [blame] | 588 | ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys, |
| 589 | epc->mem->page_size); |
| 590 | if (!ep->msi_mem) { |
Gustavo Pimentel | beb4641 | 2018-07-19 10:32:14 +0200 | [diff] [blame] | 591 | dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n"); |
Niklas Cassel | 2fd0c9d | 2017-12-20 00:29:25 +0100 | [diff] [blame] | 592 | return -ENOMEM; |
| 593 | } |
Gustavo Pimentel | beb4641 | 2018-07-19 10:32:14 +0200 | [diff] [blame] | 594 | ep->msi_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSI); |
| 595 | |
| 596 | ep->msix_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSIX); |
Niklas Cassel | 2fd0c9d | 2017-12-20 00:29:25 +0100 | [diff] [blame] | 597 | |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 598 | dw_pcie_setup(pci); |
| 599 | |
| 600 | return 0; |
| 601 | } |