Thomas Gleixner | a61127c | 2019-05-29 16:57:49 -0700 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 2 | /* |
| 3 | * core routines for the asynchronous memory transfer/transform api |
| 4 | * |
| 5 | * Copyright © 2006, Intel Corporation. |
| 6 | * |
| 7 | * Dan Williams <dan.j.williams@intel.com> |
| 8 | * |
| 9 | * with architecture considerations by: |
| 10 | * Neil Brown <neilb@suse.de> |
| 11 | * Jeff Garzik <jeff@garzik.org> |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 12 | */ |
Franck Bui-Huu | 8252474 | 2008-05-12 21:21:05 +0200 | [diff] [blame] | 13 | #include <linux/rculist.h> |
Paul Gortmaker | 4bb33cc | 2011-05-27 14:41:48 -0400 | [diff] [blame] | 14 | #include <linux/module.h> |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 15 | #include <linux/kernel.h> |
| 16 | #include <linux/async_tx.h> |
| 17 | |
| 18 | #ifdef CONFIG_DMA_ENGINE |
Dan Williams | bec0851 | 2009-01-06 11:38:14 -0700 | [diff] [blame] | 19 | static int __init async_tx_init(void) |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 20 | { |
Dan Williams | 729b5d1 | 2009-03-25 09:13:25 -0700 | [diff] [blame] | 21 | async_dmaengine_get(); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 22 | |
| 23 | printk(KERN_INFO "async_tx: api initialized (async)\n"); |
| 24 | |
| 25 | return 0; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 26 | } |
| 27 | |
| 28 | static void __exit async_tx_exit(void) |
| 29 | { |
Dan Williams | 729b5d1 | 2009-03-25 09:13:25 -0700 | [diff] [blame] | 30 | async_dmaengine_put(); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 31 | } |
| 32 | |
Dan Williams | af1f951 | 2009-08-29 19:09:26 -0700 | [diff] [blame] | 33 | module_init(async_tx_init); |
| 34 | module_exit(async_tx_exit); |
| 35 | |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 36 | /** |
Dan Williams | 47437b2 | 2008-02-02 19:49:59 -0700 | [diff] [blame] | 37 | * __async_tx_find_channel - find a channel to carry out the operation or let |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 38 | * the transaction execute synchronously |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 39 | * @submit: transaction dependency and submission modifiers |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 40 | * @tx_type: transaction type |
| 41 | */ |
| 42 | struct dma_chan * |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 43 | __async_tx_find_channel(struct async_submit_ctl *submit, |
| 44 | enum dma_transaction_type tx_type) |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 45 | { |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 46 | struct dma_async_tx_descriptor *depend_tx = submit->depend_tx; |
| 47 | |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 48 | /* see if we can keep the chain on one channel */ |
| 49 | if (depend_tx && |
Dan Williams | bec0851 | 2009-01-06 11:38:14 -0700 | [diff] [blame] | 50 | dma_has_cap(tx_type, depend_tx->chan->device->cap_mask)) |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 51 | return depend_tx->chan; |
Dan Williams | 729b5d1 | 2009-03-25 09:13:25 -0700 | [diff] [blame] | 52 | return async_dma_find_channel(tx_type); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 53 | } |
Dan Williams | 47437b2 | 2008-02-02 19:49:59 -0700 | [diff] [blame] | 54 | EXPORT_SYMBOL_GPL(__async_tx_find_channel); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 55 | #endif |
| 56 | |
Dan Williams | 19242d7 | 2008-04-17 20:17:25 -0700 | [diff] [blame] | 57 | |
| 58 | /** |
| 59 | * async_tx_channel_switch - queue an interrupt descriptor with a dependency |
| 60 | * pre-attached. |
| 61 | * @depend_tx: the operation that must finish before the new operation runs |
| 62 | * @tx: the new operation |
| 63 | */ |
| 64 | static void |
| 65 | async_tx_channel_switch(struct dma_async_tx_descriptor *depend_tx, |
| 66 | struct dma_async_tx_descriptor *tx) |
| 67 | { |
Dan Williams | 95475e5 | 2009-07-14 12:19:02 -0700 | [diff] [blame] | 68 | struct dma_chan *chan = depend_tx->chan; |
| 69 | struct dma_device *device = chan->device; |
Dan Williams | 19242d7 | 2008-04-17 20:17:25 -0700 | [diff] [blame] | 70 | struct dma_async_tx_descriptor *intr_tx = (void *) ~0; |
| 71 | |
| 72 | /* first check to see if we can still append to depend_tx */ |
Dan Williams | caa20d97 | 2010-05-17 16:24:16 -0700 | [diff] [blame] | 73 | txd_lock(depend_tx); |
| 74 | if (txd_parent(depend_tx) && depend_tx->chan == tx->chan) { |
| 75 | txd_chain(depend_tx, tx); |
Dan Williams | 19242d7 | 2008-04-17 20:17:25 -0700 | [diff] [blame] | 76 | intr_tx = NULL; |
| 77 | } |
Dan Williams | caa20d97 | 2010-05-17 16:24:16 -0700 | [diff] [blame] | 78 | txd_unlock(depend_tx); |
Dan Williams | 19242d7 | 2008-04-17 20:17:25 -0700 | [diff] [blame] | 79 | |
Dan Williams | 95475e5 | 2009-07-14 12:19:02 -0700 | [diff] [blame] | 80 | /* attached dependency, flush the parent channel */ |
| 81 | if (!intr_tx) { |
| 82 | device->device_issue_pending(chan); |
Dan Williams | 19242d7 | 2008-04-17 20:17:25 -0700 | [diff] [blame] | 83 | return; |
Dan Williams | 95475e5 | 2009-07-14 12:19:02 -0700 | [diff] [blame] | 84 | } |
Dan Williams | 19242d7 | 2008-04-17 20:17:25 -0700 | [diff] [blame] | 85 | |
| 86 | /* see if we can schedule an interrupt |
| 87 | * otherwise poll for completion |
| 88 | */ |
| 89 | if (dma_has_cap(DMA_INTERRUPT, device->cap_mask)) |
Dan Williams | 636bdea | 2008-04-17 20:17:26 -0700 | [diff] [blame] | 90 | intr_tx = device->device_prep_dma_interrupt(chan, 0); |
Dan Williams | 19242d7 | 2008-04-17 20:17:25 -0700 | [diff] [blame] | 91 | else |
| 92 | intr_tx = NULL; |
| 93 | |
| 94 | if (intr_tx) { |
| 95 | intr_tx->callback = NULL; |
| 96 | intr_tx->callback_param = NULL; |
Dan Williams | caa20d97 | 2010-05-17 16:24:16 -0700 | [diff] [blame] | 97 | /* safe to chain outside the lock since we know we are |
Dan Williams | 19242d7 | 2008-04-17 20:17:25 -0700 | [diff] [blame] | 98 | * not submitted yet |
| 99 | */ |
Dan Williams | caa20d97 | 2010-05-17 16:24:16 -0700 | [diff] [blame] | 100 | txd_chain(intr_tx, tx); |
Dan Williams | 19242d7 | 2008-04-17 20:17:25 -0700 | [diff] [blame] | 101 | |
| 102 | /* check if we need to append */ |
Dan Williams | caa20d97 | 2010-05-17 16:24:16 -0700 | [diff] [blame] | 103 | txd_lock(depend_tx); |
| 104 | if (txd_parent(depend_tx)) { |
| 105 | txd_chain(depend_tx, intr_tx); |
Dan Williams | 19242d7 | 2008-04-17 20:17:25 -0700 | [diff] [blame] | 106 | async_tx_ack(intr_tx); |
| 107 | intr_tx = NULL; |
| 108 | } |
Dan Williams | caa20d97 | 2010-05-17 16:24:16 -0700 | [diff] [blame] | 109 | txd_unlock(depend_tx); |
Dan Williams | 19242d7 | 2008-04-17 20:17:25 -0700 | [diff] [blame] | 110 | |
| 111 | if (intr_tx) { |
Dan Williams | caa20d97 | 2010-05-17 16:24:16 -0700 | [diff] [blame] | 112 | txd_clear_parent(intr_tx); |
Dan Williams | 19242d7 | 2008-04-17 20:17:25 -0700 | [diff] [blame] | 113 | intr_tx->tx_submit(intr_tx); |
| 114 | async_tx_ack(intr_tx); |
| 115 | } |
Dan Williams | 95475e5 | 2009-07-14 12:19:02 -0700 | [diff] [blame] | 116 | device->device_issue_pending(chan); |
Dan Williams | 19242d7 | 2008-04-17 20:17:25 -0700 | [diff] [blame] | 117 | } else { |
Vinod Koul | 157efa8 | 2013-10-16 21:05:50 +0530 | [diff] [blame] | 118 | if (dma_wait_for_async_tx(depend_tx) != DMA_COMPLETE) |
Bartlomiej Zolnierkiewicz | 7d28339 | 2012-11-08 10:03:16 +0000 | [diff] [blame] | 119 | panic("%s: DMA error waiting for depend_tx\n", |
Dan Williams | 19242d7 | 2008-04-17 20:17:25 -0700 | [diff] [blame] | 120 | __func__); |
| 121 | tx->tx_submit(tx); |
| 122 | } |
| 123 | } |
| 124 | |
| 125 | |
| 126 | /** |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 127 | * submit_disposition - flags for routing an incoming operation |
Dan Williams | 19242d7 | 2008-04-17 20:17:25 -0700 | [diff] [blame] | 128 | * @ASYNC_TX_SUBMITTED: we were able to append the new operation under the lock |
| 129 | * @ASYNC_TX_CHANNEL_SWITCH: when the lock is dropped schedule a channel switch |
| 130 | * @ASYNC_TX_DIRECT_SUBMIT: when the lock is dropped submit directly |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 131 | * |
| 132 | * while holding depend_tx->lock we must avoid submitting new operations |
| 133 | * to prevent a circular locking dependency with drivers that already |
| 134 | * hold a channel lock when calling async_tx_run_dependencies. |
Dan Williams | 19242d7 | 2008-04-17 20:17:25 -0700 | [diff] [blame] | 135 | */ |
| 136 | enum submit_disposition { |
| 137 | ASYNC_TX_SUBMITTED, |
| 138 | ASYNC_TX_CHANNEL_SWITCH, |
| 139 | ASYNC_TX_DIRECT_SUBMIT, |
| 140 | }; |
| 141 | |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 142 | void |
| 143 | async_tx_submit(struct dma_chan *chan, struct dma_async_tx_descriptor *tx, |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 144 | struct async_submit_ctl *submit) |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 145 | { |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 146 | struct dma_async_tx_descriptor *depend_tx = submit->depend_tx; |
| 147 | |
| 148 | tx->callback = submit->cb_fn; |
| 149 | tx->callback_param = submit->cb_param; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 150 | |
Dan Williams | 19242d7 | 2008-04-17 20:17:25 -0700 | [diff] [blame] | 151 | if (depend_tx) { |
| 152 | enum submit_disposition s; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 153 | |
Dan Williams | 19242d7 | 2008-04-17 20:17:25 -0700 | [diff] [blame] | 154 | /* sanity check the dependency chain: |
| 155 | * 1/ if ack is already set then we cannot be sure |
| 156 | * we are referring to the correct operation |
| 157 | * 2/ dependencies are 1:1 i.e. two transactions can |
| 158 | * not depend on the same parent |
| 159 | */ |
Dan Williams | caa20d97 | 2010-05-17 16:24:16 -0700 | [diff] [blame] | 160 | BUG_ON(async_tx_test_ack(depend_tx) || txd_next(depend_tx) || |
| 161 | txd_parent(tx)); |
Dan Williams | 19242d7 | 2008-04-17 20:17:25 -0700 | [diff] [blame] | 162 | |
| 163 | /* the lock prevents async_tx_run_dependencies from missing |
| 164 | * the setting of ->next when ->parent != NULL |
| 165 | */ |
Dan Williams | caa20d97 | 2010-05-17 16:24:16 -0700 | [diff] [blame] | 166 | txd_lock(depend_tx); |
| 167 | if (txd_parent(depend_tx)) { |
Dan Williams | 19242d7 | 2008-04-17 20:17:25 -0700 | [diff] [blame] | 168 | /* we have a parent so we can not submit directly |
| 169 | * if we are staying on the same channel: append |
| 170 | * else: channel switch |
| 171 | */ |
| 172 | if (depend_tx->chan == chan) { |
Dan Williams | caa20d97 | 2010-05-17 16:24:16 -0700 | [diff] [blame] | 173 | txd_chain(depend_tx, tx); |
Dan Williams | 19242d7 | 2008-04-17 20:17:25 -0700 | [diff] [blame] | 174 | s = ASYNC_TX_SUBMITTED; |
| 175 | } else |
| 176 | s = ASYNC_TX_CHANNEL_SWITCH; |
| 177 | } else { |
| 178 | /* we do not have a parent so we may be able to submit |
| 179 | * directly if we are staying on the same channel |
| 180 | */ |
| 181 | if (depend_tx->chan == chan) |
| 182 | s = ASYNC_TX_DIRECT_SUBMIT; |
| 183 | else |
| 184 | s = ASYNC_TX_CHANNEL_SWITCH; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 185 | } |
Dan Williams | caa20d97 | 2010-05-17 16:24:16 -0700 | [diff] [blame] | 186 | txd_unlock(depend_tx); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 187 | |
Dan Williams | 19242d7 | 2008-04-17 20:17:25 -0700 | [diff] [blame] | 188 | switch (s) { |
| 189 | case ASYNC_TX_SUBMITTED: |
| 190 | break; |
| 191 | case ASYNC_TX_CHANNEL_SWITCH: |
| 192 | async_tx_channel_switch(depend_tx, tx); |
| 193 | break; |
| 194 | case ASYNC_TX_DIRECT_SUBMIT: |
Dan Williams | caa20d97 | 2010-05-17 16:24:16 -0700 | [diff] [blame] | 195 | txd_clear_parent(tx); |
Dan Williams | 19242d7 | 2008-04-17 20:17:25 -0700 | [diff] [blame] | 196 | tx->tx_submit(tx); |
| 197 | break; |
| 198 | } |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 199 | } else { |
Dan Williams | caa20d97 | 2010-05-17 16:24:16 -0700 | [diff] [blame] | 200 | txd_clear_parent(tx); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 201 | tx->tx_submit(tx); |
| 202 | } |
| 203 | |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 204 | if (submit->flags & ASYNC_TX_ACK) |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 205 | async_tx_ack(tx); |
| 206 | |
Dan Williams | 88ba2aa | 2009-04-09 16:16:18 -0700 | [diff] [blame] | 207 | if (depend_tx) |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 208 | async_tx_ack(depend_tx); |
| 209 | } |
| 210 | EXPORT_SYMBOL_GPL(async_tx_submit); |
| 211 | |
| 212 | /** |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 213 | * async_trigger_callback - schedules the callback function to be run |
| 214 | * @submit: submission and completion parameters |
| 215 | * |
| 216 | * honored flags: ASYNC_TX_ACK |
| 217 | * |
| 218 | * The callback is run after any dependent operations have completed. |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 219 | */ |
| 220 | struct dma_async_tx_descriptor * |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 221 | async_trigger_callback(struct async_submit_ctl *submit) |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 222 | { |
| 223 | struct dma_chan *chan; |
| 224 | struct dma_device *device; |
| 225 | struct dma_async_tx_descriptor *tx; |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 226 | struct dma_async_tx_descriptor *depend_tx = submit->depend_tx; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 227 | |
| 228 | if (depend_tx) { |
| 229 | chan = depend_tx->chan; |
| 230 | device = chan->device; |
| 231 | |
| 232 | /* see if we can schedule an interrupt |
| 233 | * otherwise poll for completion |
| 234 | */ |
| 235 | if (device && !dma_has_cap(DMA_INTERRUPT, device->cap_mask)) |
| 236 | device = NULL; |
| 237 | |
Dan Williams | 636bdea | 2008-04-17 20:17:26 -0700 | [diff] [blame] | 238 | tx = device ? device->device_prep_dma_interrupt(chan, 0) : NULL; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 239 | } else |
| 240 | tx = NULL; |
| 241 | |
| 242 | if (tx) { |
Dan Williams | 3280ab3e | 2008-03-13 17:45:28 -0700 | [diff] [blame] | 243 | pr_debug("%s: (async)\n", __func__); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 244 | |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 245 | async_tx_submit(chan, tx, submit); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 246 | } else { |
Dan Williams | 3280ab3e | 2008-03-13 17:45:28 -0700 | [diff] [blame] | 247 | pr_debug("%s: (sync)\n", __func__); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 248 | |
| 249 | /* wait for any prerequisite operations */ |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 250 | async_tx_quiesce(&submit->depend_tx); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 251 | |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 252 | async_tx_sync_epilog(submit); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 253 | } |
| 254 | |
| 255 | return tx; |
| 256 | } |
| 257 | EXPORT_SYMBOL_GPL(async_trigger_callback); |
| 258 | |
Dan Williams | d2c52b7 | 2008-07-17 17:59:55 -0700 | [diff] [blame] | 259 | /** |
| 260 | * async_tx_quiesce - ensure tx is complete and freeable upon return |
| 261 | * @tx - transaction to quiesce |
| 262 | */ |
| 263 | void async_tx_quiesce(struct dma_async_tx_descriptor **tx) |
| 264 | { |
| 265 | if (*tx) { |
| 266 | /* if ack is already set then we cannot be sure |
| 267 | * we are referring to the correct operation |
| 268 | */ |
| 269 | BUG_ON(async_tx_test_ack(*tx)); |
Vinod Koul | 157efa8 | 2013-10-16 21:05:50 +0530 | [diff] [blame] | 270 | if (dma_wait_for_async_tx(*tx) != DMA_COMPLETE) |
Bartlomiej Zolnierkiewicz | 7d28339 | 2012-11-08 10:03:16 +0000 | [diff] [blame] | 271 | panic("%s: DMA error waiting for transaction\n", |
| 272 | __func__); |
Dan Williams | d2c52b7 | 2008-07-17 17:59:55 -0700 | [diff] [blame] | 273 | async_tx_ack(*tx); |
| 274 | *tx = NULL; |
| 275 | } |
| 276 | } |
| 277 | EXPORT_SYMBOL_GPL(async_tx_quiesce); |
| 278 | |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 279 | MODULE_AUTHOR("Intel Corporation"); |
| 280 | MODULE_DESCRIPTION("Asynchronous Bulk Memory Transactions API"); |
| 281 | MODULE_LICENSE("GPL"); |