Thomas Gleixner | a61127c | 2019-05-29 16:57:49 -0700 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 2 | /* |
| 3 | * xor offload engine api |
| 4 | * |
| 5 | * Copyright © 2006, Intel Corporation. |
| 6 | * |
| 7 | * Dan Williams <dan.j.williams@intel.com> |
| 8 | * |
| 9 | * with architecture considerations by: |
| 10 | * Neil Brown <neilb@suse.de> |
| 11 | * Jeff Garzik <jeff@garzik.org> |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 12 | */ |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/interrupt.h> |
Paul Gortmaker | 4bb33cc | 2011-05-27 14:41:48 -0400 | [diff] [blame] | 15 | #include <linux/module.h> |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 16 | #include <linux/mm.h> |
| 17 | #include <linux/dma-mapping.h> |
| 18 | #include <linux/raid/xor.h> |
| 19 | #include <linux/async_tx.h> |
| 20 | |
Dan Williams | 06164f3 | 2009-03-25 09:13:25 -0700 | [diff] [blame] | 21 | /* do_async_xor - dma map the pages and perform the xor with an engine */ |
| 22 | static __async_inline struct dma_async_tx_descriptor * |
Dan Williams | fb36ab1 | 2013-10-18 19:35:26 +0200 | [diff] [blame] | 23 | do_async_xor(struct dma_chan *chan, struct dmaengine_unmap_data *unmap, |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 24 | struct async_submit_ctl *submit) |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 25 | { |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 26 | struct dma_device *dma = chan->device; |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 27 | struct dma_async_tx_descriptor *tx = NULL; |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 28 | dma_async_tx_callback cb_fn_orig = submit->cb_fn; |
| 29 | void *cb_param_orig = submit->cb_param; |
| 30 | enum async_tx_flags flags_orig = submit->flags; |
Bartlomiej Zolnierkiewicz | 0776ae7 | 2013-10-18 19:35:33 +0200 | [diff] [blame] | 31 | enum dma_ctrl_flags dma_flags = 0; |
Dan Williams | fb36ab1 | 2013-10-18 19:35:26 +0200 | [diff] [blame] | 32 | int src_cnt = unmap->to_cnt; |
| 33 | int xor_src_cnt; |
| 34 | dma_addr_t dma_dest = unmap->addr[unmap->to_cnt]; |
| 35 | dma_addr_t *src_list = unmap->addr; |
Dan Williams | 0036731 | 2008-02-02 19:49:57 -0700 | [diff] [blame] | 36 | |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 37 | while (src_cnt) { |
Dan Williams | fb36ab1 | 2013-10-18 19:35:26 +0200 | [diff] [blame] | 38 | dma_addr_t tmp; |
| 39 | |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 40 | submit->flags = flags_orig; |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 41 | xor_src_cnt = min(src_cnt, (int)dma->max_xor); |
Dan Williams | fb36ab1 | 2013-10-18 19:35:26 +0200 | [diff] [blame] | 42 | /* if we are submitting additional xors, leave the chain open |
| 43 | * and clear the callback parameters |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 44 | */ |
| 45 | if (src_cnt > xor_src_cnt) { |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 46 | submit->flags &= ~ASYNC_TX_ACK; |
Dan Williams | 0403e38 | 2009-09-08 17:42:50 -0700 | [diff] [blame] | 47 | submit->flags |= ASYNC_TX_FENCE; |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 48 | submit->cb_fn = NULL; |
| 49 | submit->cb_param = NULL; |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 50 | } else { |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 51 | submit->cb_fn = cb_fn_orig; |
| 52 | submit->cb_param = cb_param_orig; |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 53 | } |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 54 | if (submit->cb_fn) |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 55 | dma_flags |= DMA_PREP_INTERRUPT; |
Dan Williams | 0403e38 | 2009-09-08 17:42:50 -0700 | [diff] [blame] | 56 | if (submit->flags & ASYNC_TX_FENCE) |
| 57 | dma_flags |= DMA_PREP_FENCE; |
Dan Williams | fb36ab1 | 2013-10-18 19:35:26 +0200 | [diff] [blame] | 58 | |
| 59 | /* Drivers force forward progress in case they can not provide a |
| 60 | * descriptor |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 61 | */ |
Dan Williams | fb36ab1 | 2013-10-18 19:35:26 +0200 | [diff] [blame] | 62 | tmp = src_list[0]; |
| 63 | if (src_list > unmap->addr) |
| 64 | src_list[0] = dma_dest; |
| 65 | tx = dma->device_prep_dma_xor(chan, dma_dest, src_list, |
| 66 | xor_src_cnt, unmap->len, |
| 67 | dma_flags); |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 68 | |
Dan Williams | 669ab0b | 2008-07-17 17:59:55 -0700 | [diff] [blame] | 69 | if (unlikely(!tx)) |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 70 | async_tx_quiesce(&submit->depend_tx); |
Dan Williams | 0036731 | 2008-02-02 19:49:57 -0700 | [diff] [blame] | 71 | |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 72 | /* spin wait for the preceding transactions to complete */ |
Dan Williams | 669ab0b | 2008-07-17 17:59:55 -0700 | [diff] [blame] | 73 | while (unlikely(!tx)) { |
| 74 | dma_async_issue_pending(chan); |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 75 | tx = dma->device_prep_dma_xor(chan, dma_dest, |
Dan Williams | fb36ab1 | 2013-10-18 19:35:26 +0200 | [diff] [blame] | 76 | src_list, |
| 77 | xor_src_cnt, unmap->len, |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 78 | dma_flags); |
Dan Williams | 669ab0b | 2008-07-17 17:59:55 -0700 | [diff] [blame] | 79 | } |
Xuelin Shi | 87cea76 | 2014-07-01 16:32:38 +0800 | [diff] [blame] | 80 | src_list[0] = tmp; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 81 | |
Dan Williams | fb36ab1 | 2013-10-18 19:35:26 +0200 | [diff] [blame] | 82 | dma_set_unmap(tx, unmap); |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 83 | async_tx_submit(chan, tx, submit); |
| 84 | submit->depend_tx = tx; |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 85 | |
| 86 | if (src_cnt > xor_src_cnt) { |
| 87 | /* drop completed sources */ |
| 88 | src_cnt -= xor_src_cnt; |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 89 | /* use the intermediate result a source */ |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 90 | src_cnt++; |
Dan Williams | fb36ab1 | 2013-10-18 19:35:26 +0200 | [diff] [blame] | 91 | src_list += xor_src_cnt - 1; |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 92 | } else |
| 93 | break; |
| 94 | } |
Dan Williams | 0036731 | 2008-02-02 19:49:57 -0700 | [diff] [blame] | 95 | |
| 96 | return tx; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 97 | } |
| 98 | |
| 99 | static void |
Yufen Yu | 29bcff7 | 2020-08-20 09:22:08 -0400 | [diff] [blame] | 100 | do_sync_xor_offs(struct page *dest, unsigned int offset, |
| 101 | struct page **src_list, unsigned int *src_offs, |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 102 | int src_cnt, size_t len, struct async_submit_ctl *submit) |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 103 | { |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 104 | int i; |
NeilBrown | b2141e6 | 2009-10-16 16:40:34 +1100 | [diff] [blame] | 105 | int xor_src_cnt = 0; |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 106 | int src_off = 0; |
| 107 | void *dest_buf; |
Dan Williams | 04ce9ab | 2009-06-03 14:22:28 -0700 | [diff] [blame] | 108 | void **srcs; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 109 | |
Dan Williams | 04ce9ab | 2009-06-03 14:22:28 -0700 | [diff] [blame] | 110 | if (submit->scribble) |
| 111 | srcs = submit->scribble; |
| 112 | else |
| 113 | srcs = (void **) src_list; |
| 114 | |
| 115 | /* convert to buffer pointers */ |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 116 | for (i = 0; i < src_cnt; i++) |
NeilBrown | b2141e6 | 2009-10-16 16:40:34 +1100 | [diff] [blame] | 117 | if (src_list[i]) |
Yufen Yu | 29bcff7 | 2020-08-20 09:22:08 -0400 | [diff] [blame] | 118 | srcs[xor_src_cnt++] = page_address(src_list[i]) + |
| 119 | (src_offs ? src_offs[i] : offset); |
NeilBrown | b2141e6 | 2009-10-16 16:40:34 +1100 | [diff] [blame] | 120 | src_cnt = xor_src_cnt; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 121 | /* set destination address */ |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 122 | dest_buf = page_address(dest) + offset; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 123 | |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 124 | if (submit->flags & ASYNC_TX_XOR_ZERO_DST) |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 125 | memset(dest_buf, 0, len); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 126 | |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 127 | while (src_cnt > 0) { |
| 128 | /* process up to 'MAX_XOR_BLOCKS' sources */ |
| 129 | xor_src_cnt = min(src_cnt, MAX_XOR_BLOCKS); |
| 130 | xor_blocks(xor_src_cnt, len, dest_buf, &srcs[src_off]); |
| 131 | |
| 132 | /* drop completed sources */ |
| 133 | src_cnt -= xor_src_cnt; |
| 134 | src_off += xor_src_cnt; |
| 135 | } |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 136 | |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 137 | async_tx_sync_epilog(submit); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 138 | } |
| 139 | |
Yufen Yu | 29bcff7 | 2020-08-20 09:22:08 -0400 | [diff] [blame] | 140 | static inline bool |
| 141 | dma_xor_aligned_offsets(struct dma_device *device, unsigned int offset, |
| 142 | unsigned int *src_offs, int src_cnt, int len) |
| 143 | { |
| 144 | int i; |
| 145 | |
| 146 | if (!is_dma_xor_aligned(device, offset, 0, len)) |
| 147 | return false; |
| 148 | |
| 149 | if (!src_offs) |
| 150 | return true; |
| 151 | |
| 152 | for (i = 0; i < src_cnt; i++) { |
| 153 | if (!is_dma_xor_aligned(device, src_offs[i], 0, len)) |
| 154 | return false; |
| 155 | } |
| 156 | return true; |
| 157 | } |
| 158 | |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 159 | /** |
Yufen Yu | 29bcff7 | 2020-08-20 09:22:08 -0400 | [diff] [blame] | 160 | * async_xor_offs - attempt to xor a set of blocks with a dma engine. |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 161 | * @dest: destination page |
Yufen Yu | 29bcff7 | 2020-08-20 09:22:08 -0400 | [diff] [blame] | 162 | * @offset: dst offset to start transaction |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 163 | * @src_list: array of source pages |
Yufen Yu | 29bcff7 | 2020-08-20 09:22:08 -0400 | [diff] [blame] | 164 | * @src_offs: array of source pages offset, NULL means common src/dst offset |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 165 | * @src_cnt: number of source pages |
| 166 | * @len: length in bytes |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 167 | * @submit: submission / completion modifiers |
| 168 | * |
| 169 | * honored flags: ASYNC_TX_ACK, ASYNC_TX_XOR_ZERO_DST, ASYNC_TX_XOR_DROP_DST |
| 170 | * |
| 171 | * xor_blocks always uses the dest as a source so the |
| 172 | * ASYNC_TX_XOR_ZERO_DST flag must be set to not include dest data in |
| 173 | * the calculation. The assumption with dma eninges is that they only |
| 174 | * use the destination buffer as a source when it is explicity specified |
| 175 | * in the source list. |
| 176 | * |
| 177 | * src_list note: if the dest is also a source it must be at index zero. |
| 178 | * The contents of this array will be overwritten if a scribble region |
| 179 | * is not specified. |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 180 | */ |
| 181 | struct dma_async_tx_descriptor * |
Yufen Yu | 29bcff7 | 2020-08-20 09:22:08 -0400 | [diff] [blame] | 182 | async_xor_offs(struct page *dest, unsigned int offset, |
| 183 | struct page **src_list, unsigned int *src_offs, |
| 184 | int src_cnt, size_t len, struct async_submit_ctl *submit) |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 185 | { |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 186 | struct dma_chan *chan = async_tx_find_channel(submit, DMA_XOR, |
Dan Williams | 47437b2 | 2008-02-02 19:49:59 -0700 | [diff] [blame] | 187 | &dest, 1, src_list, |
| 188 | src_cnt, len); |
Dan Williams | fb36ab1 | 2013-10-18 19:35:26 +0200 | [diff] [blame] | 189 | struct dma_device *device = chan ? chan->device : NULL; |
| 190 | struct dmaengine_unmap_data *unmap = NULL; |
Dan Williams | 04ce9ab | 2009-06-03 14:22:28 -0700 | [diff] [blame] | 191 | |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 192 | BUG_ON(src_cnt <= 1); |
| 193 | |
Dan Williams | fb36ab1 | 2013-10-18 19:35:26 +0200 | [diff] [blame] | 194 | if (device) |
NeilBrown | b02bab6 | 2016-01-07 11:02:34 +1100 | [diff] [blame] | 195 | unmap = dmaengine_get_unmap_data(device->dev, src_cnt+1, GFP_NOWAIT); |
Dan Williams | 04ce9ab | 2009-06-03 14:22:28 -0700 | [diff] [blame] | 196 | |
Yufen Yu | 29bcff7 | 2020-08-20 09:22:08 -0400 | [diff] [blame] | 197 | if (unmap && dma_xor_aligned_offsets(device, offset, |
| 198 | src_offs, src_cnt, len)) { |
Dan Williams | fb36ab1 | 2013-10-18 19:35:26 +0200 | [diff] [blame] | 199 | struct dma_async_tx_descriptor *tx; |
| 200 | int i, j; |
| 201 | |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 202 | /* run the xor asynchronously */ |
| 203 | pr_debug("%s (async): len: %zu\n", __func__, len); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 204 | |
Dan Williams | fb36ab1 | 2013-10-18 19:35:26 +0200 | [diff] [blame] | 205 | unmap->len = len; |
| 206 | for (i = 0, j = 0; i < src_cnt; i++) { |
| 207 | if (!src_list[i]) |
| 208 | continue; |
| 209 | unmap->to_cnt++; |
| 210 | unmap->addr[j++] = dma_map_page(device->dev, src_list[i], |
Yufen Yu | 29bcff7 | 2020-08-20 09:22:08 -0400 | [diff] [blame] | 211 | src_offs ? src_offs[i] : offset, |
| 212 | len, DMA_TO_DEVICE); |
Dan Williams | fb36ab1 | 2013-10-18 19:35:26 +0200 | [diff] [blame] | 213 | } |
| 214 | |
| 215 | /* map it bidirectional as it may be re-used as a source */ |
| 216 | unmap->addr[j] = dma_map_page(device->dev, dest, offset, len, |
| 217 | DMA_BIDIRECTIONAL); |
| 218 | unmap->bidi_cnt = 1; |
| 219 | |
| 220 | tx = do_async_xor(chan, unmap, submit); |
| 221 | dmaengine_unmap_put(unmap); |
| 222 | return tx; |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 223 | } else { |
Dan Williams | fb36ab1 | 2013-10-18 19:35:26 +0200 | [diff] [blame] | 224 | dmaengine_unmap_put(unmap); |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 225 | /* run the xor synchronously */ |
| 226 | pr_debug("%s (sync): len: %zu\n", __func__, len); |
Dan Williams | 04ce9ab | 2009-06-03 14:22:28 -0700 | [diff] [blame] | 227 | WARN_ONCE(chan, "%s: no space for dma address conversion\n", |
| 228 | __func__); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 229 | |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 230 | /* in the sync case the dest is an implied source |
| 231 | * (assumes the dest is the first source) |
| 232 | */ |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 233 | if (submit->flags & ASYNC_TX_XOR_DROP_DST) { |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 234 | src_cnt--; |
| 235 | src_list++; |
Xiao Ni | 9be148e | 2021-05-28 14:16:38 +0800 | [diff] [blame] | 236 | if (src_offs) |
| 237 | src_offs++; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 238 | } |
| 239 | |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 240 | /* wait for any prerequisite operations */ |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 241 | async_tx_quiesce(&submit->depend_tx); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 242 | |
Yufen Yu | 29bcff7 | 2020-08-20 09:22:08 -0400 | [diff] [blame] | 243 | do_sync_xor_offs(dest, offset, src_list, src_offs, |
| 244 | src_cnt, len, submit); |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 245 | |
| 246 | return NULL; |
| 247 | } |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 248 | } |
Yufen Yu | 29bcff7 | 2020-08-20 09:22:08 -0400 | [diff] [blame] | 249 | EXPORT_SYMBOL_GPL(async_xor_offs); |
| 250 | |
| 251 | /** |
| 252 | * async_xor - attempt to xor a set of blocks with a dma engine. |
| 253 | * @dest: destination page |
| 254 | * @src_list: array of source pages |
| 255 | * @offset: common src/dst offset to start transaction |
| 256 | * @src_cnt: number of source pages |
| 257 | * @len: length in bytes |
| 258 | * @submit: submission / completion modifiers |
| 259 | * |
| 260 | * honored flags: ASYNC_TX_ACK, ASYNC_TX_XOR_ZERO_DST, ASYNC_TX_XOR_DROP_DST |
| 261 | * |
| 262 | * xor_blocks always uses the dest as a source so the |
| 263 | * ASYNC_TX_XOR_ZERO_DST flag must be set to not include dest data in |
| 264 | * the calculation. The assumption with dma eninges is that they only |
| 265 | * use the destination buffer as a source when it is explicity specified |
| 266 | * in the source list. |
| 267 | * |
| 268 | * src_list note: if the dest is also a source it must be at index zero. |
| 269 | * The contents of this array will be overwritten if a scribble region |
| 270 | * is not specified. |
| 271 | */ |
| 272 | struct dma_async_tx_descriptor * |
| 273 | async_xor(struct page *dest, struct page **src_list, unsigned int offset, |
| 274 | int src_cnt, size_t len, struct async_submit_ctl *submit) |
| 275 | { |
| 276 | return async_xor_offs(dest, offset, src_list, NULL, |
| 277 | src_cnt, len, submit); |
| 278 | } |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 279 | EXPORT_SYMBOL_GPL(async_xor); |
| 280 | |
| 281 | static int page_is_zero(struct page *p, unsigned int offset, size_t len) |
| 282 | { |
Akinobu Mita | 2c88ae9 | 2012-10-28 00:49:33 +0900 | [diff] [blame] | 283 | return !memchr_inv(page_address(p) + offset, 0, len); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 284 | } |
| 285 | |
Dan Williams | 7b3cc2b | 2009-11-19 17:10:37 -0700 | [diff] [blame] | 286 | static inline struct dma_chan * |
| 287 | xor_val_chan(struct async_submit_ctl *submit, struct page *dest, |
| 288 | struct page **src_list, int src_cnt, size_t len) |
| 289 | { |
| 290 | #ifdef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA |
| 291 | return NULL; |
| 292 | #endif |
| 293 | return async_tx_find_channel(submit, DMA_XOR_VAL, &dest, 1, src_list, |
| 294 | src_cnt, len); |
| 295 | } |
| 296 | |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 297 | /** |
Yufen Yu | 29bcff7 | 2020-08-20 09:22:08 -0400 | [diff] [blame] | 298 | * async_xor_val_offs - attempt a xor parity check with a dma engine. |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 299 | * @dest: destination page used if the xor is performed synchronously |
Yufen Yu | 29bcff7 | 2020-08-20 09:22:08 -0400 | [diff] [blame] | 300 | * @offset: des offset in pages to start transaction |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 301 | * @src_list: array of source pages |
Yufen Yu | 29bcff7 | 2020-08-20 09:22:08 -0400 | [diff] [blame] | 302 | * @src_offs: array of source pages offset, NULL means common src/det offset |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 303 | * @src_cnt: number of source pages |
| 304 | * @len: length in bytes |
| 305 | * @result: 0 if sum == 0 else non-zero |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 306 | * @submit: submission / completion modifiers |
| 307 | * |
| 308 | * honored flags: ASYNC_TX_ACK |
| 309 | * |
| 310 | * src_list note: if the dest is also a source it must be at index zero. |
| 311 | * The contents of this array will be overwritten if a scribble region |
| 312 | * is not specified. |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 313 | */ |
| 314 | struct dma_async_tx_descriptor * |
Yufen Yu | 29bcff7 | 2020-08-20 09:22:08 -0400 | [diff] [blame] | 315 | async_xor_val_offs(struct page *dest, unsigned int offset, |
| 316 | struct page **src_list, unsigned int *src_offs, |
| 317 | int src_cnt, size_t len, enum sum_check_flags *result, |
| 318 | struct async_submit_ctl *submit) |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 319 | { |
Dan Williams | 7b3cc2b | 2009-11-19 17:10:37 -0700 | [diff] [blame] | 320 | struct dma_chan *chan = xor_val_chan(submit, dest, src_list, src_cnt, len); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 321 | struct dma_device *device = chan ? chan->device : NULL; |
Dan Williams | 0036731 | 2008-02-02 19:49:57 -0700 | [diff] [blame] | 322 | struct dma_async_tx_descriptor *tx = NULL; |
Dan Williams | 173e86b | 2013-10-18 19:35:27 +0200 | [diff] [blame] | 323 | struct dmaengine_unmap_data *unmap = NULL; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 324 | |
| 325 | BUG_ON(src_cnt <= 1); |
| 326 | |
Dan Williams | 173e86b | 2013-10-18 19:35:27 +0200 | [diff] [blame] | 327 | if (device) |
NeilBrown | b02bab6 | 2016-01-07 11:02:34 +1100 | [diff] [blame] | 328 | unmap = dmaengine_get_unmap_data(device->dev, src_cnt, GFP_NOWAIT); |
Dan Williams | 04ce9ab | 2009-06-03 14:22:28 -0700 | [diff] [blame] | 329 | |
Dan Williams | 173e86b | 2013-10-18 19:35:27 +0200 | [diff] [blame] | 330 | if (unmap && src_cnt <= device->max_xor && |
Yufen Yu | 29bcff7 | 2020-08-20 09:22:08 -0400 | [diff] [blame] | 331 | dma_xor_aligned_offsets(device, offset, src_offs, src_cnt, len)) { |
Bartlomiej Zolnierkiewicz | 0776ae7 | 2013-10-18 19:35:33 +0200 | [diff] [blame] | 332 | unsigned long dma_prep_flags = 0; |
Dan Williams | 0036731 | 2008-02-02 19:49:57 -0700 | [diff] [blame] | 333 | int i; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 334 | |
Dan Williams | 3280ab3e | 2008-03-13 17:45:28 -0700 | [diff] [blame] | 335 | pr_debug("%s: (async) len: %zu\n", __func__, len); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 336 | |
Dan Williams | 0403e38 | 2009-09-08 17:42:50 -0700 | [diff] [blame] | 337 | if (submit->cb_fn) |
| 338 | dma_prep_flags |= DMA_PREP_INTERRUPT; |
| 339 | if (submit->flags & ASYNC_TX_FENCE) |
| 340 | dma_prep_flags |= DMA_PREP_FENCE; |
Dan Williams | 0036731 | 2008-02-02 19:49:57 -0700 | [diff] [blame] | 341 | |
Dan Williams | 173e86b | 2013-10-18 19:35:27 +0200 | [diff] [blame] | 342 | for (i = 0; i < src_cnt; i++) { |
| 343 | unmap->addr[i] = dma_map_page(device->dev, src_list[i], |
Yufen Yu | 29bcff7 | 2020-08-20 09:22:08 -0400 | [diff] [blame] | 344 | src_offs ? src_offs[i] : offset, |
| 345 | len, DMA_TO_DEVICE); |
Dan Williams | 173e86b | 2013-10-18 19:35:27 +0200 | [diff] [blame] | 346 | unmap->to_cnt++; |
| 347 | } |
| 348 | unmap->len = len; |
| 349 | |
| 350 | tx = device->device_prep_dma_xor_val(chan, unmap->addr, src_cnt, |
Dan Williams | 099f53c | 2009-04-08 14:28:37 -0700 | [diff] [blame] | 351 | len, result, |
| 352 | dma_prep_flags); |
Dan Williams | 669ab0b | 2008-07-17 17:59:55 -0700 | [diff] [blame] | 353 | if (unlikely(!tx)) { |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 354 | async_tx_quiesce(&submit->depend_tx); |
Dan Williams | 0036731 | 2008-02-02 19:49:57 -0700 | [diff] [blame] | 355 | |
Dan Williams | e34a8ae | 2008-08-05 10:22:05 -0700 | [diff] [blame] | 356 | while (!tx) { |
Dan Williams | 669ab0b | 2008-07-17 17:59:55 -0700 | [diff] [blame] | 357 | dma_async_issue_pending(chan); |
Dan Williams | 099f53c | 2009-04-08 14:28:37 -0700 | [diff] [blame] | 358 | tx = device->device_prep_dma_xor_val(chan, |
Dan Williams | 173e86b | 2013-10-18 19:35:27 +0200 | [diff] [blame] | 359 | unmap->addr, src_cnt, len, result, |
Dan Williams | d4c56f9 | 2008-02-02 19:49:58 -0700 | [diff] [blame] | 360 | dma_prep_flags); |
Dan Williams | e34a8ae | 2008-08-05 10:22:05 -0700 | [diff] [blame] | 361 | } |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 362 | } |
Dan Williams | 173e86b | 2013-10-18 19:35:27 +0200 | [diff] [blame] | 363 | dma_set_unmap(tx, unmap); |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 364 | async_tx_submit(chan, tx, submit); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 365 | } else { |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 366 | enum async_tx_flags flags_orig = submit->flags; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 367 | |
Dan Williams | 3280ab3e | 2008-03-13 17:45:28 -0700 | [diff] [blame] | 368 | pr_debug("%s: (sync) len: %zu\n", __func__, len); |
Dan Williams | 04ce9ab | 2009-06-03 14:22:28 -0700 | [diff] [blame] | 369 | WARN_ONCE(device && src_cnt <= device->max_xor, |
| 370 | "%s: no space for dma address conversion\n", |
| 371 | __func__); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 372 | |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 373 | submit->flags |= ASYNC_TX_XOR_DROP_DST; |
| 374 | submit->flags &= ~ASYNC_TX_ACK; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 375 | |
Yufen Yu | 29bcff7 | 2020-08-20 09:22:08 -0400 | [diff] [blame] | 376 | tx = async_xor_offs(dest, offset, src_list, src_offs, |
| 377 | src_cnt, len, submit); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 378 | |
Dan Williams | d2c52b7 | 2008-07-17 17:59:55 -0700 | [diff] [blame] | 379 | async_tx_quiesce(&tx); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 380 | |
Dan Williams | ad283ea | 2009-08-29 19:09:26 -0700 | [diff] [blame] | 381 | *result = !page_is_zero(dest, offset, len) << SUM_CHECK_P; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 382 | |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 383 | async_tx_sync_epilog(submit); |
| 384 | submit->flags = flags_orig; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 385 | } |
Dan Williams | 173e86b | 2013-10-18 19:35:27 +0200 | [diff] [blame] | 386 | dmaengine_unmap_put(unmap); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 387 | |
| 388 | return tx; |
| 389 | } |
Yufen Yu | 29bcff7 | 2020-08-20 09:22:08 -0400 | [diff] [blame] | 390 | EXPORT_SYMBOL_GPL(async_xor_val_offs); |
| 391 | |
| 392 | /** |
| 393 | * async_xor_val - attempt a xor parity check with a dma engine. |
| 394 | * @dest: destination page used if the xor is performed synchronously |
| 395 | * @src_list: array of source pages |
| 396 | * @offset: offset in pages to start transaction |
| 397 | * @src_cnt: number of source pages |
| 398 | * @len: length in bytes |
| 399 | * @result: 0 if sum == 0 else non-zero |
| 400 | * @submit: submission / completion modifiers |
| 401 | * |
| 402 | * honored flags: ASYNC_TX_ACK |
| 403 | * |
| 404 | * src_list note: if the dest is also a source it must be at index zero. |
| 405 | * The contents of this array will be overwritten if a scribble region |
| 406 | * is not specified. |
| 407 | */ |
| 408 | struct dma_async_tx_descriptor * |
| 409 | async_xor_val(struct page *dest, struct page **src_list, unsigned int offset, |
| 410 | int src_cnt, size_t len, enum sum_check_flags *result, |
| 411 | struct async_submit_ctl *submit) |
| 412 | { |
| 413 | return async_xor_val_offs(dest, offset, src_list, NULL, src_cnt, |
| 414 | len, result, submit); |
| 415 | } |
Dan Williams | 099f53c | 2009-04-08 14:28:37 -0700 | [diff] [blame] | 416 | EXPORT_SYMBOL_GPL(async_xor_val); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 417 | |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 418 | MODULE_AUTHOR("Intel Corporation"); |
| 419 | MODULE_DESCRIPTION("asynchronous xor/xor-zero-sum api"); |
| 420 | MODULE_LICENSE("GPL"); |