| Thomas Gleixner | d2912cb | 2019-06-04 10:11:33 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Ambresh K | 40ca609 | 2013-07-09 13:02:09 +0530 | [diff] [blame] | 2 | /* |
| 3 | * DRA7xx CM2 instance offset macros |
| 4 | * |
| Alexander A. Klimov | 83bf6db | 2020-07-19 12:30:33 +0200 | [diff] [blame] | 5 | * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com |
| Ambresh K | 40ca609 | 2013-07-09 13:02:09 +0530 | [diff] [blame] | 6 | * |
| 7 | * Generated by code originally written by: |
| 8 | * Paul Walmsley (paul@pwsan.com) |
| 9 | * Rajendra Nayak (rnayak@ti.com) |
| 10 | * Benoit Cousson (b-cousson@ti.com) |
| 11 | * |
| 12 | * This file is automatically generated from the OMAP hardware databases. |
| 13 | * We respectfully ask that any modifications to this file be coordinated |
| 14 | * with the public linux-omap@vger.kernel.org mailing list and the |
| 15 | * authors above to ensure that the autogeneration scripts are kept |
| 16 | * up-to-date with the file contents. |
| Ambresh K | 40ca609 | 2013-07-09 13:02:09 +0530 | [diff] [blame] | 17 | */ |
| 18 | |
| 19 | #ifndef __ARCH_ARM_MACH_OMAP2_CM2_7XX_H |
| 20 | #define __ARCH_ARM_MACH_OMAP2_CM2_7XX_H |
| 21 | |
| Ambresh K | 40ca609 | 2013-07-09 13:02:09 +0530 | [diff] [blame] | 22 | /* CM2 base address */ |
| 23 | #define DRA7XX_CM_CORE_BASE 0x4a008000 |
| 24 | |
| 25 | #define DRA7XX_CM_CORE_REGADDR(inst, reg) \ |
| 26 | OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_BASE + (inst) + (reg)) |
| 27 | |
| 28 | /* CM_CORE instances */ |
| 29 | #define DRA7XX_CM_CORE_OCP_SOCKET_INST 0x0000 |
| 30 | #define DRA7XX_CM_CORE_CKGEN_INST 0x0104 |
| 31 | #define DRA7XX_CM_CORE_COREAON_INST 0x0600 |
| 32 | #define DRA7XX_CM_CORE_CORE_INST 0x0700 |
| 33 | #define DRA7XX_CM_CORE_IVA_INST 0x0f00 |
| 34 | #define DRA7XX_CM_CORE_CAM_INST 0x1000 |
| 35 | #define DRA7XX_CM_CORE_DSS_INST 0x1100 |
| 36 | #define DRA7XX_CM_CORE_GPU_INST 0x1200 |
| 37 | #define DRA7XX_CM_CORE_L3INIT_INST 0x1300 |
| 38 | #define DRA7XX_CM_CORE_CUSTEFUSE_INST 0x1600 |
| 39 | #define DRA7XX_CM_CORE_L4PER_INST 0x1700 |
| Ambresh K | 40ca609 | 2013-07-09 13:02:09 +0530 | [diff] [blame] | 40 | |
| 41 | /* CM_CORE clockdomain register offsets (from instance start) */ |
| 42 | #define DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS 0x0000 |
| 43 | #define DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS 0x0000 |
| 44 | #define DRA7XX_CM_CORE_CORE_IPU2_CDOFFS 0x0200 |
| 45 | #define DRA7XX_CM_CORE_CORE_DMA_CDOFFS 0x0300 |
| 46 | #define DRA7XX_CM_CORE_CORE_EMIF_CDOFFS 0x0400 |
| 47 | #define DRA7XX_CM_CORE_CORE_ATL_CDOFFS 0x0520 |
| 48 | #define DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS 0x0600 |
| 49 | #define DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS 0x0700 |
| 50 | #define DRA7XX_CM_CORE_IVA_IVA_CDOFFS 0x0000 |
| 51 | #define DRA7XX_CM_CORE_CAM_CAM_CDOFFS 0x0000 |
| 52 | #define DRA7XX_CM_CORE_DSS_DSS_CDOFFS 0x0000 |
| 53 | #define DRA7XX_CM_CORE_GPU_GPU_CDOFFS 0x0000 |
| 54 | #define DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS 0x0000 |
| 55 | #define DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS 0x00a0 |
| 56 | #define DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS 0x00c0 |
| 57 | #define DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS 0x0000 |
| 58 | #define DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS 0x0000 |
| 59 | #define DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS 0x0180 |
| 60 | #define DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS 0x01fc |
| 61 | #define DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS 0x0210 |
| 62 | |
| Ambresh K | 40ca609 | 2013-07-09 13:02:09 +0530 | [diff] [blame] | 63 | #endif |