David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 1 | /* pci_fire.c: Sun4u platform PCI-E controller support. |
| 2 | * |
| 3 | * Copyright (C) 2007 David S. Miller (davem@davemloft.net) |
| 4 | */ |
| 5 | #include <linux/kernel.h> |
| 6 | #include <linux/pci.h> |
| 7 | #include <linux/slab.h> |
| 8 | #include <linux/init.h> |
David S. Miller | 9bb3c22 | 2007-08-30 22:33:25 -0700 | [diff] [blame] | 9 | #include <linux/msi.h> |
Paul Gortmaker | 7b64db6 | 2011-07-18 15:57:46 -0400 | [diff] [blame] | 10 | #include <linux/export.h> |
David S. Miller | 9bb3c22 | 2007-08-30 22:33:25 -0700 | [diff] [blame] | 11 | #include <linux/irq.h> |
David S. Miller | c804996 | 2008-08-30 03:12:38 -0700 | [diff] [blame] | 12 | #include <linux/of_device.h> |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 13 | |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 14 | #include <asm/prom.h> |
David S. Miller | 9bb3c22 | 2007-08-30 22:33:25 -0700 | [diff] [blame] | 15 | #include <asm/irq.h> |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 16 | #include <asm/upa.h> |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 17 | |
| 18 | #include "pci_impl.h" |
| 19 | |
David S. Miller | c804996 | 2008-08-30 03:12:38 -0700 | [diff] [blame] | 20 | #define DRIVER_NAME "fire" |
| 21 | #define PFX DRIVER_NAME ": " |
| 22 | |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 23 | #define FIRE_IOMMU_CONTROL 0x40000UL |
| 24 | #define FIRE_IOMMU_TSBBASE 0x40008UL |
| 25 | #define FIRE_IOMMU_FLUSH 0x40100UL |
David S. Miller | 95d71e6 | 2007-05-11 21:02:09 -0700 | [diff] [blame] | 26 | #define FIRE_IOMMU_FLUSHINV 0x40108UL |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 27 | |
David S. Miller | ad7ad57 | 2007-07-27 22:39:14 -0700 | [diff] [blame] | 28 | static int pci_fire_pbm_iommu_init(struct pci_pbm_info *pbm) |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 29 | { |
| 30 | struct iommu *iommu = pbm->iommu; |
| 31 | u32 vdma[2], dma_mask; |
| 32 | u64 control; |
David S. Miller | ad7ad57 | 2007-07-27 22:39:14 -0700 | [diff] [blame] | 33 | int tsbsize, err; |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 34 | |
| 35 | /* No virtual-dma property on these guys, use largest size. */ |
| 36 | vdma[0] = 0xc0000000; /* base */ |
| 37 | vdma[1] = 0x40000000; /* size */ |
| 38 | dma_mask = 0xffffffff; |
| 39 | tsbsize = 128; |
| 40 | |
| 41 | /* Register addresses. */ |
| 42 | iommu->iommu_control = pbm->pbm_regs + FIRE_IOMMU_CONTROL; |
| 43 | iommu->iommu_tsbbase = pbm->pbm_regs + FIRE_IOMMU_TSBBASE; |
| 44 | iommu->iommu_flush = pbm->pbm_regs + FIRE_IOMMU_FLUSH; |
| 45 | iommu->iommu_flushinv = pbm->pbm_regs + FIRE_IOMMU_FLUSHINV; |
| 46 | |
| 47 | /* We use the main control/status register of FIRE as the write |
| 48 | * completion register. |
| 49 | */ |
| 50 | iommu->write_complete_reg = pbm->controller_regs + 0x410000UL; |
| 51 | |
| 52 | /* |
| 53 | * Invalidate TLB Entries. |
| 54 | */ |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 55 | upa_writeq(~(u64)0, iommu->iommu_flushinv); |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 56 | |
David S. Miller | c1b1a5f1 | 2008-03-19 04:52:48 -0700 | [diff] [blame] | 57 | err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask, |
| 58 | pbm->numa_node); |
David S. Miller | ad7ad57 | 2007-07-27 22:39:14 -0700 | [diff] [blame] | 59 | if (err) |
| 60 | return err; |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 61 | |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 62 | upa_writeq(__pa(iommu->page_table) | 0x7UL, iommu->iommu_tsbbase); |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 63 | |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 64 | control = upa_readq(iommu->iommu_control); |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 65 | control |= (0x00000400 /* TSB cache snoop enable */ | |
| 66 | 0x00000300 /* Cache mode */ | |
| 67 | 0x00000002 /* Bypass enable */ | |
| 68 | 0x00000001 /* Translation enable */); |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 69 | upa_writeq(control, iommu->iommu_control); |
David S. Miller | ad7ad57 | 2007-07-27 22:39:14 -0700 | [diff] [blame] | 70 | |
| 71 | return 0; |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 72 | } |
| 73 | |
David S. Miller | 9bb3c22 | 2007-08-30 22:33:25 -0700 | [diff] [blame] | 74 | #ifdef CONFIG_PCI_MSI |
| 75 | struct pci_msiq_entry { |
| 76 | u64 word0; |
| 77 | #define MSIQ_WORD0_RESV 0x8000000000000000UL |
| 78 | #define MSIQ_WORD0_FMT_TYPE 0x7f00000000000000UL |
| 79 | #define MSIQ_WORD0_FMT_TYPE_SHIFT 56 |
| 80 | #define MSIQ_WORD0_LEN 0x00ffc00000000000UL |
| 81 | #define MSIQ_WORD0_LEN_SHIFT 46 |
| 82 | #define MSIQ_WORD0_ADDR0 0x00003fff00000000UL |
| 83 | #define MSIQ_WORD0_ADDR0_SHIFT 32 |
| 84 | #define MSIQ_WORD0_RID 0x00000000ffff0000UL |
| 85 | #define MSIQ_WORD0_RID_SHIFT 16 |
| 86 | #define MSIQ_WORD0_DATA0 0x000000000000ffffUL |
| 87 | #define MSIQ_WORD0_DATA0_SHIFT 0 |
| 88 | |
| 89 | #define MSIQ_TYPE_MSG 0x6 |
| 90 | #define MSIQ_TYPE_MSI32 0xb |
| 91 | #define MSIQ_TYPE_MSI64 0xf |
| 92 | |
| 93 | u64 word1; |
| 94 | #define MSIQ_WORD1_ADDR1 0xffffffffffff0000UL |
| 95 | #define MSIQ_WORD1_ADDR1_SHIFT 16 |
| 96 | #define MSIQ_WORD1_DATA1 0x000000000000ffffUL |
| 97 | #define MSIQ_WORD1_DATA1_SHIFT 0 |
| 98 | |
| 99 | u64 resv[6]; |
| 100 | }; |
| 101 | |
| 102 | /* All MSI registers are offset from pbm->pbm_regs */ |
| 103 | #define EVENT_QUEUE_BASE_ADDR_REG 0x010000UL |
| 104 | #define EVENT_QUEUE_BASE_ADDR_ALL_ONES 0xfffc000000000000UL |
| 105 | |
| 106 | #define EVENT_QUEUE_CONTROL_SET(EQ) (0x011000UL + (EQ) * 0x8UL) |
| 107 | #define EVENT_QUEUE_CONTROL_SET_OFLOW 0x0200000000000000UL |
| 108 | #define EVENT_QUEUE_CONTROL_SET_EN 0x0000100000000000UL |
| 109 | |
| 110 | #define EVENT_QUEUE_CONTROL_CLEAR(EQ) (0x011200UL + (EQ) * 0x8UL) |
| 111 | #define EVENT_QUEUE_CONTROL_CLEAR_OF 0x0200000000000000UL |
| 112 | #define EVENT_QUEUE_CONTROL_CLEAR_E2I 0x0000800000000000UL |
| 113 | #define EVENT_QUEUE_CONTROL_CLEAR_DIS 0x0000100000000000UL |
| 114 | |
| 115 | #define EVENT_QUEUE_STATE(EQ) (0x011400UL + (EQ) * 0x8UL) |
| 116 | #define EVENT_QUEUE_STATE_MASK 0x0000000000000007UL |
| 117 | #define EVENT_QUEUE_STATE_IDLE 0x0000000000000001UL |
| 118 | #define EVENT_QUEUE_STATE_ACTIVE 0x0000000000000002UL |
| 119 | #define EVENT_QUEUE_STATE_ERROR 0x0000000000000004UL |
| 120 | |
| 121 | #define EVENT_QUEUE_TAIL(EQ) (0x011600UL + (EQ) * 0x8UL) |
| 122 | #define EVENT_QUEUE_TAIL_OFLOW 0x0200000000000000UL |
| 123 | #define EVENT_QUEUE_TAIL_VAL 0x000000000000007fUL |
| 124 | |
| 125 | #define EVENT_QUEUE_HEAD(EQ) (0x011800UL + (EQ) * 0x8UL) |
| 126 | #define EVENT_QUEUE_HEAD_VAL 0x000000000000007fUL |
| 127 | |
| 128 | #define MSI_MAP(MSI) (0x020000UL + (MSI) * 0x8UL) |
| 129 | #define MSI_MAP_VALID 0x8000000000000000UL |
| 130 | #define MSI_MAP_EQWR_N 0x4000000000000000UL |
| 131 | #define MSI_MAP_EQNUM 0x000000000000003fUL |
| 132 | |
| 133 | #define MSI_CLEAR(MSI) (0x028000UL + (MSI) * 0x8UL) |
| 134 | #define MSI_CLEAR_EQWR_N 0x4000000000000000UL |
| 135 | |
| 136 | #define IMONDO_DATA0 0x02C000UL |
| 137 | #define IMONDO_DATA0_DATA 0xffffffffffffffc0UL |
| 138 | |
| 139 | #define IMONDO_DATA1 0x02C008UL |
| 140 | #define IMONDO_DATA1_DATA 0xffffffffffffffffUL |
| 141 | |
| 142 | #define MSI_32BIT_ADDR 0x034000UL |
| 143 | #define MSI_32BIT_ADDR_VAL 0x00000000ffff0000UL |
| 144 | |
| 145 | #define MSI_64BIT_ADDR 0x034008UL |
| 146 | #define MSI_64BIT_ADDR_VAL 0xffffffffffff0000UL |
| 147 | |
David S. Miller | 759f89e | 2007-10-11 03:16:13 -0700 | [diff] [blame] | 148 | static int pci_fire_get_head(struct pci_pbm_info *pbm, unsigned long msiqid, |
| 149 | unsigned long *head) |
David S. Miller | 9bb3c22 | 2007-08-30 22:33:25 -0700 | [diff] [blame] | 150 | { |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 151 | *head = upa_readq(pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid)); |
David S. Miller | 759f89e | 2007-10-11 03:16:13 -0700 | [diff] [blame] | 152 | return 0; |
David S. Miller | 9bb3c22 | 2007-08-30 22:33:25 -0700 | [diff] [blame] | 153 | } |
| 154 | |
David S. Miller | 759f89e | 2007-10-11 03:16:13 -0700 | [diff] [blame] | 155 | static int pci_fire_dequeue_msi(struct pci_pbm_info *pbm, unsigned long msiqid, |
| 156 | unsigned long *head, unsigned long *msi) |
David S. Miller | 9bb3c22 | 2007-08-30 22:33:25 -0700 | [diff] [blame] | 157 | { |
David S. Miller | 759f89e | 2007-10-11 03:16:13 -0700 | [diff] [blame] | 158 | unsigned long type_fmt, type, msi_num; |
| 159 | struct pci_msiq_entry *base, *ep; |
David S. Miller | 9bb3c22 | 2007-08-30 22:33:25 -0700 | [diff] [blame] | 160 | |
David S. Miller | 759f89e | 2007-10-11 03:16:13 -0700 | [diff] [blame] | 161 | base = (pbm->msi_queues + ((msiqid - pbm->msiq_first) * 8192)); |
| 162 | ep = &base[*head]; |
David S. Miller | 9bb3c22 | 2007-08-30 22:33:25 -0700 | [diff] [blame] | 163 | |
David S. Miller | 759f89e | 2007-10-11 03:16:13 -0700 | [diff] [blame] | 164 | if ((ep->word0 & MSIQ_WORD0_FMT_TYPE) == 0) |
| 165 | return 0; |
| 166 | |
| 167 | type_fmt = ((ep->word0 & MSIQ_WORD0_FMT_TYPE) >> |
| 168 | MSIQ_WORD0_FMT_TYPE_SHIFT); |
| 169 | type = (type_fmt >> 3); |
| 170 | if (unlikely(type != MSIQ_TYPE_MSI32 && |
| 171 | type != MSIQ_TYPE_MSI64)) |
| 172 | return -EINVAL; |
| 173 | |
| 174 | *msi = msi_num = ((ep->word0 & MSIQ_WORD0_DATA0) >> |
| 175 | MSIQ_WORD0_DATA0_SHIFT); |
| 176 | |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 177 | upa_writeq(MSI_CLEAR_EQWR_N, pbm->pbm_regs + MSI_CLEAR(msi_num)); |
David S. Miller | 759f89e | 2007-10-11 03:16:13 -0700 | [diff] [blame] | 178 | |
| 179 | /* Clear the entry. */ |
| 180 | ep->word0 &= ~MSIQ_WORD0_FMT_TYPE; |
| 181 | |
| 182 | /* Go to next entry in ring. */ |
| 183 | (*head)++; |
| 184 | if (*head >= pbm->msiq_ent_count) |
| 185 | *head = 0; |
| 186 | |
| 187 | return 1; |
| 188 | } |
| 189 | |
| 190 | static int pci_fire_set_head(struct pci_pbm_info *pbm, unsigned long msiqid, |
| 191 | unsigned long head) |
| 192 | { |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 193 | upa_writeq(head, pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid)); |
David S. Miller | 759f89e | 2007-10-11 03:16:13 -0700 | [diff] [blame] | 194 | return 0; |
| 195 | } |
| 196 | |
| 197 | static int pci_fire_msi_setup(struct pci_pbm_info *pbm, unsigned long msiqid, |
| 198 | unsigned long msi, int is_msi64) |
| 199 | { |
| 200 | u64 val; |
| 201 | |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 202 | val = upa_readq(pbm->pbm_regs + MSI_MAP(msi)); |
David S. Miller | 759f89e | 2007-10-11 03:16:13 -0700 | [diff] [blame] | 203 | val &= ~(MSI_MAP_EQNUM); |
| 204 | val |= msiqid; |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 205 | upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi)); |
David S. Miller | 759f89e | 2007-10-11 03:16:13 -0700 | [diff] [blame] | 206 | |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 207 | upa_writeq(MSI_CLEAR_EQWR_N, pbm->pbm_regs + MSI_CLEAR(msi)); |
David S. Miller | 759f89e | 2007-10-11 03:16:13 -0700 | [diff] [blame] | 208 | |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 209 | val = upa_readq(pbm->pbm_regs + MSI_MAP(msi)); |
David S. Miller | 759f89e | 2007-10-11 03:16:13 -0700 | [diff] [blame] | 210 | val |= MSI_MAP_VALID; |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 211 | upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi)); |
David S. Miller | 9bb3c22 | 2007-08-30 22:33:25 -0700 | [diff] [blame] | 212 | |
| 213 | return 0; |
| 214 | } |
| 215 | |
David S. Miller | 759f89e | 2007-10-11 03:16:13 -0700 | [diff] [blame] | 216 | static int pci_fire_msi_teardown(struct pci_pbm_info *pbm, unsigned long msi) |
David S. Miller | 9bb3c22 | 2007-08-30 22:33:25 -0700 | [diff] [blame] | 217 | { |
David S. Miller | 759f89e | 2007-10-11 03:16:13 -0700 | [diff] [blame] | 218 | u64 val; |
| 219 | |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 220 | val = upa_readq(pbm->pbm_regs + MSI_MAP(msi)); |
David S. Miller | 759f89e | 2007-10-11 03:16:13 -0700 | [diff] [blame] | 221 | |
| 222 | val &= ~MSI_MAP_VALID; |
| 223 | |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 224 | upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi)); |
David S. Miller | 759f89e | 2007-10-11 03:16:13 -0700 | [diff] [blame] | 225 | |
| 226 | return 0; |
David S. Miller | 9bb3c22 | 2007-08-30 22:33:25 -0700 | [diff] [blame] | 227 | } |
| 228 | |
David S. Miller | 759f89e | 2007-10-11 03:16:13 -0700 | [diff] [blame] | 229 | static int pci_fire_msiq_alloc(struct pci_pbm_info *pbm) |
David S. Miller | 9bb3c22 | 2007-08-30 22:33:25 -0700 | [diff] [blame] | 230 | { |
| 231 | unsigned long pages, order, i; |
| 232 | |
| 233 | order = get_order(512 * 1024); |
| 234 | pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order); |
| 235 | if (pages == 0UL) { |
| 236 | printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n", |
| 237 | order); |
| 238 | return -ENOMEM; |
| 239 | } |
| 240 | memset((char *)pages, 0, PAGE_SIZE << order); |
| 241 | pbm->msi_queues = (void *) pages; |
| 242 | |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 243 | upa_writeq((EVENT_QUEUE_BASE_ADDR_ALL_ONES | |
| 244 | __pa(pbm->msi_queues)), |
| 245 | pbm->pbm_regs + EVENT_QUEUE_BASE_ADDR_REG); |
David S. Miller | 9bb3c22 | 2007-08-30 22:33:25 -0700 | [diff] [blame] | 246 | |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 247 | upa_writeq(pbm->portid << 6, pbm->pbm_regs + IMONDO_DATA0); |
| 248 | upa_writeq(0, pbm->pbm_regs + IMONDO_DATA1); |
David S. Miller | 9bb3c22 | 2007-08-30 22:33:25 -0700 | [diff] [blame] | 249 | |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 250 | upa_writeq(pbm->msi32_start, pbm->pbm_regs + MSI_32BIT_ADDR); |
| 251 | upa_writeq(pbm->msi64_start, pbm->pbm_regs + MSI_64BIT_ADDR); |
David S. Miller | 9bb3c22 | 2007-08-30 22:33:25 -0700 | [diff] [blame] | 252 | |
| 253 | for (i = 0; i < pbm->msiq_num; i++) { |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 254 | upa_writeq(0, pbm->pbm_regs + EVENT_QUEUE_HEAD(i)); |
| 255 | upa_writeq(0, pbm->pbm_regs + EVENT_QUEUE_TAIL(i)); |
David S. Miller | 9bb3c22 | 2007-08-30 22:33:25 -0700 | [diff] [blame] | 256 | } |
| 257 | |
| 258 | return 0; |
| 259 | } |
| 260 | |
David S. Miller | 759f89e | 2007-10-11 03:16:13 -0700 | [diff] [blame] | 261 | static void pci_fire_msiq_free(struct pci_pbm_info *pbm) |
David S. Miller | 9bb3c22 | 2007-08-30 22:33:25 -0700 | [diff] [blame] | 262 | { |
David S. Miller | 759f89e | 2007-10-11 03:16:13 -0700 | [diff] [blame] | 263 | unsigned long pages, order; |
David S. Miller | 9bb3c22 | 2007-08-30 22:33:25 -0700 | [diff] [blame] | 264 | |
David S. Miller | 759f89e | 2007-10-11 03:16:13 -0700 | [diff] [blame] | 265 | order = get_order(512 * 1024); |
| 266 | pages = (unsigned long) pbm->msi_queues; |
David S. Miller | 9bb3c22 | 2007-08-30 22:33:25 -0700 | [diff] [blame] | 267 | |
David S. Miller | 759f89e | 2007-10-11 03:16:13 -0700 | [diff] [blame] | 268 | free_pages(pages, order); |
| 269 | |
| 270 | pbm->msi_queues = NULL; |
David S. Miller | 9bb3c22 | 2007-08-30 22:33:25 -0700 | [diff] [blame] | 271 | } |
| 272 | |
David S. Miller | 759f89e | 2007-10-11 03:16:13 -0700 | [diff] [blame] | 273 | static int pci_fire_msiq_build_irq(struct pci_pbm_info *pbm, |
| 274 | unsigned long msiqid, |
| 275 | unsigned long devino) |
David S. Miller | 9bb3c22 | 2007-08-30 22:33:25 -0700 | [diff] [blame] | 276 | { |
David S. Miller | 759f89e | 2007-10-11 03:16:13 -0700 | [diff] [blame] | 277 | unsigned long cregs = (unsigned long) pbm->pbm_regs; |
| 278 | unsigned long imap_reg, iclr_reg, int_ctrlr; |
Sam Ravnborg | 44ed3c0 | 2011-01-22 11:32:20 +0000 | [diff] [blame] | 279 | unsigned int irq; |
David S. Miller | 759f89e | 2007-10-11 03:16:13 -0700 | [diff] [blame] | 280 | int fixup; |
David S. Miller | 9bb3c22 | 2007-08-30 22:33:25 -0700 | [diff] [blame] | 281 | u64 val; |
| 282 | |
David S. Miller | 759f89e | 2007-10-11 03:16:13 -0700 | [diff] [blame] | 283 | imap_reg = cregs + (0x001000UL + (devino * 0x08UL)); |
| 284 | iclr_reg = cregs + (0x001400UL + (devino * 0x08UL)); |
David S. Miller | 9bb3c22 | 2007-08-30 22:33:25 -0700 | [diff] [blame] | 285 | |
David S. Miller | 759f89e | 2007-10-11 03:16:13 -0700 | [diff] [blame] | 286 | /* XXX iterate amongst the 4 IRQ controllers XXX */ |
| 287 | int_ctrlr = (1UL << 6); |
David S. Miller | 9bb3c22 | 2007-08-30 22:33:25 -0700 | [diff] [blame] | 288 | |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 289 | val = upa_readq(imap_reg); |
David S. Miller | 759f89e | 2007-10-11 03:16:13 -0700 | [diff] [blame] | 290 | val |= (1UL << 63) | int_ctrlr; |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 291 | upa_writeq(val, imap_reg); |
David S. Miller | 9bb3c22 | 2007-08-30 22:33:25 -0700 | [diff] [blame] | 292 | |
David S. Miller | 759f89e | 2007-10-11 03:16:13 -0700 | [diff] [blame] | 293 | fixup = ((pbm->portid << 6) | devino) - int_ctrlr; |
David S. Miller | 9bb3c22 | 2007-08-30 22:33:25 -0700 | [diff] [blame] | 294 | |
Sam Ravnborg | 44ed3c0 | 2011-01-22 11:32:20 +0000 | [diff] [blame] | 295 | irq = build_irq(fixup, iclr_reg, imap_reg); |
| 296 | if (!irq) |
David S. Miller | 759f89e | 2007-10-11 03:16:13 -0700 | [diff] [blame] | 297 | return -ENOMEM; |
David S. Miller | 9bb3c22 | 2007-08-30 22:33:25 -0700 | [diff] [blame] | 298 | |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 299 | upa_writeq(EVENT_QUEUE_CONTROL_SET_EN, |
| 300 | pbm->pbm_regs + EVENT_QUEUE_CONTROL_SET(msiqid)); |
David S. Miller | 9bb3c22 | 2007-08-30 22:33:25 -0700 | [diff] [blame] | 301 | |
Sam Ravnborg | 44ed3c0 | 2011-01-22 11:32:20 +0000 | [diff] [blame] | 302 | return irq; |
David S. Miller | 9bb3c22 | 2007-08-30 22:33:25 -0700 | [diff] [blame] | 303 | } |
| 304 | |
David S. Miller | 759f89e | 2007-10-11 03:16:13 -0700 | [diff] [blame] | 305 | static const struct sparc64_msiq_ops pci_fire_msiq_ops = { |
| 306 | .get_head = pci_fire_get_head, |
| 307 | .dequeue_msi = pci_fire_dequeue_msi, |
| 308 | .set_head = pci_fire_set_head, |
| 309 | .msi_setup = pci_fire_msi_setup, |
| 310 | .msi_teardown = pci_fire_msi_teardown, |
| 311 | .msiq_alloc = pci_fire_msiq_alloc, |
| 312 | .msiq_free = pci_fire_msiq_free, |
| 313 | .msiq_build_irq = pci_fire_msiq_build_irq, |
| 314 | }; |
David S. Miller | 9bb3c22 | 2007-08-30 22:33:25 -0700 | [diff] [blame] | 315 | |
| 316 | static void pci_fire_msi_init(struct pci_pbm_info *pbm) |
| 317 | { |
David S. Miller | 759f89e | 2007-10-11 03:16:13 -0700 | [diff] [blame] | 318 | sparc64_pbm_msi_init(pbm, &pci_fire_msiq_ops); |
David S. Miller | 9bb3c22 | 2007-08-30 22:33:25 -0700 | [diff] [blame] | 319 | } |
| 320 | #else /* CONFIG_PCI_MSI */ |
| 321 | static void pci_fire_msi_init(struct pci_pbm_info *pbm) |
| 322 | { |
| 323 | } |
| 324 | #endif /* !(CONFIG_PCI_MSI) */ |
| 325 | |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 326 | /* Based at pbm->controller_regs */ |
| 327 | #define FIRE_PARITY_CONTROL 0x470010UL |
| 328 | #define FIRE_PARITY_ENAB 0x8000000000000000UL |
| 329 | #define FIRE_FATAL_RESET_CTL 0x471028UL |
| 330 | #define FIRE_FATAL_RESET_SPARE 0x0000000004000000UL |
| 331 | #define FIRE_FATAL_RESET_MB 0x0000000002000000UL |
| 332 | #define FIRE_FATAL_RESET_CPE 0x0000000000008000UL |
| 333 | #define FIRE_FATAL_RESET_APE 0x0000000000004000UL |
| 334 | #define FIRE_FATAL_RESET_PIO 0x0000000000000040UL |
| 335 | #define FIRE_FATAL_RESET_JW 0x0000000000000004UL |
| 336 | #define FIRE_FATAL_RESET_JI 0x0000000000000002UL |
| 337 | #define FIRE_FATAL_RESET_JR 0x0000000000000001UL |
| 338 | #define FIRE_CORE_INTR_ENABLE 0x471800UL |
| 339 | |
| 340 | /* Based at pbm->pbm_regs */ |
| 341 | #define FIRE_TLU_CTRL 0x80000UL |
| 342 | #define FIRE_TLU_CTRL_TIM 0x00000000da000000UL |
| 343 | #define FIRE_TLU_CTRL_QDET 0x0000000000000100UL |
| 344 | #define FIRE_TLU_CTRL_CFG 0x0000000000000001UL |
| 345 | #define FIRE_TLU_DEV_CTRL 0x90008UL |
| 346 | #define FIRE_TLU_LINK_CTRL 0x90020UL |
| 347 | #define FIRE_TLU_LINK_CTRL_CLK 0x0000000000000040UL |
| 348 | #define FIRE_LPU_RESET 0xe2008UL |
| 349 | #define FIRE_LPU_LLCFG 0xe2200UL |
| 350 | #define FIRE_LPU_LLCFG_VC0 0x0000000000000100UL |
| 351 | #define FIRE_LPU_FCTRL_UCTRL 0xe2240UL |
| 352 | #define FIRE_LPU_FCTRL_UCTRL_N 0x0000000000000002UL |
| 353 | #define FIRE_LPU_FCTRL_UCTRL_P 0x0000000000000001UL |
| 354 | #define FIRE_LPU_TXL_FIFOP 0xe2430UL |
| 355 | #define FIRE_LPU_LTSSM_CFG2 0xe2788UL |
| 356 | #define FIRE_LPU_LTSSM_CFG3 0xe2790UL |
| 357 | #define FIRE_LPU_LTSSM_CFG4 0xe2798UL |
| 358 | #define FIRE_LPU_LTSSM_CFG5 0xe27a0UL |
| 359 | #define FIRE_DMC_IENAB 0x31800UL |
| 360 | #define FIRE_DMC_DBG_SEL_A 0x53000UL |
| 361 | #define FIRE_DMC_DBG_SEL_B 0x53008UL |
| 362 | #define FIRE_PEC_IENAB 0x51800UL |
| 363 | |
| 364 | static void pci_fire_hw_init(struct pci_pbm_info *pbm) |
| 365 | { |
| 366 | u64 val; |
| 367 | |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 368 | upa_writeq(FIRE_PARITY_ENAB, |
| 369 | pbm->controller_regs + FIRE_PARITY_CONTROL); |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 370 | |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 371 | upa_writeq((FIRE_FATAL_RESET_SPARE | |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 372 | FIRE_FATAL_RESET_MB | |
| 373 | FIRE_FATAL_RESET_CPE | |
| 374 | FIRE_FATAL_RESET_APE | |
| 375 | FIRE_FATAL_RESET_PIO | |
| 376 | FIRE_FATAL_RESET_JW | |
| 377 | FIRE_FATAL_RESET_JI | |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 378 | FIRE_FATAL_RESET_JR), |
| 379 | pbm->controller_regs + FIRE_FATAL_RESET_CTL); |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 380 | |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 381 | upa_writeq(~(u64)0, pbm->controller_regs + FIRE_CORE_INTR_ENABLE); |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 382 | |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 383 | val = upa_readq(pbm->pbm_regs + FIRE_TLU_CTRL); |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 384 | val |= (FIRE_TLU_CTRL_TIM | |
| 385 | FIRE_TLU_CTRL_QDET | |
| 386 | FIRE_TLU_CTRL_CFG); |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 387 | upa_writeq(val, pbm->pbm_regs + FIRE_TLU_CTRL); |
| 388 | upa_writeq(0, pbm->pbm_regs + FIRE_TLU_DEV_CTRL); |
| 389 | upa_writeq(FIRE_TLU_LINK_CTRL_CLK, |
| 390 | pbm->pbm_regs + FIRE_TLU_LINK_CTRL); |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 391 | |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 392 | upa_writeq(0, pbm->pbm_regs + FIRE_LPU_RESET); |
| 393 | upa_writeq(FIRE_LPU_LLCFG_VC0, pbm->pbm_regs + FIRE_LPU_LLCFG); |
| 394 | upa_writeq((FIRE_LPU_FCTRL_UCTRL_N | FIRE_LPU_FCTRL_UCTRL_P), |
| 395 | pbm->pbm_regs + FIRE_LPU_FCTRL_UCTRL); |
| 396 | upa_writeq(((0xffff << 16) | (0x0000 << 0)), |
| 397 | pbm->pbm_regs + FIRE_LPU_TXL_FIFOP); |
| 398 | upa_writeq(3000000, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG2); |
| 399 | upa_writeq(500000, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG3); |
| 400 | upa_writeq((2 << 16) | (140 << 8), |
| 401 | pbm->pbm_regs + FIRE_LPU_LTSSM_CFG4); |
| 402 | upa_writeq(0, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG5); |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 403 | |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 404 | upa_writeq(~(u64)0, pbm->pbm_regs + FIRE_DMC_IENAB); |
| 405 | upa_writeq(0, pbm->pbm_regs + FIRE_DMC_DBG_SEL_A); |
| 406 | upa_writeq(0, pbm->pbm_regs + FIRE_DMC_DBG_SEL_B); |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 407 | |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 408 | upa_writeq(~(u64)0, pbm->pbm_regs + FIRE_PEC_IENAB); |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 409 | } |
| 410 | |
Greg Kroah-Hartman | 7c9503b | 2012-12-21 14:03:26 -0800 | [diff] [blame] | 411 | static int pci_fire_pbm_init(struct pci_pbm_info *pbm, |
| 412 | struct platform_device *op, u32 portid) |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 413 | { |
| 414 | const struct linux_prom64_registers *regs; |
Grant Likely | 61c7a08 | 2010-04-13 16:12:29 -0700 | [diff] [blame] | 415 | struct device_node *dp = op->dev.of_node; |
David S. Miller | 9bb3c22 | 2007-08-30 22:33:25 -0700 | [diff] [blame] | 416 | int err; |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 417 | |
David S. Miller | c1b1a5f1 | 2008-03-19 04:52:48 -0700 | [diff] [blame] | 418 | pbm->numa_node = -1; |
| 419 | |
David S. Miller | ca3dd88 | 2007-05-09 02:35:27 -0700 | [diff] [blame] | 420 | pbm->pci_ops = &sun4u_pci_ops; |
| 421 | pbm->config_space_reg_bits = 12; |
David S. Miller | 34768bc | 2007-05-07 23:06:27 -0700 | [diff] [blame] | 422 | |
David S. Miller | 6c108f1 | 2007-05-07 23:49:01 -0700 | [diff] [blame] | 423 | pbm->index = pci_num_pbms++; |
| 424 | |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 425 | pbm->portid = portid; |
David S. Miller | 22fecba | 2008-09-10 00:19:28 -0700 | [diff] [blame] | 426 | pbm->op = op; |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 427 | pbm->name = dp->full_name; |
| 428 | |
| 429 | regs = of_get_property(dp, "reg", NULL); |
| 430 | pbm->pbm_regs = regs[0].phys_addr; |
| 431 | pbm->controller_regs = regs[1].phys_addr - 0x410000UL; |
| 432 | |
| 433 | printk("%s: SUN4U PCIE Bus Module\n", pbm->name); |
| 434 | |
| 435 | pci_determine_mem_io_space(pbm); |
| 436 | |
David S. Miller | cfa0652 | 2007-05-07 21:51:41 -0700 | [diff] [blame] | 437 | pci_get_pbm_props(pbm); |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 438 | |
| 439 | pci_fire_hw_init(pbm); |
David S. Miller | ad7ad57 | 2007-07-27 22:39:14 -0700 | [diff] [blame] | 440 | |
David S. Miller | 9bb3c22 | 2007-08-30 22:33:25 -0700 | [diff] [blame] | 441 | err = pci_fire_pbm_iommu_init(pbm); |
| 442 | if (err) |
| 443 | return err; |
| 444 | |
| 445 | pci_fire_msi_init(pbm); |
| 446 | |
David S. Miller | e822358a | 2008-09-01 18:32:22 -0700 | [diff] [blame] | 447 | pbm->pci_bus = pci_scan_one_pbm(pbm, &op->dev); |
| 448 | |
| 449 | /* XXX register error interrupt handlers XXX */ |
David S. Miller | c804996 | 2008-08-30 03:12:38 -0700 | [diff] [blame] | 450 | |
David S. Miller | d3ae4b5 | 2008-09-09 23:54:02 -0700 | [diff] [blame] | 451 | pbm->next = pci_pbm_root; |
| 452 | pci_pbm_root = pbm; |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 453 | |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 454 | return 0; |
| 455 | } |
| 456 | |
Greg Kroah-Hartman | 7c9503b | 2012-12-21 14:03:26 -0800 | [diff] [blame] | 457 | static int fire_probe(struct platform_device *op) |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 458 | { |
Grant Likely | 61c7a08 | 2010-04-13 16:12:29 -0700 | [diff] [blame] | 459 | struct device_node *dp = op->dev.of_node; |
David S. Miller | 34768bc | 2007-05-07 23:06:27 -0700 | [diff] [blame] | 460 | struct pci_pbm_info *pbm; |
David S. Miller | c804996 | 2008-08-30 03:12:38 -0700 | [diff] [blame] | 461 | struct iommu *iommu; |
| 462 | u32 portid; |
| 463 | int err; |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 464 | |
David S. Miller | c804996 | 2008-08-30 03:12:38 -0700 | [diff] [blame] | 465 | portid = of_getintprop_default(dp, "portid", 0xff); |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 466 | |
David S. Miller | c804996 | 2008-08-30 03:12:38 -0700 | [diff] [blame] | 467 | err = -ENOMEM; |
David S. Miller | d3ae4b5 | 2008-09-09 23:54:02 -0700 | [diff] [blame] | 468 | pbm = kzalloc(sizeof(*pbm), GFP_KERNEL); |
| 469 | if (!pbm) { |
| 470 | printk(KERN_ERR PFX "Cannot allocate pci_pbminfo.\n"); |
David S. Miller | d7472c3 | 2008-08-31 01:33:52 -0700 | [diff] [blame] | 471 | goto out_err; |
David S. Miller | c804996 | 2008-08-30 03:12:38 -0700 | [diff] [blame] | 472 | } |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 473 | |
David S. Miller | d3ae4b5 | 2008-09-09 23:54:02 -0700 | [diff] [blame] | 474 | iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL); |
David S. Miller | c804996 | 2008-08-30 03:12:38 -0700 | [diff] [blame] | 475 | if (!iommu) { |
David S. Miller | d3ae4b5 | 2008-09-09 23:54:02 -0700 | [diff] [blame] | 476 | printk(KERN_ERR PFX "Cannot allocate PBM iommu.\n"); |
David S. Miller | d7472c3 | 2008-08-31 01:33:52 -0700 | [diff] [blame] | 477 | goto out_free_controller; |
David S. Miller | c804996 | 2008-08-30 03:12:38 -0700 | [diff] [blame] | 478 | } |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 479 | |
David S. Miller | d3ae4b5 | 2008-09-09 23:54:02 -0700 | [diff] [blame] | 480 | pbm->iommu = iommu; |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 481 | |
David S. Miller | d3ae4b5 | 2008-09-09 23:54:02 -0700 | [diff] [blame] | 482 | err = pci_fire_pbm_init(pbm, op, portid); |
| 483 | if (err) |
| 484 | goto out_free_iommu; |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 485 | |
David S. Miller | d3ae4b5 | 2008-09-09 23:54:02 -0700 | [diff] [blame] | 486 | dev_set_drvdata(&op->dev, pbm); |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 487 | |
David S. Miller | d3ae4b5 | 2008-09-09 23:54:02 -0700 | [diff] [blame] | 488 | return 0; |
David S. Miller | ad7ad57 | 2007-07-27 22:39:14 -0700 | [diff] [blame] | 489 | |
David S. Miller | d3ae4b5 | 2008-09-09 23:54:02 -0700 | [diff] [blame] | 490 | out_free_iommu: |
| 491 | kfree(pbm->iommu); |
David S. Miller | d7472c3 | 2008-08-31 01:33:52 -0700 | [diff] [blame] | 492 | |
| 493 | out_free_controller: |
David S. Miller | d3ae4b5 | 2008-09-09 23:54:02 -0700 | [diff] [blame] | 494 | kfree(pbm); |
David S. Miller | d7472c3 | 2008-08-31 01:33:52 -0700 | [diff] [blame] | 495 | |
| 496 | out_err: |
David S. Miller | c804996 | 2008-08-30 03:12:38 -0700 | [diff] [blame] | 497 | return err; |
David S. Miller | 861fe90 | 2007-05-02 17:31:36 -0700 | [diff] [blame] | 498 | } |
David S. Miller | c804996 | 2008-08-30 03:12:38 -0700 | [diff] [blame] | 499 | |
David S. Miller | 3628aa0 | 2011-03-30 17:37:56 -0700 | [diff] [blame] | 500 | static const struct of_device_id fire_match[] = { |
David S. Miller | c804996 | 2008-08-30 03:12:38 -0700 | [diff] [blame] | 501 | { |
| 502 | .name = "pci", |
| 503 | .compatible = "pciex108e,80f0", |
| 504 | }, |
| 505 | {}, |
| 506 | }; |
| 507 | |
Grant Likely | 4ebb24f | 2011-02-22 20:01:33 -0700 | [diff] [blame] | 508 | static struct platform_driver fire_driver = { |
Grant Likely | 4018294 | 2010-04-13 16:13:02 -0700 | [diff] [blame] | 509 | .driver = { |
| 510 | .name = DRIVER_NAME, |
Grant Likely | 4018294 | 2010-04-13 16:13:02 -0700 | [diff] [blame] | 511 | .of_match_table = fire_match, |
| 512 | }, |
David S. Miller | c804996 | 2008-08-30 03:12:38 -0700 | [diff] [blame] | 513 | .probe = fire_probe, |
| 514 | }; |
| 515 | |
| 516 | static int __init fire_init(void) |
| 517 | { |
Grant Likely | 4ebb24f | 2011-02-22 20:01:33 -0700 | [diff] [blame] | 518 | return platform_driver_register(&fire_driver); |
David S. Miller | c804996 | 2008-08-30 03:12:38 -0700 | [diff] [blame] | 519 | } |
| 520 | |
| 521 | subsys_initcall(fire_init); |