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Changbin Du4e37f052019-05-14 22:47:30 +08001.. SPDX-License-Identifier: GPL-2.0
2.. include:: <isonum.txt>
Zhang, Yanmin47402402006-07-31 15:15:18 +08003
Changbin Du4e37f052019-05-14 22:47:30 +08004===========================================================
5The PCI Express Advanced Error Reporting Driver Guide HOWTO
6===========================================================
Zhang, Yanmin47402402006-07-31 15:15:18 +08007
Changbin Du4e37f052019-05-14 22:47:30 +08008:Authors: - T. Long Nguyen <tom.l.nguyen@intel.com>
9 - Yanmin Zhang <yanmin.zhang@intel.com>
Zhang, Yanmin47402402006-07-31 15:15:18 +080010
Changbin Du4e37f052019-05-14 22:47:30 +080011:Copyright: |copy| 2006 Intel Corporation
12
13Overview
14===========
15
16About this guide
17----------------
Zhang, Yanmin47402402006-07-31 15:15:18 +080018
19This guide describes the basics of the PCI Express Advanced Error
20Reporting (AER) driver and provides information on how to use it, as
21well as how to enable the drivers of endpoint devices to conform with
22PCI Express AER driver.
23
Zhang, Yanmin47402402006-07-31 15:15:18 +080024
Changbin Du4e37f052019-05-14 22:47:30 +080025What is the PCI Express AER Driver?
26-----------------------------------
Zhang, Yanmin47402402006-07-31 15:15:18 +080027
28PCI Express error signaling can occur on the PCI Express link itself
29or on behalf of transactions initiated on the link. PCI Express
30defines two error reporting paradigms: the baseline capability and
31the Advanced Error Reporting capability. The baseline capability is
32required of all PCI Express components providing a minimum defined
33set of error reporting requirements. Advanced Error Reporting
34capability is implemented with a PCI Express advanced error reporting
35extended capability structure providing more robust error reporting.
36
37The PCI Express AER driver provides the infrastructure to support PCI
38Express Advanced Error Reporting capability. The PCI Express AER
39driver provides three basic functions:
40
Changbin Du4e37f052019-05-14 22:47:30 +080041 - Gathers the comprehensive error information if errors occurred.
42 - Reports error to the users.
43 - Performs error recovery actions.
Zhang, Yanmin47402402006-07-31 15:15:18 +080044
45AER driver only attaches root ports which support PCI-Express AER
46capability.
47
48
Changbin Du4e37f052019-05-14 22:47:30 +080049User Guide
50==========
Zhang, Yanmin47402402006-07-31 15:15:18 +080051
Changbin Du4e37f052019-05-14 22:47:30 +080052Include the PCI Express AER Root Driver into the Linux Kernel
53-------------------------------------------------------------
Zhang, Yanmin47402402006-07-31 15:15:18 +080054
55The PCI Express AER Root driver is a Root Port service driver attached
56to the PCI Express Port Bus driver. If a user wants to use it, the driver
57has to be compiled. Option CONFIG_PCIEAER supports this capability. It
58depends on CONFIG_PCIEPORTBUS, so pls. set CONFIG_PCIEPORTBUS=y and
59CONFIG_PCIEAER = y.
60
Changbin Du4e37f052019-05-14 22:47:30 +080061Load PCI Express AER Root Driver
62--------------------------------
Bjorn Helgaas7ece1412016-09-06 16:24:37 -050063
64Some systems have AER support in firmware. Enabling Linux AER support at
65the same time the firmware handles AER may result in unpredictable
66behavior. Therefore, Linux does not handle AER events unless the firmware
67grants AER control to the OS via the ACPI _OSC method. See the PCI FW 3.0
68Specification for details regarding _OSC usage.
Zhang, Yanmin47402402006-07-31 15:15:18 +080069
Changbin Du4e37f052019-05-14 22:47:30 +080070AER error output
71----------------
Bjorn Helgaas7ece1412016-09-06 16:24:37 -050072
73When a PCIe AER error is captured, an error message will be output to
74console. If it's a correctable error, it is output as a warning.
Zhang, Yanmin47402402006-07-31 15:15:18 +080075Otherwise, it is printed as an error. So users could choose different
76log level to filter out correctable error messages.
77
Changbin Du4e37f052019-05-14 22:47:30 +080078Below shows an example::
79
80 0000:50:00.0: PCIe Bus Error: severity=Uncorrected (Fatal), type=Transaction Layer, id=0500(Requester ID)
81 0000:50:00.0: device [8086:0329] error status/mask=00100000/00000000
82 0000:50:00.0: [20] Unsupported Request (First)
83 0000:50:00.0: TLP Header: 04000001 00200a03 05010000 00050100
Zhang, Yanmin47402402006-07-31 15:15:18 +080084
85In the example, 'Requester ID' means the ID of the device who sends
86the error message to root port. Pls. refer to pci express specs for
87other fields.
88
Changbin Du4e37f052019-05-14 22:47:30 +080089AER Statistics / Counters
90-------------------------
Rajat Jain81aa5202018-06-21 16:48:28 -070091
92When PCIe AER errors are captured, the counters / statistics are also exposed
93in the form of sysfs attributes which are documented at
94Documentation/ABI/testing/sysfs-bus-pci-devices-aer_stats
Zhang, Yanmin47402402006-07-31 15:15:18 +080095
Changbin Du4e37f052019-05-14 22:47:30 +080096Developer Guide
97===============
Zhang, Yanmin47402402006-07-31 15:15:18 +080098
99To enable AER aware support requires a software driver to configure
100the AER capability structure within its device and to provide callbacks.
101
102To support AER better, developers need understand how AER does work
103firstly.
104
105PCI Express errors are classified into two types: correctable errors
106and uncorrectable errors. This classification is based on the impacts
107of those errors, which may result in degraded performance or function
108failure.
109
110Correctable errors pose no impacts on the functionality of the
111interface. The PCI Express protocol can recover without any software
112intervention or any loss of data. These errors are detected and
113corrected by hardware. Unlike correctable errors, uncorrectable
114errors impact functionality of the interface. Uncorrectable errors
115can cause a particular transaction or a particular PCI Express link
116to be unreliable. Depending on those error conditions, uncorrectable
117errors are further classified into non-fatal errors and fatal errors.
118Non-fatal errors cause the particular transaction to be unreliable,
119but the PCI Express link itself is fully functional. Fatal errors, on
120the other hand, cause the link to be unreliable.
121
122When AER is enabled, a PCI Express device will automatically send an
Hidetoshi Seto89713422010-04-15 13:21:27 +0900123error message to the PCIe root port above it when the device captures
Zhang, Yanmin47402402006-07-31 15:15:18 +0800124an error. The Root Port, upon receiving an error reporting message,
125internally processes and logs the error message in its PCI Express
126capability structure. Error information being logged includes storing
127the error reporting agent's requestor ID into the Error Source
128Identification Registers and setting the error bits of the Root Error
129Status Register accordingly. If AER error reporting is enabled in Root
130Error Command Register, the Root Port generates an interrupt if an
131error is detected.
132
133Note that the errors as described above are related to the PCI Express
134hierarchy and links. These errors do not include any device specific
135errors because device specific errors will still get sent directly to
136the device driver.
137
Changbin Du4e37f052019-05-14 22:47:30 +0800138Configure the AER capability structure
139--------------------------------------
Zhang, Yanmin47402402006-07-31 15:15:18 +0800140
141AER aware drivers of PCI Express component need change the device
142control registers to enable AER. They also could change AER registers,
143including mask and severity registers. Helper function
144pci_enable_pcie_error_reporting could be used to enable AER. See
145section 3.3.
146
Changbin Du4e37f052019-05-14 22:47:30 +0800147Provide callbacks
148-----------------
Zhang, Yanmin47402402006-07-31 15:15:18 +0800149
Changbin Du4e37f052019-05-14 22:47:30 +0800150callback reset_link to reset pci express link
151~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Zhang, Yanmin47402402006-07-31 15:15:18 +0800152
153This callback is used to reset the pci express physical link when a
154fatal error happens. The root port aer service driver provides a
155default reset_link function, but different upstream ports might
156have different specifications to reset pci express link, so all
157upstream ports should provide their own reset_link functions.
158
Zhang, Yanmin47402402006-07-31 15:15:18 +0800159Section 3.2.2.2 provides more detailed info on when to call
160reset_link.
161
Changbin Du4e37f052019-05-14 22:47:30 +0800162PCI error-recovery callbacks
163~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Zhang, Yanmin47402402006-07-31 15:15:18 +0800164
165The PCI Express AER Root driver uses error callbacks to coordinate
166with downstream device drivers associated with a hierarchy in question
167when performing error recovery actions.
168
169Data struct pci_driver has a pointer, err_handler, to point to
170pci_error_handlers who consists of a couple of callback function
171pointers. AER driver follows the rules defined in
172pci-error-recovery.txt except pci express specific parts (e.g.
173reset_link). Pls. refer to pci-error-recovery.txt for detailed
174definitions of the callbacks.
175
176Below sections specify when to call the error callback functions.
177
Changbin Du4e37f052019-05-14 22:47:30 +0800178Correctable errors
179~~~~~~~~~~~~~~~~~~
Zhang, Yanmin47402402006-07-31 15:15:18 +0800180
181Correctable errors pose no impacts on the functionality of
182the interface. The PCI Express protocol can recover without any
183software intervention or any loss of data. These errors do not
184require any recovery actions. The AER driver clears the device's
185correctable error status register accordingly and logs these errors.
186
Changbin Du4e37f052019-05-14 22:47:30 +0800187Non-correctable (non-fatal and fatal) errors
188~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Zhang, Yanmin47402402006-07-31 15:15:18 +0800189
190If an error message indicates a non-fatal error, performing link reset
191at upstream is not required. The AER driver calls error_detected(dev,
192pci_channel_io_normal) to all drivers associated within a hierarchy in
Changbin Du4e37f052019-05-14 22:47:30 +0800193question. for example::
194
195 EndPoint<==>DownstreamPort B<==>UpstreamPort A<==>RootPort
196
Zhang, Yanmin47402402006-07-31 15:15:18 +0800197If Upstream port A captures an AER error, the hierarchy consists of
198Downstream port B and EndPoint.
199
200A driver may return PCI_ERS_RESULT_CAN_RECOVER,
201PCI_ERS_RESULT_DISCONNECT, or PCI_ERS_RESULT_NEED_RESET, depending on
202whether it can recover or the AER driver calls mmio_enabled as next.
203
204If an error message indicates a fatal error, kernel will broadcast
205error_detected(dev, pci_channel_io_frozen) to all drivers within
206a hierarchy in question. Then, performing link reset at upstream is
207necessary. As different kinds of devices might use different approaches
208to reset link, AER port service driver is required to provide the
Kuppuswamy Sathyanarayananb6cf1a42020-03-23 17:26:02 -0700209function to reset link via callback parameter of pcie_do_recovery()
210function. If reset_link is not NULL, recovery function will use it
211to reset the link. If error_detected returns PCI_ERS_RESULT_CAN_RECOVER
212and reset_link returns PCI_ERS_RESULT_RECOVERED, the error handling goes
Zhang, Yanmin47402402006-07-31 15:15:18 +0800213to mmio_enabled.
214
Changbin Du4e37f052019-05-14 22:47:30 +0800215helper functions
216----------------
217::
Zhang, Yanmin47402402006-07-31 15:15:18 +0800218
Changbin Du4e37f052019-05-14 22:47:30 +0800219 int pci_enable_pcie_error_reporting(struct pci_dev *dev);
220
Zhang, Yanmin47402402006-07-31 15:15:18 +0800221pci_enable_pcie_error_reporting enables the device to send error
222messages to root port when an error is detected. Note that devices
223don't enable the error reporting by default, so device drivers need
224call this function to enable it.
225
Changbin Du4e37f052019-05-14 22:47:30 +0800226::
227
228 int pci_disable_pcie_error_reporting(struct pci_dev *dev);
229
Zhang, Yanmin47402402006-07-31 15:15:18 +0800230pci_disable_pcie_error_reporting disables the device to send error
231messages to root port when an error is detected.
232
Changbin Du4e37f052019-05-14 22:47:30 +0800233::
234
Kuppuswamy Sathyanarayanan894020f2020-03-23 17:26:08 -0700235 int pci_aer_clear_nonfatal_status(struct pci_dev *dev);`
Changbin Du4e37f052019-05-14 22:47:30 +0800236
Kuppuswamy Sathyanarayanan894020f2020-03-23 17:26:08 -0700237pci_aer_clear_nonfatal_status clears non-fatal errors in the uncorrectable
Zhang, Yanmin47402402006-07-31 15:15:18 +0800238error status register.
239
Changbin Du4e37f052019-05-14 22:47:30 +0800240Frequent Asked Questions
241------------------------
Zhang, Yanmin47402402006-07-31 15:15:18 +0800242
Changbin Du4e37f052019-05-14 22:47:30 +0800243Q:
244 What happens if a PCI Express device driver does not provide an
245 error recovery handler (pci_driver->err_handler is equal to NULL)?
Zhang, Yanmin47402402006-07-31 15:15:18 +0800246
Changbin Du4e37f052019-05-14 22:47:30 +0800247A:
248 The devices attached with the driver won't be recovered. If the
249 error is fatal, kernel will print out warning messages. Please refer
250 to section 3 for more information.
Zhang, Yanmin47402402006-07-31 15:15:18 +0800251
Changbin Du4e37f052019-05-14 22:47:30 +0800252Q:
253 What happens if an upstream port service driver does not provide
254 callback reset_link?
Zhang, Yanmin47402402006-07-31 15:15:18 +0800255
Changbin Du4e37f052019-05-14 22:47:30 +0800256A:
257 Fatal error recovery will fail if the errors are reported by the
258 upstream ports who are attached by the service driver.
Zhang, Yanmin47402402006-07-31 15:15:18 +0800259
Changbin Du4e37f052019-05-14 22:47:30 +0800260Q:
261 How does this infrastructure deal with driver that is not PCI
262 Express aware?
Zhang, Yanmin47402402006-07-31 15:15:18 +0800263
Changbin Du4e37f052019-05-14 22:47:30 +0800264A:
265 This infrastructure calls the error callback functions of the
266 driver when an error happens. But if the driver is not aware of
267 PCI Express, the device might not report its own errors to root
268 port.
Zhang, Yanmin47402402006-07-31 15:15:18 +0800269
Changbin Du4e37f052019-05-14 22:47:30 +0800270Q:
271 What modifications will that driver need to make it compatible
272 with the PCI Express AER Root driver?
Zhang, Yanmin47402402006-07-31 15:15:18 +0800273
Changbin Du4e37f052019-05-14 22:47:30 +0800274A:
275 It could call the helper functions to enable AER in devices and
276 cleanup uncorrectable status register. Pls. refer to section 3.3.
Zhang, Yanmin47402402006-07-31 15:15:18 +0800277
Huang Yingbfe5a742009-04-24 10:45:31 +0800278
Changbin Du4e37f052019-05-14 22:47:30 +0800279Software error injection
280========================
Huang Yingbfe5a742009-04-24 10:45:31 +0800281
Hidetoshi Seto89713422010-04-15 13:21:27 +0900282Debugging PCIe AER error recovery code is quite difficult because it
Huang Yingbfe5a742009-04-24 10:45:31 +0800283is hard to trigger real hardware errors. Software based error
Hidetoshi Seto89713422010-04-15 13:21:27 +0900284injection can be used to fake various kinds of PCIe errors.
Huang Yingbfe5a742009-04-24 10:45:31 +0800285
Hidetoshi Seto89713422010-04-15 13:21:27 +0900286First you should enable PCIe AER software error injection in kernel
Huang Yingbfe5a742009-04-24 10:45:31 +0800287configuration, that is, following item should be in your .config.
288
289CONFIG_PCIEAER_INJECT=y or CONFIG_PCIEAER_INJECT=m
290
291After reboot with new kernel or insert the module, a device file named
292/dev/aer_inject should be created.
293
294Then, you need a user space tool named aer-inject, which can be gotten
295from:
Changbin Du4e37f052019-05-14 22:47:30 +0800296
Cao jin2eb6a4b2017-03-01 17:05:28 +0800297 https://git.kernel.org/cgit/linux/kernel/git/gong.chen/aer-inject.git/
Huang Yingbfe5a742009-04-24 10:45:31 +0800298
299More information about aer-inject can be found in the document comes
300with its source code.