Sudeep Holla | 6d6a1d8 | 2017-06-13 17:19:36 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * System Control and Power Interface (SCMI) Protocol based clock driver |
| 4 | * |
Cristian Marussi | beb076b | 2021-03-16 12:48:43 +0000 | [diff] [blame^] | 5 | * Copyright (C) 2018-2021 ARM Ltd. |
Sudeep Holla | 6d6a1d8 | 2017-06-13 17:19:36 +0100 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <linux/clk-provider.h> |
| 9 | #include <linux/device.h> |
| 10 | #include <linux/err.h> |
| 11 | #include <linux/of.h> |
| 12 | #include <linux/module.h> |
| 13 | #include <linux/scmi_protocol.h> |
| 14 | #include <asm/div64.h> |
| 15 | |
Cristian Marussi | beb076b | 2021-03-16 12:48:43 +0000 | [diff] [blame^] | 16 | static const struct scmi_clk_proto_ops *scmi_proto_clk_ops; |
| 17 | |
Sudeep Holla | 6d6a1d8 | 2017-06-13 17:19:36 +0100 | [diff] [blame] | 18 | struct scmi_clk { |
| 19 | u32 id; |
| 20 | struct clk_hw hw; |
| 21 | const struct scmi_clock_info *info; |
Cristian Marussi | beb076b | 2021-03-16 12:48:43 +0000 | [diff] [blame^] | 22 | const struct scmi_protocol_handle *ph; |
Sudeep Holla | 6d6a1d8 | 2017-06-13 17:19:36 +0100 | [diff] [blame] | 23 | }; |
| 24 | |
| 25 | #define to_scmi_clk(clk) container_of(clk, struct scmi_clk, hw) |
| 26 | |
| 27 | static unsigned long scmi_clk_recalc_rate(struct clk_hw *hw, |
| 28 | unsigned long parent_rate) |
| 29 | { |
| 30 | int ret; |
| 31 | u64 rate; |
| 32 | struct scmi_clk *clk = to_scmi_clk(hw); |
| 33 | |
Cristian Marussi | beb076b | 2021-03-16 12:48:43 +0000 | [diff] [blame^] | 34 | ret = scmi_proto_clk_ops->rate_get(clk->ph, clk->id, &rate); |
Sudeep Holla | 6d6a1d8 | 2017-06-13 17:19:36 +0100 | [diff] [blame] | 35 | if (ret) |
| 36 | return 0; |
| 37 | return rate; |
| 38 | } |
| 39 | |
| 40 | static long scmi_clk_round_rate(struct clk_hw *hw, unsigned long rate, |
| 41 | unsigned long *parent_rate) |
| 42 | { |
Sudeep Holla | 6d6a1d8 | 2017-06-13 17:19:36 +0100 | [diff] [blame] | 43 | u64 fmin, fmax, ftmp; |
| 44 | struct scmi_clk *clk = to_scmi_clk(hw); |
| 45 | |
| 46 | /* |
| 47 | * We can't figure out what rate it will be, so just return the |
| 48 | * rate back to the caller. scmi_clk_recalc_rate() will be called |
| 49 | * after the rate is set and we'll know what rate the clock is |
| 50 | * running at then. |
| 51 | */ |
| 52 | if (clk->info->rate_discrete) |
| 53 | return rate; |
| 54 | |
| 55 | fmin = clk->info->range.min_rate; |
| 56 | fmax = clk->info->range.max_rate; |
| 57 | if (rate <= fmin) |
| 58 | return fmin; |
| 59 | else if (rate >= fmax) |
| 60 | return fmax; |
| 61 | |
| 62 | ftmp = rate - fmin; |
| 63 | ftmp += clk->info->range.step_size - 1; /* to round up */ |
Amit Daniel Kachhap | 7a8655e | 2018-07-31 11:25:55 +0530 | [diff] [blame] | 64 | do_div(ftmp, clk->info->range.step_size); |
Sudeep Holla | 6d6a1d8 | 2017-06-13 17:19:36 +0100 | [diff] [blame] | 65 | |
Amit Daniel Kachhap | 7a8655e | 2018-07-31 11:25:55 +0530 | [diff] [blame] | 66 | return ftmp * clk->info->range.step_size + fmin; |
Sudeep Holla | 6d6a1d8 | 2017-06-13 17:19:36 +0100 | [diff] [blame] | 67 | } |
| 68 | |
| 69 | static int scmi_clk_set_rate(struct clk_hw *hw, unsigned long rate, |
| 70 | unsigned long parent_rate) |
| 71 | { |
| 72 | struct scmi_clk *clk = to_scmi_clk(hw); |
| 73 | |
Cristian Marussi | beb076b | 2021-03-16 12:48:43 +0000 | [diff] [blame^] | 74 | return scmi_proto_clk_ops->rate_set(clk->ph, clk->id, rate); |
Sudeep Holla | 6d6a1d8 | 2017-06-13 17:19:36 +0100 | [diff] [blame] | 75 | } |
| 76 | |
| 77 | static int scmi_clk_enable(struct clk_hw *hw) |
| 78 | { |
| 79 | struct scmi_clk *clk = to_scmi_clk(hw); |
| 80 | |
Cristian Marussi | beb076b | 2021-03-16 12:48:43 +0000 | [diff] [blame^] | 81 | return scmi_proto_clk_ops->enable(clk->ph, clk->id); |
Sudeep Holla | 6d6a1d8 | 2017-06-13 17:19:36 +0100 | [diff] [blame] | 82 | } |
| 83 | |
| 84 | static void scmi_clk_disable(struct clk_hw *hw) |
| 85 | { |
| 86 | struct scmi_clk *clk = to_scmi_clk(hw); |
| 87 | |
Cristian Marussi | beb076b | 2021-03-16 12:48:43 +0000 | [diff] [blame^] | 88 | scmi_proto_clk_ops->disable(clk->ph, clk->id); |
Sudeep Holla | 6d6a1d8 | 2017-06-13 17:19:36 +0100 | [diff] [blame] | 89 | } |
| 90 | |
| 91 | static const struct clk_ops scmi_clk_ops = { |
| 92 | .recalc_rate = scmi_clk_recalc_rate, |
| 93 | .round_rate = scmi_clk_round_rate, |
| 94 | .set_rate = scmi_clk_set_rate, |
| 95 | /* |
| 96 | * We can't provide enable/disable callback as we can't perform the same |
| 97 | * in atomic context. Since the clock framework provides standard API |
| 98 | * clk_prepare_enable that helps cases using clk_enable in non-atomic |
| 99 | * context, it should be fine providing prepare/unprepare. |
| 100 | */ |
| 101 | .prepare = scmi_clk_enable, |
| 102 | .unprepare = scmi_clk_disable, |
| 103 | }; |
| 104 | |
| 105 | static int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk) |
| 106 | { |
| 107 | int ret; |
Sudeep Holla | fcd2e0d | 2020-07-09 09:17:05 +0100 | [diff] [blame] | 108 | unsigned long min_rate, max_rate; |
| 109 | |
Sudeep Holla | 6d6a1d8 | 2017-06-13 17:19:36 +0100 | [diff] [blame] | 110 | struct clk_init_data init = { |
| 111 | .flags = CLK_GET_RATE_NOCACHE, |
| 112 | .num_parents = 0, |
| 113 | .ops = &scmi_clk_ops, |
| 114 | .name = sclk->info->name, |
| 115 | }; |
| 116 | |
| 117 | sclk->hw.init = &init; |
| 118 | ret = devm_clk_hw_register(dev, &sclk->hw); |
Sudeep Holla | fcd2e0d | 2020-07-09 09:17:05 +0100 | [diff] [blame] | 119 | if (ret) |
| 120 | return ret; |
| 121 | |
| 122 | if (sclk->info->rate_discrete) { |
| 123 | int num_rates = sclk->info->list.num_rates; |
| 124 | |
| 125 | if (num_rates <= 0) |
| 126 | return -EINVAL; |
| 127 | |
| 128 | min_rate = sclk->info->list.rates[0]; |
| 129 | max_rate = sclk->info->list.rates[num_rates - 1]; |
| 130 | } else { |
| 131 | min_rate = sclk->info->range.min_rate; |
| 132 | max_rate = sclk->info->range.max_rate; |
| 133 | } |
| 134 | |
| 135 | clk_hw_set_rate_range(&sclk->hw, min_rate, max_rate); |
Sudeep Holla | 6d6a1d8 | 2017-06-13 17:19:36 +0100 | [diff] [blame] | 136 | return ret; |
| 137 | } |
| 138 | |
| 139 | static int scmi_clocks_probe(struct scmi_device *sdev) |
| 140 | { |
| 141 | int idx, count, err; |
| 142 | struct clk_hw **hws; |
| 143 | struct clk_hw_onecell_data *clk_data; |
| 144 | struct device *dev = &sdev->dev; |
| 145 | struct device_node *np = dev->of_node; |
| 146 | const struct scmi_handle *handle = sdev->handle; |
Cristian Marussi | beb076b | 2021-03-16 12:48:43 +0000 | [diff] [blame^] | 147 | struct scmi_protocol_handle *ph; |
Sudeep Holla | 6d6a1d8 | 2017-06-13 17:19:36 +0100 | [diff] [blame] | 148 | |
Cristian Marussi | beb076b | 2021-03-16 12:48:43 +0000 | [diff] [blame^] | 149 | if (!handle) |
Sudeep Holla | 6d6a1d8 | 2017-06-13 17:19:36 +0100 | [diff] [blame] | 150 | return -ENODEV; |
| 151 | |
Cristian Marussi | beb076b | 2021-03-16 12:48:43 +0000 | [diff] [blame^] | 152 | scmi_proto_clk_ops = |
| 153 | handle->devm_protocol_get(sdev, SCMI_PROTOCOL_CLOCK, &ph); |
| 154 | if (IS_ERR(scmi_proto_clk_ops)) |
| 155 | return PTR_ERR(scmi_proto_clk_ops); |
| 156 | |
| 157 | count = scmi_proto_clk_ops->count_get(ph); |
Sudeep Holla | 6d6a1d8 | 2017-06-13 17:19:36 +0100 | [diff] [blame] | 158 | if (count < 0) { |
Rob Herring | e665f02 | 2018-08-28 10:44:29 -0500 | [diff] [blame] | 159 | dev_err(dev, "%pOFn: invalid clock output count\n", np); |
Sudeep Holla | 6d6a1d8 | 2017-06-13 17:19:36 +0100 | [diff] [blame] | 160 | return -EINVAL; |
| 161 | } |
| 162 | |
Kees Cook | 0ed2dd0 | 2018-05-08 16:08:53 -0700 | [diff] [blame] | 163 | clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, count), |
| 164 | GFP_KERNEL); |
Sudeep Holla | 6d6a1d8 | 2017-06-13 17:19:36 +0100 | [diff] [blame] | 165 | if (!clk_data) |
| 166 | return -ENOMEM; |
| 167 | |
| 168 | clk_data->num = count; |
| 169 | hws = clk_data->hws; |
| 170 | |
| 171 | for (idx = 0; idx < count; idx++) { |
| 172 | struct scmi_clk *sclk; |
| 173 | |
| 174 | sclk = devm_kzalloc(dev, sizeof(*sclk), GFP_KERNEL); |
| 175 | if (!sclk) |
| 176 | return -ENOMEM; |
| 177 | |
Cristian Marussi | beb076b | 2021-03-16 12:48:43 +0000 | [diff] [blame^] | 178 | sclk->info = scmi_proto_clk_ops->info_get(ph, idx); |
Sudeep Holla | 6d6a1d8 | 2017-06-13 17:19:36 +0100 | [diff] [blame] | 179 | if (!sclk->info) { |
| 180 | dev_dbg(dev, "invalid clock info for idx %d\n", idx); |
| 181 | continue; |
| 182 | } |
| 183 | |
| 184 | sclk->id = idx; |
Cristian Marussi | beb076b | 2021-03-16 12:48:43 +0000 | [diff] [blame^] | 185 | sclk->ph = ph; |
Sudeep Holla | 6d6a1d8 | 2017-06-13 17:19:36 +0100 | [diff] [blame] | 186 | |
| 187 | err = scmi_clk_ops_init(dev, sclk); |
| 188 | if (err) { |
| 189 | dev_err(dev, "failed to register clock %d\n", idx); |
| 190 | devm_kfree(dev, sclk); |
| 191 | hws[idx] = NULL; |
| 192 | } else { |
| 193 | dev_dbg(dev, "Registered clock:%s\n", sclk->info->name); |
| 194 | hws[idx] = &sclk->hw; |
| 195 | } |
| 196 | } |
| 197 | |
Sudeep Holla | 7f9badf | 2018-03-20 11:22:48 +0000 | [diff] [blame] | 198 | return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, |
| 199 | clk_data); |
Sudeep Holla | 6d6a1d8 | 2017-06-13 17:19:36 +0100 | [diff] [blame] | 200 | } |
| 201 | |
| 202 | static const struct scmi_device_id scmi_id_table[] = { |
Sudeep Holla | 43998df | 2019-11-06 17:55:47 +0000 | [diff] [blame] | 203 | { SCMI_PROTOCOL_CLOCK, "clocks" }, |
Sudeep Holla | 6d6a1d8 | 2017-06-13 17:19:36 +0100 | [diff] [blame] | 204 | { }, |
| 205 | }; |
| 206 | MODULE_DEVICE_TABLE(scmi, scmi_id_table); |
| 207 | |
| 208 | static struct scmi_driver scmi_clocks_driver = { |
| 209 | .name = "scmi-clocks", |
| 210 | .probe = scmi_clocks_probe, |
Sudeep Holla | 6d6a1d8 | 2017-06-13 17:19:36 +0100 | [diff] [blame] | 211 | .id_table = scmi_id_table, |
| 212 | }; |
| 213 | module_scmi_driver(scmi_clocks_driver); |
| 214 | |
| 215 | MODULE_AUTHOR("Sudeep Holla <sudeep.holla@arm.com>"); |
| 216 | MODULE_DESCRIPTION("ARM SCMI clock driver"); |
| 217 | MODULE_LICENSE("GPL v2"); |