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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / bb4b3b7762735cdaba5a40fd94c9303d9ffa147a / . / drivers / mmc / host / sdhci-esdhc.h
blob: dfa58f8b8dfaea79bc4ca18967714430933057fc [file] [log] [blame]
Wolfram Sang80872e22010-10-15 12:21:03 +0200[diff] [blame]1/*
2 * Freescale eSDHC controller driver generics for OF and pltfm.
3 *
4 * Copyright (c) 2007 Freescale Semiconductor, Inc.
5 * Copyright (c) 2009 MontaVista Software, Inc.
6 * Copyright (c) 2010 Pengutronix e.K.
7 * Author: Wolfram Sang <w.sang@pengutronix.de>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 */
13
14#ifndef _DRIVERS_MMC_SDHCI_ESDHC_H
15#define _DRIVERS_MMC_SDHCI_ESDHC_H
16
17/*
18 * Ops and quirks for the Freescale eSDHC controller.
19 */
20
21#define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \
Benoît Thébaudeaucbb45092017-05-30 11:14:08 +0200[diff] [blame]22 SDHCI_QUIRK_32BIT_DMA_ADDR | \
Wolfram Sang80872e22010-10-15 12:21:03 +0200[diff] [blame]23 SDHCI_QUIRK_NO_BUSY_IRQ | \
Wolfram Sang80872e22010-10-15 12:21:03 +0200[diff] [blame]24 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \
Yangbo Lu67b589a2015-07-10 11:42:37 +0800[diff] [blame]25 SDHCI_QUIRK_PIO_NEEDS_DELAY | \
26 SDHCI_QUIRK_NO_HISPD_BIT)
Wolfram Sang80872e22010-10-15 12:21:03 +0200[diff] [blame]27
Wolfram Sang80872e22010-10-15 12:21:03 +0200[diff] [blame]28/* pltfm-specific */
29#define ESDHC_HOST_CONTROL_LE 0x20
30
Oded Gabbay66b50a02013-06-27 12:00:05 -0400[diff] [blame]31/*
yangbo lua6b44882016-12-26 17:46:29 +0800[diff] [blame]32 * eSDHC register definition
Oded Gabbay66b50a02013-06-27 12:00:05 -0400[diff] [blame]33 */
Oded Gabbay66b50a02013-06-27 12:00:05 -0400[diff] [blame]34
yangbo lue87d2db2016-12-26 17:46:30 +0800[diff] [blame]35/* Present State Register */
36#define ESDHC_PRSSTAT 0x24
37#define ESDHC_CLOCK_STABLE 0x00000008
38
yangbo lua6b44882016-12-26 17:46:29 +0800[diff] [blame]39/* Protocol Control Register */
40#define ESDHC_PROCTL 0x28
yangbo luea356452017-04-20 16:14:41 +0800[diff] [blame]41#define ESDHC_VOLT_SEL 0x00000400
yangbo lua6b44882016-12-26 17:46:29 +0800[diff] [blame]42#define ESDHC_CTRL_4BITBUS (0x1 << 1)
43#define ESDHC_CTRL_8BITBUS (0x2 << 1)
44#define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
45#define ESDHC_HOST_CONTROL_RES 0x01
Wolfram Sang80872e22010-10-15 12:21:03 +0200[diff] [blame]46
yangbo lua6b44882016-12-26 17:46:29 +0800[diff] [blame]47/* System Control Register */
48#define ESDHC_SYSTEM_CONTROL 0x2c
49#define ESDHC_CLOCK_MASK 0x0000fff0
50#define ESDHC_PREDIV_SHIFT 8
51#define ESDHC_DIVIDER_SHIFT 4
yangbo lue87d2db2016-12-26 17:46:30 +0800[diff] [blame]52#define ESDHC_CLOCK_SDCLKEN 0x00000008
yangbo lua6b44882016-12-26 17:46:29 +0800[diff] [blame]53#define ESDHC_CLOCK_PEREN 0x00000004
54#define ESDHC_CLOCK_HCKEN 0x00000002
55#define ESDHC_CLOCK_IPGEN 0x00000001
56
yangbo lu2f3110c2017-08-15 10:17:03 +0800[diff] [blame]57/* Host Controller Capabilities Register 2 */
58#define ESDHC_CAPABILITIES_1 0x114
59
yangbo luba49cbd2017-04-20 16:14:42 +0800[diff] [blame]60/* Tuning Block Control Register */
61#define ESDHC_TBCTL 0x120
62#define ESDHC_TB_EN 0x00000004
63
yangbo lua6b44882016-12-26 17:46:29 +0800[diff] [blame]64/* Control Register for DMA transfer */
65#define ESDHC_DMA_SYSCTL 0x40c
yangbo lu19c3a0e2017-04-20 16:14:40 +0800[diff] [blame]66#define ESDHC_PERIPHERAL_CLK_SEL 0x00080000
yangbo luba49cbd2017-04-20 16:14:42 +0800[diff] [blame]67#define ESDHC_FLUSH_ASYNC_FIFO 0x00040000
yangbo lua6b44882016-12-26 17:46:29 +0800[diff] [blame]68#define ESDHC_DMA_SNOOP 0x00000040
Wolfram Sang80872e22010-10-15 12:21:03 +0200[diff] [blame]69
Wolfram Sang80872e22010-10-15 12:21:03 +0200[diff] [blame]70#endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */