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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / bae9e13fc55cbc5ae25409385b2f1ba9187082d0 / . / sound / soc / codecs / cs35l41-tables.c
blob: 9d1a7d7dd24d13a180b9ceb889b6830cff9ecda0 [file] [log] [blame]
David Rhodes6450ef52021-09-07 17:57:18 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2//
3// cs35l41-tables.c -- CS35L41 ALSA SoC audio driver
4//
5// Copyright 2017-2021 Cirrus Logic, Inc.
6//
7// Author: David Rhodes <david.rhodes@cirrus.com>
8
9#include "cs35l41.h"
10
11const struct reg_default cs35l41_reg[CS35L41_MAX_CACHE_REG] = {
Charles Keepax4295c8c2021-09-14 15:13:49 +0100[diff] [blame]12 { CS35L41_PWR_CTRL1, 0x00000000 },
13 { CS35L41_PWR_CTRL3, 0x01000010 },
14 { CS35L41_GPIO_PAD_CONTROL, 0x00000000 },
15 { CS35L41_SP_ENABLES, 0x00000000 },
16 { CS35L41_SP_RATE_CTRL, 0x00000028 },
17 { CS35L41_SP_FORMAT, 0x18180200 },
18 { CS35L41_SP_HIZ_CTRL, 0x00000002 },
19 { CS35L41_SP_FRAME_TX_SLOT, 0x03020100 },
20 { CS35L41_SP_FRAME_RX_SLOT, 0x00000100 },
21 { CS35L41_SP_TX_WL, 0x00000018 },
22 { CS35L41_SP_RX_WL, 0x00000018 },
23 { CS35L41_DAC_PCM1_SRC, 0x00000008 },
24 { CS35L41_ASP_TX1_SRC, 0x00000018 },
25 { CS35L41_ASP_TX2_SRC, 0x00000019 },
26 { CS35L41_ASP_TX3_SRC, 0x00000020 },
27 { CS35L41_ASP_TX4_SRC, 0x00000021 },
28 { CS35L41_DSP1_RX1_SRC, 0x00000008 },
29 { CS35L41_DSP1_RX2_SRC, 0x00000009 },
30 { CS35L41_DSP1_RX3_SRC, 0x00000018 },
31 { CS35L41_DSP1_RX4_SRC, 0x00000019 },
32 { CS35L41_DSP1_RX5_SRC, 0x00000020 },
33 { CS35L41_DSP1_RX6_SRC, 0x00000021 },
34 { CS35L41_DSP1_RX7_SRC, 0x0000003A },
35 { CS35L41_DSP1_RX8_SRC, 0x00000001 },
36 { CS35L41_NGATE1_SRC, 0x00000008 },
37 { CS35L41_NGATE2_SRC, 0x00000009 },
38 { CS35L41_AMP_DIG_VOL_CTRL, 0x00008000 },
39 { CS35L41_CLASSH_CFG, 0x000B0405 },
40 { CS35L41_WKFET_CFG, 0x00000111 },
41 { CS35L41_NG_CFG, 0x00000033 },
42 { CS35L41_AMP_GAIN_CTRL, 0x00000273 },
43 { CS35L41_GPIO1_CTRL1, 0xE1000001 },
44 { CS35L41_GPIO2_CTRL1, 0xE1000001 },
45 { CS35L41_MIXER_NGATE_CFG, 0x00000000 },
46 { CS35L41_MIXER_NGATE_CH1_CFG, 0x00000303 },
47 { CS35L41_MIXER_NGATE_CH2_CFG, 0x00000303 },
David Rhodes6450ef52021-09-07 17:57:18 -0500[diff] [blame]48};
49
50bool cs35l41_readable_reg(struct device *dev, unsigned int reg)
51{
52 switch (reg) {
53 case CS35L41_DEVID:
54 case CS35L41_REVID:
55 case CS35L41_FABID:
56 case CS35L41_RELID:
57 case CS35L41_OTPID:
58 case CS35L41_TEST_KEY_CTL:
59 case CS35L41_USER_KEY_CTL:
60 case CS35L41_OTP_CTRL0:
61 case CS35L41_OTP_CTRL3:
62 case CS35L41_OTP_CTRL4:
63 case CS35L41_OTP_CTRL5:
64 case CS35L41_OTP_CTRL6:
65 case CS35L41_OTP_CTRL7:
66 case CS35L41_OTP_CTRL8:
67 case CS35L41_PWR_CTRL1:
68 case CS35L41_PWR_CTRL2:
69 case CS35L41_PWR_CTRL3:
70 case CS35L41_CTRL_OVRRIDE:
71 case CS35L41_AMP_OUT_MUTE:
72 case CS35L41_PROTECT_REL_ERR_IGN:
73 case CS35L41_GPIO_PAD_CONTROL:
74 case CS35L41_JTAG_CONTROL:
75 case CS35L41_PLL_CLK_CTRL:
76 case CS35L41_DSP_CLK_CTRL:
77 case CS35L41_GLOBAL_CLK_CTRL:
78 case CS35L41_DATA_FS_SEL:
79 case CS35L41_MDSYNC_EN:
80 case CS35L41_MDSYNC_TX_ID:
81 case CS35L41_MDSYNC_PWR_CTRL:
82 case CS35L41_MDSYNC_DATA_TX:
83 case CS35L41_MDSYNC_TX_STATUS:
84 case CS35L41_MDSYNC_DATA_RX:
85 case CS35L41_MDSYNC_RX_STATUS:
86 case CS35L41_MDSYNC_ERR_STATUS:
87 case CS35L41_MDSYNC_SYNC_PTE2:
88 case CS35L41_MDSYNC_SYNC_PTE3:
89 case CS35L41_MDSYNC_SYNC_MSM_STATUS:
90 case CS35L41_BSTCVRT_VCTRL1:
91 case CS35L41_BSTCVRT_VCTRL2:
92 case CS35L41_BSTCVRT_PEAK_CUR:
93 case CS35L41_BSTCVRT_SFT_RAMP:
94 case CS35L41_BSTCVRT_COEFF:
95 case CS35L41_BSTCVRT_SLOPE_LBST:
96 case CS35L41_BSTCVRT_SW_FREQ:
97 case CS35L41_BSTCVRT_DCM_CTRL:
98 case CS35L41_BSTCVRT_DCM_MODE_FORCE:
99 case CS35L41_BSTCVRT_OVERVOLT_CTRL:
100 case CS35L41_VI_VOL_POL:
101 case CS35L41_DTEMP_WARN_THLD:
102 case CS35L41_DTEMP_CFG:
103 case CS35L41_DTEMP_EN:
104 case CS35L41_VPVBST_FS_SEL:
105 case CS35L41_SP_ENABLES:
106 case CS35L41_SP_RATE_CTRL:
107 case CS35L41_SP_FORMAT:
108 case CS35L41_SP_HIZ_CTRL:
109 case CS35L41_SP_FRAME_TX_SLOT:
110 case CS35L41_SP_FRAME_RX_SLOT:
111 case CS35L41_SP_TX_WL:
112 case CS35L41_SP_RX_WL:
113 case CS35L41_DAC_PCM1_SRC:
114 case CS35L41_ASP_TX1_SRC:
115 case CS35L41_ASP_TX2_SRC:
116 case CS35L41_ASP_TX3_SRC:
117 case CS35L41_ASP_TX4_SRC:
118 case CS35L41_DSP1_RX1_SRC:
119 case CS35L41_DSP1_RX2_SRC:
120 case CS35L41_DSP1_RX3_SRC:
121 case CS35L41_DSP1_RX4_SRC:
122 case CS35L41_DSP1_RX5_SRC:
123 case CS35L41_DSP1_RX6_SRC:
124 case CS35L41_DSP1_RX7_SRC:
125 case CS35L41_DSP1_RX8_SRC:
126 case CS35L41_NGATE1_SRC:
127 case CS35L41_NGATE2_SRC:
128 case CS35L41_AMP_DIG_VOL_CTRL:
129 case CS35L41_VPBR_CFG:
130 case CS35L41_VBBR_CFG:
131 case CS35L41_VPBR_STATUS:
132 case CS35L41_VBBR_STATUS:
133 case CS35L41_OVERTEMP_CFG:
134 case CS35L41_AMP_ERR_VOL:
135 case CS35L41_VOL_STATUS_TO_DSP:
136 case CS35L41_CLASSH_CFG:
137 case CS35L41_WKFET_CFG:
138 case CS35L41_NG_CFG:
139 case CS35L41_AMP_GAIN_CTRL:
140 case CS35L41_DAC_MSM_CFG:
141 case CS35L41_IRQ1_CFG:
142 case CS35L41_IRQ1_STATUS:
143 case CS35L41_IRQ1_STATUS1:
144 case CS35L41_IRQ1_STATUS2:
145 case CS35L41_IRQ1_STATUS3:
146 case CS35L41_IRQ1_STATUS4:
147 case CS35L41_IRQ1_RAW_STATUS1:
148 case CS35L41_IRQ1_RAW_STATUS2:
149 case CS35L41_IRQ1_RAW_STATUS3:
150 case CS35L41_IRQ1_RAW_STATUS4:
151 case CS35L41_IRQ1_MASK1:
152 case CS35L41_IRQ1_MASK2:
153 case CS35L41_IRQ1_MASK3:
154 case CS35L41_IRQ1_MASK4:
155 case CS35L41_IRQ1_FRC1:
156 case CS35L41_IRQ1_FRC2:
157 case CS35L41_IRQ1_FRC3:
158 case CS35L41_IRQ1_FRC4:
159 case CS35L41_IRQ1_EDGE1:
160 case CS35L41_IRQ1_EDGE4:
161 case CS35L41_IRQ1_POL1:
162 case CS35L41_IRQ1_POL2:
163 case CS35L41_IRQ1_POL3:
164 case CS35L41_IRQ1_POL4:
165 case CS35L41_IRQ1_DB3:
166 case CS35L41_IRQ2_CFG:
167 case CS35L41_IRQ2_STATUS:
168 case CS35L41_IRQ2_STATUS1:
169 case CS35L41_IRQ2_STATUS2:
170 case CS35L41_IRQ2_STATUS3:
171 case CS35L41_IRQ2_STATUS4:
172 case CS35L41_IRQ2_RAW_STATUS1:
173 case CS35L41_IRQ2_RAW_STATUS2:
174 case CS35L41_IRQ2_RAW_STATUS3:
175 case CS35L41_IRQ2_RAW_STATUS4:
176 case CS35L41_IRQ2_MASK1:
177 case CS35L41_IRQ2_MASK2:
178 case CS35L41_IRQ2_MASK3:
179 case CS35L41_IRQ2_MASK4:
180 case CS35L41_IRQ2_FRC1:
181 case CS35L41_IRQ2_FRC2:
182 case CS35L41_IRQ2_FRC3:
183 case CS35L41_IRQ2_FRC4:
184 case CS35L41_IRQ2_EDGE1:
185 case CS35L41_IRQ2_EDGE4:
186 case CS35L41_IRQ2_POL1:
187 case CS35L41_IRQ2_POL2:
188 case CS35L41_IRQ2_POL3:
189 case CS35L41_IRQ2_POL4:
190 case CS35L41_IRQ2_DB3:
191 case CS35L41_GPIO_STATUS1:
192 case CS35L41_GPIO1_CTRL1:
193 case CS35L41_GPIO2_CTRL1:
194 case CS35L41_MIXER_NGATE_CFG:
195 case CS35L41_MIXER_NGATE_CH1_CFG:
196 case CS35L41_MIXER_NGATE_CH2_CFG:
197 case CS35L41_DSP_MBOX_1 ... CS35L41_DSP_VIRT2_MBOX_8:
198 case CS35L41_CLOCK_DETECT_1:
199 case CS35L41_DIE_STS1:
200 case CS35L41_DIE_STS2:
201 case CS35L41_TEMP_CAL1:
202 case CS35L41_TEMP_CAL2:
David Rhodesbae9e132021-10-29 16:40:28 -0500[diff] [blame^]203 case CS35L41_DSP1_TIMESTAMP_COUNT:
204 case CS35L41_DSP1_SYS_ID:
205 case CS35L41_DSP1_SYS_VERSION:
206 case CS35L41_DSP1_SYS_CORE_ID:
207 case CS35L41_DSP1_SYS_AHB_ADDR:
208 case CS35L41_DSP1_SYS_XSRAM_SIZE:
209 case CS35L41_DSP1_SYS_YSRAM_SIZE:
210 case CS35L41_DSP1_SYS_PSRAM_SIZE:
211 case CS35L41_DSP1_SYS_PM_BOOT_SIZE:
212 case CS35L41_DSP1_SYS_FEATURES:
213 case CS35L41_DSP1_SYS_FIR_FILTERS:
214 case CS35L41_DSP1_SYS_LMS_FILTERS:
215 case CS35L41_DSP1_SYS_XM_BANK_SIZE:
216 case CS35L41_DSP1_SYS_YM_BANK_SIZE:
217 case CS35L41_DSP1_SYS_PM_BANK_SIZE:
218 case CS35L41_DSP1_RX1_RATE:
219 case CS35L41_DSP1_RX2_RATE:
220 case CS35L41_DSP1_RX3_RATE:
221 case CS35L41_DSP1_RX4_RATE:
222 case CS35L41_DSP1_RX5_RATE:
223 case CS35L41_DSP1_RX6_RATE:
224 case CS35L41_DSP1_RX7_RATE:
225 case CS35L41_DSP1_RX8_RATE:
226 case CS35L41_DSP1_TX1_RATE:
227 case CS35L41_DSP1_TX2_RATE:
228 case CS35L41_DSP1_TX3_RATE:
229 case CS35L41_DSP1_TX4_RATE:
230 case CS35L41_DSP1_TX5_RATE:
231 case CS35L41_DSP1_TX6_RATE:
232 case CS35L41_DSP1_TX7_RATE:
233 case CS35L41_DSP1_TX8_RATE:
234 case CS35L41_DSP1_SCRATCH1:
235 case CS35L41_DSP1_SCRATCH2:
236 case CS35L41_DSP1_SCRATCH3:
237 case CS35L41_DSP1_SCRATCH4:
238 case CS35L41_DSP1_CCM_CORE_CTRL:
239 case CS35L41_DSP1_CCM_CLK_OVERRIDE:
240 case CS35L41_DSP1_XM_MSTR_EN:
241 case CS35L41_DSP1_XM_CORE_PRI:
242 case CS35L41_DSP1_XM_AHB_PACK_PL_PRI:
243 case CS35L41_DSP1_XM_AHB_UP_PL_PRI:
244 case CS35L41_DSP1_XM_ACCEL_PL0_PRI:
245 case CS35L41_DSP1_XM_NPL0_PRI:
246 case CS35L41_DSP1_YM_MSTR_EN:
247 case CS35L41_DSP1_YM_CORE_PRI:
248 case CS35L41_DSP1_YM_AHB_PACK_PL_PRI:
249 case CS35L41_DSP1_YM_AHB_UP_PL_PRI:
250 case CS35L41_DSP1_YM_ACCEL_PL0_PRI:
251 case CS35L41_DSP1_YM_NPL0_PRI:
252 case CS35L41_DSP1_MPU_XM_ACCESS0:
253 case CS35L41_DSP1_MPU_YM_ACCESS0:
254 case CS35L41_DSP1_MPU_WNDW_ACCESS0:
255 case CS35L41_DSP1_MPU_XREG_ACCESS0:
256 case CS35L41_DSP1_MPU_YREG_ACCESS0:
257 case CS35L41_DSP1_MPU_XM_ACCESS1:
258 case CS35L41_DSP1_MPU_YM_ACCESS1:
259 case CS35L41_DSP1_MPU_WNDW_ACCESS1:
260 case CS35L41_DSP1_MPU_XREG_ACCESS1:
261 case CS35L41_DSP1_MPU_YREG_ACCESS1:
262 case CS35L41_DSP1_MPU_XM_ACCESS2:
263 case CS35L41_DSP1_MPU_YM_ACCESS2:
264 case CS35L41_DSP1_MPU_WNDW_ACCESS2:
265 case CS35L41_DSP1_MPU_XREG_ACCESS2:
266 case CS35L41_DSP1_MPU_YREG_ACCESS2:
267 case CS35L41_DSP1_MPU_XM_ACCESS3:
268 case CS35L41_DSP1_MPU_YM_ACCESS3:
269 case CS35L41_DSP1_MPU_WNDW_ACCESS3:
270 case CS35L41_DSP1_MPU_XREG_ACCESS3:
271 case CS35L41_DSP1_MPU_YREG_ACCESS3:
272 case CS35L41_DSP1_MPU_XM_VIO_ADDR:
273 case CS35L41_DSP1_MPU_XM_VIO_STATUS:
274 case CS35L41_DSP1_MPU_YM_VIO_ADDR:
275 case CS35L41_DSP1_MPU_YM_VIO_STATUS:
276 case CS35L41_DSP1_MPU_PM_VIO_ADDR:
277 case CS35L41_DSP1_MPU_PM_VIO_STATUS:
278 case CS35L41_DSP1_MPU_LOCK_CONFIG:
279 case CS35L41_DSP1_MPU_WDT_RST_CTRL:
David Rhodes6450ef52021-09-07 17:57:18 -0500[diff] [blame]280 case CS35L41_OTP_TRIM_1:
281 case CS35L41_OTP_TRIM_2:
282 case CS35L41_OTP_TRIM_3:
283 case CS35L41_OTP_TRIM_4:
284 case CS35L41_OTP_TRIM_5:
285 case CS35L41_OTP_TRIM_6:
286 case CS35L41_OTP_TRIM_7:
287 case CS35L41_OTP_TRIM_8:
288 case CS35L41_OTP_TRIM_9:
289 case CS35L41_OTP_TRIM_10:
290 case CS35L41_OTP_TRIM_11:
291 case CS35L41_OTP_TRIM_12:
292 case CS35L41_OTP_TRIM_13:
293 case CS35L41_OTP_TRIM_14:
294 case CS35L41_OTP_TRIM_15:
295 case CS35L41_OTP_TRIM_16:
296 case CS35L41_OTP_TRIM_17:
297 case CS35L41_OTP_TRIM_18:
298 case CS35L41_OTP_TRIM_19:
299 case CS35L41_OTP_TRIM_20:
300 case CS35L41_OTP_TRIM_21:
301 case CS35L41_OTP_TRIM_22:
302 case CS35L41_OTP_TRIM_23:
303 case CS35L41_OTP_TRIM_24:
304 case CS35L41_OTP_TRIM_25:
305 case CS35L41_OTP_TRIM_26:
306 case CS35L41_OTP_TRIM_27:
307 case CS35L41_OTP_TRIM_28:
308 case CS35L41_OTP_TRIM_29:
309 case CS35L41_OTP_TRIM_30:
310 case CS35L41_OTP_TRIM_31:
311 case CS35L41_OTP_TRIM_32:
312 case CS35L41_OTP_TRIM_33:
313 case CS35L41_OTP_TRIM_34:
314 case CS35L41_OTP_TRIM_35:
315 case CS35L41_OTP_TRIM_36:
316 case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31:
David Rhodesbae9e132021-10-29 16:40:28 -0500[diff] [blame^]317 case CS35L41_DSP1_XMEM_PACK_0 ... CS35L41_DSP1_XMEM_PACK_3068:
318 case CS35L41_DSP1_XMEM_UNPACK32_0 ... CS35L41_DSP1_XMEM_UNPACK32_2046:
319 case CS35L41_DSP1_XMEM_UNPACK24_0 ... CS35L41_DSP1_XMEM_UNPACK24_4093:
320 case CS35L41_DSP1_YMEM_PACK_0 ... CS35L41_DSP1_YMEM_PACK_1532:
321 case CS35L41_DSP1_YMEM_UNPACK32_0 ... CS35L41_DSP1_YMEM_UNPACK32_1022:
322 case CS35L41_DSP1_YMEM_UNPACK24_0 ... CS35L41_DSP1_YMEM_UNPACK24_2045:
323 case CS35L41_DSP1_PMEM_0 ... CS35L41_DSP1_PMEM_5114:
David Rhodes6450ef52021-09-07 17:57:18 -0500[diff] [blame]324 /*test regs*/
325 case CS35L41_PLL_OVR:
326 case CS35L41_BST_TEST_DUTY:
327 case CS35L41_DIGPWM_IOCTRL:
328 return true;
329 default:
330 return false;
331 }
332}
333
334bool cs35l41_precious_reg(struct device *dev, unsigned int reg)
335{
336 switch (reg) {
337 case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31:
David Rhodesbae9e132021-10-29 16:40:28 -0500[diff] [blame^]338 case CS35L41_DSP1_XMEM_PACK_0 ... CS35L41_DSP1_XMEM_PACK_3068:
339 case CS35L41_DSP1_YMEM_PACK_0 ... CS35L41_DSP1_YMEM_PACK_1532:
340 case CS35L41_DSP1_PMEM_0 ... CS35L41_DSP1_PMEM_5114:
David Rhodes6450ef52021-09-07 17:57:18 -0500[diff] [blame]341 return true;
342 default:
343 return false;
344 }
345}
346
347bool cs35l41_volatile_reg(struct device *dev, unsigned int reg)
348{
349 switch (reg) {
350 case CS35L41_DEVID:
351 case CS35L41_SFT_RESET:
352 case CS35L41_FABID:
353 case CS35L41_REVID:
354 case CS35L41_DTEMP_EN:
355 case CS35L41_IRQ1_STATUS:
356 case CS35L41_IRQ1_STATUS1:
357 case CS35L41_IRQ1_STATUS2:
358 case CS35L41_IRQ1_STATUS3:
359 case CS35L41_IRQ1_STATUS4:
360 case CS35L41_IRQ1_RAW_STATUS1:
361 case CS35L41_IRQ1_RAW_STATUS2:
362 case CS35L41_IRQ1_RAW_STATUS3:
363 case CS35L41_IRQ1_RAW_STATUS4:
364 case CS35L41_IRQ1_FRC1:
365 case CS35L41_IRQ1_FRC2:
366 case CS35L41_IRQ1_FRC3:
367 case CS35L41_IRQ1_FRC4:
368 case CS35L41_IRQ1_EDGE1:
369 case CS35L41_IRQ1_EDGE4:
370 case CS35L41_IRQ1_POL1:
371 case CS35L41_IRQ1_POL2:
372 case CS35L41_IRQ1_POL3:
373 case CS35L41_IRQ1_POL4:
374 case CS35L41_IRQ1_DB3:
375 case CS35L41_IRQ2_STATUS:
376 case CS35L41_IRQ2_STATUS1:
377 case CS35L41_IRQ2_STATUS2:
378 case CS35L41_IRQ2_STATUS3:
379 case CS35L41_IRQ2_STATUS4:
380 case CS35L41_IRQ2_RAW_STATUS1:
381 case CS35L41_IRQ2_RAW_STATUS2:
382 case CS35L41_IRQ2_RAW_STATUS3:
383 case CS35L41_IRQ2_RAW_STATUS4:
384 case CS35L41_IRQ2_FRC1:
385 case CS35L41_IRQ2_FRC2:
386 case CS35L41_IRQ2_FRC3:
387 case CS35L41_IRQ2_FRC4:
388 case CS35L41_IRQ2_EDGE1:
389 case CS35L41_IRQ2_EDGE4:
390 case CS35L41_IRQ2_POL1:
391 case CS35L41_IRQ2_POL2:
392 case CS35L41_IRQ2_POL3:
393 case CS35L41_IRQ2_POL4:
394 case CS35L41_IRQ2_DB3:
395 case CS35L41_GPIO_STATUS1:
396 case CS35L41_OTP_TRIM_1:
397 case CS35L41_OTP_TRIM_2:
398 case CS35L41_OTP_TRIM_3:
399 case CS35L41_OTP_TRIM_4:
400 case CS35L41_OTP_TRIM_5:
401 case CS35L41_OTP_TRIM_6:
402 case CS35L41_OTP_TRIM_7:
403 case CS35L41_OTP_TRIM_8:
404 case CS35L41_OTP_TRIM_9:
405 case CS35L41_OTP_TRIM_10:
406 case CS35L41_OTP_TRIM_11:
407 case CS35L41_OTP_TRIM_12:
408 case CS35L41_OTP_TRIM_13:
409 case CS35L41_OTP_TRIM_14:
410 case CS35L41_OTP_TRIM_15:
411 case CS35L41_OTP_TRIM_16:
412 case CS35L41_OTP_TRIM_17:
413 case CS35L41_OTP_TRIM_18:
414 case CS35L41_OTP_TRIM_19:
415 case CS35L41_OTP_TRIM_20:
416 case CS35L41_OTP_TRIM_21:
417 case CS35L41_OTP_TRIM_22:
418 case CS35L41_OTP_TRIM_23:
419 case CS35L41_OTP_TRIM_24:
420 case CS35L41_OTP_TRIM_25:
421 case CS35L41_OTP_TRIM_26:
422 case CS35L41_OTP_TRIM_27:
423 case CS35L41_OTP_TRIM_28:
424 case CS35L41_OTP_TRIM_29:
425 case CS35L41_OTP_TRIM_30:
426 case CS35L41_OTP_TRIM_31:
427 case CS35L41_OTP_TRIM_32:
428 case CS35L41_OTP_TRIM_33:
429 case CS35L41_OTP_TRIM_34:
430 case CS35L41_OTP_TRIM_35:
431 case CS35L41_OTP_TRIM_36:
David Rhodesbae9e132021-10-29 16:40:28 -0500[diff] [blame^]432 case CS35L41_DSP_MBOX_1 ... CS35L41_DSP_VIRT2_MBOX_8:
433 case CS35L41_DSP1_XMEM_PACK_0 ... CS35L41_DSP1_XMEM_PACK_3068:
434 case CS35L41_DSP1_XMEM_UNPACK32_0 ... CS35L41_DSP1_XMEM_UNPACK32_2046:
435 case CS35L41_DSP1_XMEM_UNPACK24_0 ... CS35L41_DSP1_XMEM_UNPACK24_4093:
436 case CS35L41_DSP1_YMEM_PACK_0 ... CS35L41_DSP1_YMEM_PACK_1532:
437 case CS35L41_DSP1_YMEM_UNPACK32_0 ... CS35L41_DSP1_YMEM_UNPACK32_1022:
438 case CS35L41_DSP1_YMEM_UNPACK24_0 ... CS35L41_DSP1_YMEM_UNPACK24_2045:
439 case CS35L41_DSP1_PMEM_0 ... CS35L41_DSP1_PMEM_5114:
440 case CS35L41_DSP1_CCM_CORE_CTRL ... CS35L41_DSP1_WDT_STATUS:
David Rhodes6450ef52021-09-07 17:57:18 -0500[diff] [blame]441 case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31:
442 return true;
443 default:
444 return false;
445 }
446}
447
Charles Keepax4295c8c2021-09-14 15:13:49 +0100[diff] [blame]448static const struct cs35l41_otp_packed_element_t otp_map_1[CS35L41_NUM_OTP_ELEM] = {
David Rhodes6450ef52021-09-07 17:57:18 -0500[diff] [blame]449 /* addr shift size */
Charles Keepax4295c8c2021-09-14 15:13:49 +0100[diff] [blame]450 { 0x00002030, 0, 4 }, /*TRIM_OSC_FREQ_TRIM*/
451 { 0x00002030, 7, 1 }, /*TRIM_OSC_TRIM_DONE*/
452 { 0x0000208c, 24, 6 }, /*TST_DIGREG_VREF_TRIM*/
453 { 0x00002090, 14, 4 }, /*TST_REF_TRIM*/
454 { 0x00002090, 10, 4 }, /*TST_REF_TEMPCO_TRIM*/
455 { 0x0000300C, 11, 4 }, /*PLL_LDOA_TST_VREF_TRIM*/
456 { 0x0000394C, 23, 2 }, /*BST_ATEST_CM_VOFF*/
457 { 0x00003950, 0, 7 }, /*BST_ATRIM_IADC_OFFSET*/
458 { 0x00003950, 8, 7 }, /*BST_ATRIM_IADC_GAIN1*/
459 { 0x00003950, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET1*/
460 { 0x00003950, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN1*/
461 { 0x00003954, 0, 7 }, /*BST_ATRIM_IADC_OFFSET2*/
462 { 0x00003954, 8, 7 }, /*BST_ATRIM_IADC_GAIN2*/
463 { 0x00003954, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET2*/
464 { 0x00003954, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN2*/
465 { 0x00003958, 0, 7 }, /*BST_ATRIM_IADC_OFFSET3*/
466 { 0x00003958, 8, 7 }, /*BST_ATRIM_IADC_GAIN3*/
467 { 0x00003958, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET3*/
468 { 0x00003958, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN3*/
469 { 0x0000395C, 0, 7 }, /*BST_ATRIM_IADC_OFFSET4*/
470 { 0x0000395C, 8, 7 }, /*BST_ATRIM_IADC_GAIN4*/
471 { 0x0000395C, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET4*/
472 { 0x0000395C, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN4*/
473 { 0x0000416C, 0, 8 }, /*VMON_GAIN_OTP_VAL*/
474 { 0x00004160, 0, 7 }, /*VMON_OFFSET_OTP_VAL*/
475 { 0x0000416C, 8, 8 }, /*IMON_GAIN_OTP_VAL*/
476 { 0x00004160, 16, 10 }, /*IMON_OFFSET_OTP_VAL*/
477 { 0x0000416C, 16, 12 }, /*VMON_CM_GAIN_OTP_VAL*/
478 { 0x0000416C, 28, 1 }, /*VMON_CM_GAIN_SIGN_OTP_VAL*/
479 { 0x00004170, 0, 6 }, /*IMON_CAL_TEMPCO_OTP_VAL*/
480 { 0x00004170, 6, 1 }, /*IMON_CAL_TEMPCO_SIGN_OTP*/
481 { 0x00004170, 8, 6 }, /*IMON_CAL_TEMPCO2_OTP_VAL*/
482 { 0x00004170, 14, 1 }, /*IMON_CAL_TEMPCO2_DN_UPB_OTP_VAL*/
483 { 0x00004170, 16, 9 }, /*IMON_CAL_TEMPCO_TBASE_OTP_VAL*/
484 { 0x00004360, 0, 5 }, /*TEMP_GAIN_OTP_VAL*/
485 { 0x00004360, 6, 9 }, /*TEMP_OFFSET_OTP_VAL*/
486 { 0x00004448, 0, 8 }, /*VP_SARADC_OFFSET*/
487 { 0x00004448, 8, 8 }, /*VP_GAIN_INDEX*/
488 { 0x00004448, 16, 8 }, /*VBST_SARADC_OFFSET*/
489 { 0x00004448, 24, 8 }, /*VBST_GAIN_INDEX*/
490 { 0x0000444C, 0, 3 }, /*ANA_SELINVREF*/
491 { 0x00006E30, 0, 5 }, /*GAIN_ERR_COEFF_0*/
492 { 0x00006E30, 8, 5 }, /*GAIN_ERR_COEFF_1*/
493 { 0x00006E30, 16, 5 }, /*GAIN_ERR_COEFF_2*/
494 { 0x00006E30, 24, 5 }, /*GAIN_ERR_COEFF_3*/
495 { 0x00006E34, 0, 5 }, /*GAIN_ERR_COEFF_4*/
496 { 0x00006E34, 8, 5 }, /*GAIN_ERR_COEFF_5*/
497 { 0x00006E34, 16, 5 }, /*GAIN_ERR_COEFF_6*/
498 { 0x00006E34, 24, 5 }, /*GAIN_ERR_COEFF_7*/
499 { 0x00006E38, 0, 5 }, /*GAIN_ERR_COEFF_8*/
500 { 0x00006E38, 8, 5 }, /*GAIN_ERR_COEFF_9*/
501 { 0x00006E38, 16, 5 }, /*GAIN_ERR_COEFF_10*/
502 { 0x00006E38, 24, 5 }, /*GAIN_ERR_COEFF_11*/
503 { 0x00006E3C, 0, 5 }, /*GAIN_ERR_COEFF_12*/
504 { 0x00006E3C, 8, 5 }, /*GAIN_ERR_COEFF_13*/
505 { 0x00006E3C, 16, 5 }, /*GAIN_ERR_COEFF_14*/
506 { 0x00006E3C, 24, 5 }, /*GAIN_ERR_COEFF_15*/
507 { 0x00006E40, 0, 5 }, /*GAIN_ERR_COEFF_16*/
508 { 0x00006E40, 8, 5 }, /*GAIN_ERR_COEFF_17*/
509 { 0x00006E40, 16, 5 }, /*GAIN_ERR_COEFF_18*/
510 { 0x00006E40, 24, 5 }, /*GAIN_ERR_COEFF_19*/
511 { 0x00006E44, 0, 5 }, /*GAIN_ERR_COEFF_20*/
512 { 0x00006E48, 0, 10 }, /*VOFF_GAIN_0*/
513 { 0x00006E48, 10, 10 }, /*VOFF_GAIN_1*/
514 { 0x00006E48, 20, 10 }, /*VOFF_GAIN_2*/
515 { 0x00006E4C, 0, 10 }, /*VOFF_GAIN_3*/
516 { 0x00006E4C, 10, 10 }, /*VOFF_GAIN_4*/
517 { 0x00006E4C, 20, 10 }, /*VOFF_GAIN_5*/
518 { 0x00006E50, 0, 10 }, /*VOFF_GAIN_6*/
519 { 0x00006E50, 10, 10 }, /*VOFF_GAIN_7*/
520 { 0x00006E50, 20, 10 }, /*VOFF_GAIN_8*/
521 { 0x00006E54, 0, 10 }, /*VOFF_GAIN_9*/
522 { 0x00006E54, 10, 10 }, /*VOFF_GAIN_10*/
523 { 0x00006E54, 20, 10 }, /*VOFF_GAIN_11*/
524 { 0x00006E58, 0, 10 }, /*VOFF_GAIN_12*/
525 { 0x00006E58, 10, 10 }, /*VOFF_GAIN_13*/
526 { 0x00006E58, 20, 10 }, /*VOFF_GAIN_14*/
527 { 0x00006E5C, 0, 10 }, /*VOFF_GAIN_15*/
528 { 0x00006E5C, 10, 10 }, /*VOFF_GAIN_16*/
529 { 0x00006E5C, 20, 10 }, /*VOFF_GAIN_17*/
530 { 0x00006E60, 0, 10 }, /*VOFF_GAIN_18*/
531 { 0x00006E60, 10, 10 }, /*VOFF_GAIN_19*/
532 { 0x00006E60, 20, 10 }, /*VOFF_GAIN_20*/
533 { 0x00006E64, 0, 10 }, /*VOFF_INT1*/
534 { 0x00007418, 7, 5 }, /*DS_SPK_INT1_CAP_TRIM*/
535 { 0x0000741C, 0, 5 }, /*DS_SPK_INT2_CAP_TRIM*/
536 { 0x0000741C, 11, 4 }, /*DS_SPK_LPF_CAP_TRIM*/
537 { 0x0000741C, 19, 4 }, /*DS_SPK_QUAN_CAP_TRIM*/
538 { 0x00007434, 17, 1 }, /*FORCE_CAL*/
539 { 0x00007434, 18, 7 }, /*CAL_OVERRIDE*/
540 { 0x00007068, 0, 9 }, /*MODIX*/
541 { 0x0000410C, 7, 1 }, /*VIMON_DLY_NOT_COMB*/
542 { 0x0000400C, 0, 7 }, /*VIMON_DLY*/
543 { 0x00000000, 0, 1 }, /*extra bit*/
544 { 0x00017040, 0, 8 }, /*X_COORDINATE*/
545 { 0x00017040, 8, 8 }, /*Y_COORDINATE*/
546 { 0x00017040, 16, 8 }, /*WAFER_ID*/
547 { 0x00017040, 24, 8 }, /*DVS*/
548 { 0x00017044, 0, 24 }, /*LOT_NUMBER*/
David Rhodes6450ef52021-09-07 17:57:18 -0500[diff] [blame]549};
550
Charles Keepax4295c8c2021-09-14 15:13:49 +0100[diff] [blame]551static const struct cs35l41_otp_packed_element_t otp_map_2[CS35L41_NUM_OTP_ELEM] = {
David Rhodes6450ef52021-09-07 17:57:18 -0500[diff] [blame]552 /* addr shift size */
Charles Keepax4295c8c2021-09-14 15:13:49 +0100[diff] [blame]553 { 0x00002030, 0, 4 }, /*TRIM_OSC_FREQ_TRIM*/
554 { 0x00002030, 7, 1 }, /*TRIM_OSC_TRIM_DONE*/
555 { 0x0000208c, 24, 6 }, /*TST_DIGREG_VREF_TRIM*/
556 { 0x00002090, 14, 4 }, /*TST_REF_TRIM*/
557 { 0x00002090, 10, 4 }, /*TST_REF_TEMPCO_TRIM*/
558 { 0x0000300C, 11, 4 }, /*PLL_LDOA_TST_VREF_TRIM*/
559 { 0x0000394C, 23, 2 }, /*BST_ATEST_CM_VOFF*/
560 { 0x00003950, 0, 7 }, /*BST_ATRIM_IADC_OFFSET*/
561 { 0x00003950, 8, 7 }, /*BST_ATRIM_IADC_GAIN1*/
562 { 0x00003950, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET1*/
563 { 0x00003950, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN1*/
564 { 0x00003954, 0, 7 }, /*BST_ATRIM_IADC_OFFSET2*/
565 { 0x00003954, 8, 7 }, /*BST_ATRIM_IADC_GAIN2*/
566 { 0x00003954, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET2*/
567 { 0x00003954, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN2*/
568 { 0x00003958, 0, 7 }, /*BST_ATRIM_IADC_OFFSET3*/
569 { 0x00003958, 8, 7 }, /*BST_ATRIM_IADC_GAIN3*/
570 { 0x00003958, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET3*/
571 { 0x00003958, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN3*/
572 { 0x0000395C, 0, 7 }, /*BST_ATRIM_IADC_OFFSET4*/
573 { 0x0000395C, 8, 7 }, /*BST_ATRIM_IADC_GAIN4*/
574 { 0x0000395C, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET4*/
575 { 0x0000395C, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN4*/
576 { 0x0000416C, 0, 8 }, /*VMON_GAIN_OTP_VAL*/
577 { 0x00004160, 0, 7 }, /*VMON_OFFSET_OTP_VAL*/
578 { 0x0000416C, 8, 8 }, /*IMON_GAIN_OTP_VAL*/
579 { 0x00004160, 16, 10 }, /*IMON_OFFSET_OTP_VAL*/
580 { 0x0000416C, 16, 12 }, /*VMON_CM_GAIN_OTP_VAL*/
581 { 0x0000416C, 28, 1 }, /*VMON_CM_GAIN_SIGN_OTP_VAL*/
582 { 0x00004170, 0, 6 }, /*IMON_CAL_TEMPCO_OTP_VAL*/
583 { 0x00004170, 6, 1 }, /*IMON_CAL_TEMPCO_SIGN_OTP*/
584 { 0x00004170, 8, 6 }, /*IMON_CAL_TEMPCO2_OTP_VAL*/
585 { 0x00004170, 14, 1 }, /*IMON_CAL_TEMPCO2_DN_UPB_OTP_VAL*/
586 { 0x00004170, 16, 9 }, /*IMON_CAL_TEMPCO_TBASE_OTP_VAL*/
587 { 0x00004360, 0, 5 }, /*TEMP_GAIN_OTP_VAL*/
588 { 0x00004360, 6, 9 }, /*TEMP_OFFSET_OTP_VAL*/
589 { 0x00004448, 0, 8 }, /*VP_SARADC_OFFSET*/
590 { 0x00004448, 8, 8 }, /*VP_GAIN_INDEX*/
591 { 0x00004448, 16, 8 }, /*VBST_SARADC_OFFSET*/
592 { 0x00004448, 24, 8 }, /*VBST_GAIN_INDEX*/
593 { 0x0000444C, 0, 3 }, /*ANA_SELINVREF*/
594 { 0x00006E30, 0, 5 }, /*GAIN_ERR_COEFF_0*/
595 { 0x00006E30, 8, 5 }, /*GAIN_ERR_COEFF_1*/
596 { 0x00006E30, 16, 5 }, /*GAIN_ERR_COEFF_2*/
597 { 0x00006E30, 24, 5 }, /*GAIN_ERR_COEFF_3*/
598 { 0x00006E34, 0, 5 }, /*GAIN_ERR_COEFF_4*/
599 { 0x00006E34, 8, 5 }, /*GAIN_ERR_COEFF_5*/
600 { 0x00006E34, 16, 5 }, /*GAIN_ERR_COEFF_6*/
601 { 0x00006E34, 24, 5 }, /*GAIN_ERR_COEFF_7*/
602 { 0x00006E38, 0, 5 }, /*GAIN_ERR_COEFF_8*/
603 { 0x00006E38, 8, 5 }, /*GAIN_ERR_COEFF_9*/
604 { 0x00006E38, 16, 5 }, /*GAIN_ERR_COEFF_10*/
605 { 0x00006E38, 24, 5 }, /*GAIN_ERR_COEFF_11*/
606 { 0x00006E3C, 0, 5 }, /*GAIN_ERR_COEFF_12*/
607 { 0x00006E3C, 8, 5 }, /*GAIN_ERR_COEFF_13*/
608 { 0x00006E3C, 16, 5 }, /*GAIN_ERR_COEFF_14*/
609 { 0x00006E3C, 24, 5 }, /*GAIN_ERR_COEFF_15*/
610 { 0x00006E40, 0, 5 }, /*GAIN_ERR_COEFF_16*/
611 { 0x00006E40, 8, 5 }, /*GAIN_ERR_COEFF_17*/
612 { 0x00006E40, 16, 5 }, /*GAIN_ERR_COEFF_18*/
613 { 0x00006E40, 24, 5 }, /*GAIN_ERR_COEFF_19*/
614 { 0x00006E44, 0, 5 }, /*GAIN_ERR_COEFF_20*/
615 { 0x00006E48, 0, 10 }, /*VOFF_GAIN_0*/
616 { 0x00006E48, 10, 10 }, /*VOFF_GAIN_1*/
617 { 0x00006E48, 20, 10 }, /*VOFF_GAIN_2*/
618 { 0x00006E4C, 0, 10 }, /*VOFF_GAIN_3*/
619 { 0x00006E4C, 10, 10 }, /*VOFF_GAIN_4*/
620 { 0x00006E4C, 20, 10 }, /*VOFF_GAIN_5*/
621 { 0x00006E50, 0, 10 }, /*VOFF_GAIN_6*/
622 { 0x00006E50, 10, 10 }, /*VOFF_GAIN_7*/
623 { 0x00006E50, 20, 10 }, /*VOFF_GAIN_8*/
624 { 0x00006E54, 0, 10 }, /*VOFF_GAIN_9*/
625 { 0x00006E54, 10, 10 }, /*VOFF_GAIN_10*/
626 { 0x00006E54, 20, 10 }, /*VOFF_GAIN_11*/
627 { 0x00006E58, 0, 10 }, /*VOFF_GAIN_12*/
628 { 0x00006E58, 10, 10 }, /*VOFF_GAIN_13*/
629 { 0x00006E58, 20, 10 }, /*VOFF_GAIN_14*/
630 { 0x00006E5C, 0, 10 }, /*VOFF_GAIN_15*/
631 { 0x00006E5C, 10, 10 }, /*VOFF_GAIN_16*/
632 { 0x00006E5C, 20, 10 }, /*VOFF_GAIN_17*/
633 { 0x00006E60, 0, 10 }, /*VOFF_GAIN_18*/
634 { 0x00006E60, 10, 10 }, /*VOFF_GAIN_19*/
635 { 0x00006E60, 20, 10 }, /*VOFF_GAIN_20*/
636 { 0x00006E64, 0, 10 }, /*VOFF_INT1*/
637 { 0x00007418, 7, 5 }, /*DS_SPK_INT1_CAP_TRIM*/
638 { 0x0000741C, 0, 5 }, /*DS_SPK_INT2_CAP_TRIM*/
639 { 0x0000741C, 11, 4 }, /*DS_SPK_LPF_CAP_TRIM*/
640 { 0x0000741C, 19, 4 }, /*DS_SPK_QUAN_CAP_TRIM*/
641 { 0x00007434, 17, 1 }, /*FORCE_CAL*/
642 { 0x00007434, 18, 7 }, /*CAL_OVERRIDE*/
643 { 0x00007068, 0, 9 }, /*MODIX*/
644 { 0x0000410C, 7, 1 }, /*VIMON_DLY_NOT_COMB*/
645 { 0x0000400C, 0, 7 }, /*VIMON_DLY*/
646 { 0x00004000, 11, 1 }, /*VMON_POL*/
647 { 0x00017040, 0, 8 }, /*X_COORDINATE*/
648 { 0x00017040, 8, 8 }, /*Y_COORDINATE*/
649 { 0x00017040, 16, 8 }, /*WAFER_ID*/
650 { 0x00017040, 24, 8 }, /*DVS*/
651 { 0x00017044, 0, 24 }, /*LOT_NUMBER*/
David Rhodes6450ef52021-09-07 17:57:18 -0500[diff] [blame]652};
653
Charles Keepax4295c8c2021-09-14 15:13:49 +0100[diff] [blame]654const struct cs35l41_otp_map_element_t cs35l41_otp_map_map[CS35L41_NUM_OTP_MAPS] = {
David Rhodes6450ef52021-09-07 17:57:18 -0500[diff] [blame]655 {
656 .id = 0x01,
657 .map = otp_map_1,
658 .num_elements = CS35L41_NUM_OTP_ELEM,
659 .bit_offset = 16,
660 .word_offset = 2,
661 },
662 {
663 .id = 0x02,
664 .map = otp_map_2,
665 .num_elements = CS35L41_NUM_OTP_ELEM,
666 .bit_offset = 16,
667 .word_offset = 2,
668 },
669 {
670 .id = 0x03,
671 .map = otp_map_2,
672 .num_elements = CS35L41_NUM_OTP_ELEM,
673 .bit_offset = 16,
674 .word_offset = 2,
675 },
676 {
677 .id = 0x06,
678 .map = otp_map_2,
679 .num_elements = CS35L41_NUM_OTP_ELEM,
680 .bit_offset = 16,
681 .word_offset = 2,
682 },
683 {
684 .id = 0x08,
685 .map = otp_map_1,
686 .num_elements = CS35L41_NUM_OTP_ELEM,
687 .bit_offset = 16,
688 .word_offset = 2,
689 },
690};