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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / b9c665d75beb9239f8a0847786cf27dcb8a61b00 / . / arch / arm / boot / dts / tegra30-cardhu.dtsi
blob: b1271a894327912f0a4d15f3b6fb189865dad6ea [file] [log] [blame]
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]1/include/ "tegra30.dtsi"
2
Laxman Dewangan640a7af2012-08-09 16:30:38 +0530[diff] [blame]3/**
4 * This file contains common DT entry for all fab version of Cardhu.
5 * There is multiple fab version of Cardhu starting from A01 to A07.
6 * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
7 * A02 will have different sets of GPIOs for fixed regulator compare to
8 * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
9 * compatible with fab version A04. Based on Cardhu fab version, the
10 * related dts file need to be chosen like for Cardhu fab version A02,
11 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
12 * tegra30-cardhu-a04.dts.
13 * The identification of board is done in two ways, by looking the sticker
14 * on PCB and by reading board id eeprom.
15 * The stciker will have number like 600-81291-1000-002 C.3. In this 4th
16 * number is the fab version like here it is 002 and hence fab version A02.
17 * The (downstream internal) U-Boot of Cardhu display the board-id as
18 * follows:
19 * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
20 * In this Fab version is 02 i.e. A02.
21 * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
22 * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
23 * wide.
24 */
25
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]26/ {
27 model = "NVIDIA Tegra30 Cardhu evaluation board";
28 compatible = "nvidia,cardhu", "nvidia,tegra30";
29
30 memory {
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]31 reg = <0x80000000 0x40000000>;
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]32 };
33
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]34 pinmux {
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]35 pinctrl-names = "default";
36 pinctrl-0 = <&state_default>;
37
38 state_default: pinmux {
39 sdmmc1_clk_pz0 {
40 nvidia,pins = "sdmmc1_clk_pz0";
41 nvidia,function = "sdmmc1";
42 nvidia,pull = <0>;
43 nvidia,tristate = <0>;
44 };
45 sdmmc1_cmd_pz1 {
46 nvidia,pins = "sdmmc1_cmd_pz1",
47 "sdmmc1_dat0_py7",
48 "sdmmc1_dat1_py6",
49 "sdmmc1_dat2_py5",
50 "sdmmc1_dat3_py4";
51 nvidia,function = "sdmmc1";
52 nvidia,pull = <2>;
53 nvidia,tristate = <0>;
54 };
55 sdmmc4_clk_pcc4 {
56 nvidia,pins = "sdmmc4_clk_pcc4",
57 "sdmmc4_rst_n_pcc3";
58 nvidia,function = "sdmmc4";
59 nvidia,pull = <0>;
60 nvidia,tristate = <0>;
61 };
62 sdmmc4_dat0_paa0 {
63 nvidia,pins = "sdmmc4_dat0_paa0",
64 "sdmmc4_dat1_paa1",
65 "sdmmc4_dat2_paa2",
66 "sdmmc4_dat3_paa3",
67 "sdmmc4_dat4_paa4",
68 "sdmmc4_dat5_paa5",
69 "sdmmc4_dat6_paa6",
70 "sdmmc4_dat7_paa7";
71 nvidia,function = "sdmmc4";
72 nvidia,pull = <2>;
73 nvidia,tristate = <0>;
74 };
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]75 dap2_fs_pa2 {
76 nvidia,pins = "dap2_fs_pa2",
77 "dap2_sclk_pa3",
78 "dap2_din_pa4",
79 "dap2_dout_pa5";
80 nvidia,function = "i2s1";
81 nvidia,pull = <0>;
82 nvidia,tristate = <0>;
83 };
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]84 };
85 };
86
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]87 serial@70006000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]88 status = "okay";
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]89 clock-frequency = <408000000>;
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]90 };
91
92 i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]93 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]94 clock-frequency = <100000>;
95 };
96
97 i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]98 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]99 clock-frequency = <100000>;
100 };
101
102 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]103 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]104 clock-frequency = <100000>;
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530[diff] [blame]105
106 /* ALS and Proximity sensor */
107 isl29028@44 {
108 compatible = "isil,isl29028";
109 reg = <0x44>;
110 interrupt-parent = <&gpio>;
111 interrupts = <88 0x04>; /*gpio PL0 */
112 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]113 };
114
115 i2c@7000c700 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]116 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]117 clock-frequency = <100000>;
118 };
119
120 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]121 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]122 clock-frequency = <100000>;
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]123
124 wm8903: wm8903@1a {
125 compatible = "wlf,wm8903";
126 reg = <0x1a>;
127 interrupt-parent = <&gpio>;
128 interrupts = <179 0x04>; /* gpio PW3 */
129
130 gpio-controller;
131 #gpio-cells = <2>;
132
133 micdet-cfg = <0>;
134 micdet-delay = <100>;
135 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
136 };
Laxman Dewangan331da582012-05-10 20:38:45 +0000[diff] [blame]137
138 tps62361 {
139 compatible = "ti,tps62361";
140 reg = <0x60>;
141
142 regulator-name = "tps62361-vout";
143 regulator-min-microvolt = <500000>;
144 regulator-max-microvolt = <1500000>;
145 regulator-boot-on;
146 regulator-always-on;
147 ti,vsel0-state-high;
148 ti,vsel1-state-high;
149 };
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]150
151 pmic: tps65911@2d {
152 compatible = "ti,tps65911";
153 reg = <0x2d>;
154
155 interrupts = <0 86 0x4>;
156 #interrupt-cells = <2>;
157 interrupt-controller;
158
Stephen Warren44b12ef2012-09-11 11:42:26 -0600[diff] [blame]159 ti,system-power-controller;
160
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]161 #gpio-cells = <2>;
162 gpio-controller;
163
164 vcc1-supply = <&vdd_ac_bat_reg>;
165 vcc2-supply = <&vdd_ac_bat_reg>;
166 vcc3-supply = <&vio_reg>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]167 vcc4-supply = <&vdd_5v0_reg>;
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]168 vcc5-supply = <&vdd_ac_bat_reg>;
169 vcc6-supply = <&vdd2_reg>;
170 vcc7-supply = <&vdd_ac_bat_reg>;
171 vccio-supply = <&vdd_ac_bat_reg>;
172
173 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame^]174 vdd1_reg: vdd1 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]175 regulator-name = "vddio_ddr_1v2";
176 regulator-min-microvolt = <1200000>;
177 regulator-max-microvolt = <1200000>;
178 regulator-always-on;
179 };
180
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame^]181 vdd2_reg: vdd2 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]182 regulator-name = "vdd_1v5_gen";
183 regulator-min-microvolt = <1500000>;
184 regulator-max-microvolt = <1500000>;
185 regulator-always-on;
186 };
187
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame^]188 vddctrl_reg: vddctrl {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]189 regulator-name = "vdd_cpu,vdd_sys";
190 regulator-min-microvolt = <1000000>;
191 regulator-max-microvolt = <1000000>;
192 regulator-always-on;
193 };
194
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame^]195 vio_reg: vio {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]196 regulator-name = "vdd_1v8_gen";
197 regulator-min-microvolt = <1800000>;
198 regulator-max-microvolt = <1800000>;
199 regulator-always-on;
200 };
201
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame^]202 ldo1_reg: ldo1 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]203 regulator-name = "vdd_pexa,vdd_pexb";
204 regulator-min-microvolt = <1050000>;
205 regulator-max-microvolt = <1050000>;
206 };
207
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame^]208 ldo2_reg: ldo2 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]209 regulator-name = "vdd_sata,avdd_plle";
210 regulator-min-microvolt = <1050000>;
211 regulator-max-microvolt = <1050000>;
212 };
213
214 /* LDO3 is not connected to anything */
215
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame^]216 ldo4_reg: ldo4 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]217 regulator-name = "vdd_rtc";
218 regulator-min-microvolt = <1200000>;
219 regulator-max-microvolt = <1200000>;
220 regulator-always-on;
221 };
222
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame^]223 ldo5_reg: ldo5 {
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]224 regulator-name = "vddio_sdmmc,avdd_vdac";
225 regulator-min-microvolt = <3300000>;
226 regulator-max-microvolt = <3300000>;
227 regulator-always-on;
228 };
229
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame^]230 ldo6_reg: ldo6 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]231 regulator-name = "avdd_dsi_csi,pwrdet_mipi";
232 regulator-min-microvolt = <1200000>;
233 regulator-max-microvolt = <1200000>;
234 };
235
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame^]236 ldo7_reg: ldo7 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]237 regulator-name = "vdd_pllm,x,u,a_p_c_s";
238 regulator-min-microvolt = <1200000>;
239 regulator-max-microvolt = <1200000>;
240 regulator-always-on;
241 };
242
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame^]243 ldo8_reg: ldo8 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]244 regulator-name = "vdd_ddr_hs";
245 regulator-min-microvolt = <1000000>;
246 regulator-max-microvolt = <1000000>;
247 regulator-always-on;
248 };
249 };
250 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]251 };
Stephen Warren850c4c82012-02-01 16:29:57 -0700[diff] [blame]252
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]253 ahub {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]254 i2s@70080400 {
255 status = "okay";
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]256 };
257 };
258
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]259 pmc {
260 status = "okay";
261 nvidia,invert-interrupt;
262 };
263
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]264 sdhci@78000000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]265 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]266 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
267 wp-gpios = <&gpio 155 0>; /* gpio PT3 */
268 power-gpios = <&gpio 31 0>; /* gpio PD7 */
Arnd Bergmann7f217792012-05-13 00:14:24 -0400[diff] [blame]269 bus-width = <4>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]270 };
271
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]272 sdhci@78000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]273 status = "okay";
Arnd Bergmann7f217792012-05-13 00:14:24 -0400[diff] [blame]274 bus-width = <8>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]275 };
276
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]277 regulators {
278 compatible = "simple-bus";
279 #address-cells = <1>;
280 #size-cells = <0>;
281
282 vdd_ac_bat_reg: regulator@0 {
283 compatible = "regulator-fixed";
284 reg = <0>;
285 regulator-name = "vdd_ac_bat";
286 regulator-min-microvolt = <5000000>;
287 regulator-max-microvolt = <5000000>;
288 regulator-always-on;
289 };
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]290
291 cam_1v8_reg: regulator@1 {
292 compatible = "regulator-fixed";
293 reg = <1>;
294 regulator-name = "cam_1v8";
295 regulator-min-microvolt = <1800000>;
296 regulator-max-microvolt = <1800000>;
297 enable-active-high;
298 gpio = <&gpio 220 0>; /* gpio PBB4 */
299 vin-supply = <&vio_reg>;
300 };
301
302 cp_5v_reg: regulator@2 {
303 compatible = "regulator-fixed";
304 reg = <2>;
305 regulator-name = "cp_5v";
306 regulator-min-microvolt = <5000000>;
307 regulator-max-microvolt = <5000000>;
308 regulator-boot-on;
309 regulator-always-on;
310 enable-active-high;
311 gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
312 };
313
314 emmc_3v3_reg: regulator@3 {
315 compatible = "regulator-fixed";
316 reg = <3>;
317 regulator-name = "emmc_3v3";
318 regulator-min-microvolt = <3300000>;
319 regulator-max-microvolt = <3300000>;
320 regulator-always-on;
321 regulator-boot-on;
322 enable-active-high;
323 gpio = <&gpio 25 0>; /* gpio PD1 */
324 vin-supply = <&sys_3v3_reg>;
325 };
326
327 modem_3v3_reg: regulator@4 {
328 compatible = "regulator-fixed";
329 reg = <4>;
330 regulator-name = "modem_3v3";
331 regulator-min-microvolt = <3300000>;
332 regulator-max-microvolt = <3300000>;
333 enable-active-high;
334 gpio = <&gpio 30 0>; /* gpio PD6 */
335 };
336
337 pex_hvdd_3v3_reg: regulator@5 {
338 compatible = "regulator-fixed";
339 reg = <5>;
340 regulator-name = "pex_hvdd_3v3";
341 regulator-min-microvolt = <3300000>;
342 regulator-max-microvolt = <3300000>;
343 enable-active-high;
344 gpio = <&gpio 95 0>; /* gpio PL7 */
345 vin-supply = <&sys_3v3_reg>;
346 };
347
348 vdd_cam1_ldo_reg: regulator@6 {
349 compatible = "regulator-fixed";
350 reg = <6>;
351 regulator-name = "vdd_cam1_ldo";
352 regulator-min-microvolt = <2800000>;
353 regulator-max-microvolt = <2800000>;
354 enable-active-high;
355 gpio = <&gpio 142 0>; /* gpio PR6 */
356 vin-supply = <&sys_3v3_reg>;
357 };
358
359 vdd_cam2_ldo_reg: regulator@7 {
360 compatible = "regulator-fixed";
361 reg = <7>;
362 regulator-name = "vdd_cam2_ldo";
363 regulator-min-microvolt = <2800000>;
364 regulator-max-microvolt = <2800000>;
365 enable-active-high;
366 gpio = <&gpio 143 0>; /* gpio PR7 */
367 vin-supply = <&sys_3v3_reg>;
368 };
369
370 vdd_cam3_ldo_reg: regulator@8 {
371 compatible = "regulator-fixed";
372 reg = <8>;
373 regulator-name = "vdd_cam3_ldo";
374 regulator-min-microvolt = <3300000>;
375 regulator-max-microvolt = <3300000>;
376 enable-active-high;
377 gpio = <&gpio 144 0>; /* gpio PS0 */
378 vin-supply = <&sys_3v3_reg>;
379 };
380
381 vdd_com_reg: regulator@9 {
382 compatible = "regulator-fixed";
383 reg = <9>;
384 regulator-name = "vdd_com";
385 regulator-min-microvolt = <3300000>;
386 regulator-max-microvolt = <3300000>;
387 enable-active-high;
388 gpio = <&gpio 24 0>; /* gpio PD0 */
389 vin-supply = <&sys_3v3_reg>;
390 };
391
392 vdd_fuse_3v3_reg: regulator@10 {
393 compatible = "regulator-fixed";
394 reg = <10>;
395 regulator-name = "vdd_fuse_3v3";
396 regulator-min-microvolt = <3300000>;
397 regulator-max-microvolt = <3300000>;
398 enable-active-high;
399 gpio = <&gpio 94 0>; /* gpio PL6 */
400 vin-supply = <&sys_3v3_reg>;
401 };
402
403 vdd_pnl1_reg: regulator@11 {
404 compatible = "regulator-fixed";
405 reg = <11>;
406 regulator-name = "vdd_pnl1";
407 regulator-min-microvolt = <3300000>;
408 regulator-max-microvolt = <3300000>;
409 regulator-always-on;
410 regulator-boot-on;
411 enable-active-high;
412 gpio = <&gpio 92 0>; /* gpio PL4 */
413 vin-supply = <&sys_3v3_reg>;
414 };
415
416 vdd_vid_reg: regulator@12 {
417 compatible = "regulator-fixed";
418 reg = <12>;
419 regulator-name = "vddio_vid";
420 regulator-min-microvolt = <5000000>;
421 regulator-max-microvolt = <5000000>;
422 enable-active-high;
423 gpio = <&gpio 152 0>; /* GPIO PT0 */
424 gpio-open-drain;
425 vin-supply = <&vdd_5v0_reg>;
426 };
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]427 };
428
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]429 sound {
430 compatible = "nvidia,tegra-audio-wm8903-cardhu",
431 "nvidia,tegra-audio-wm8903";
432 nvidia,model = "NVIDIA Tegra Cardhu";
433
434 nvidia,audio-routing =
435 "Headphone Jack", "HPOUTR",
436 "Headphone Jack", "HPOUTL",
437 "Int Spk", "ROP",
438 "Int Spk", "RON",
439 "Int Spk", "LOP",
440 "Int Spk", "LON",
441 "Mic Jack", "MICBIAS",
442 "IN1L", "Mic Jack";
443
444 nvidia,i2s-controller = <&tegra_i2s1>;
445 nvidia,audio-codec = <&wm8903>;
446
447 nvidia,spkr-en-gpios = <&wm8903 2 0>;
448 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
449 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]450};