blob: a9cb089923be11b7b5f743a1fc772967418c2174 [file] [log] [blame]
Roland Stigge2944a442012-06-07 12:22:15 +02001/*
2 * NXP LPC32XX NAND SLC driver
3 *
4 * Authors:
5 * Kevin Wells <kevin.wells@nxp.com>
6 * Roland Stigge <stigge@antcom.de>
7 *
8 * Copyright © 2011 NXP Semiconductors
9 * Copyright © 2012 Roland Stigge
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 */
21
22#include <linux/slab.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
25#include <linux/mtd/mtd.h>
Boris Brezillond4092d72017-08-04 17:29:10 +020026#include <linux/mtd/rawnand.h>
Roland Stigge2944a442012-06-07 12:22:15 +020027#include <linux/mtd/partitions.h>
28#include <linux/clk.h>
29#include <linux/err.h>
30#include <linux/delay.h>
31#include <linux/io.h>
32#include <linux/mm.h>
33#include <linux/dma-mapping.h>
34#include <linux/dmaengine.h>
35#include <linux/mtd/nand_ecc.h>
36#include <linux/gpio.h>
37#include <linux/of.h>
Roland Stigge2944a442012-06-07 12:22:15 +020038#include <linux/of_gpio.h>
Roland Stiggede20c222012-08-16 15:15:34 +020039#include <linux/mtd/lpc32xx_slc.h>
Roland Stigge2944a442012-06-07 12:22:15 +020040
41#define LPC32XX_MODNAME "lpc32xx-nand"
42
43/**********************************************************************
44* SLC NAND controller register offsets
45**********************************************************************/
46
47#define SLC_DATA(x) (x + 0x000)
48#define SLC_ADDR(x) (x + 0x004)
49#define SLC_CMD(x) (x + 0x008)
50#define SLC_STOP(x) (x + 0x00C)
51#define SLC_CTRL(x) (x + 0x010)
52#define SLC_CFG(x) (x + 0x014)
53#define SLC_STAT(x) (x + 0x018)
54#define SLC_INT_STAT(x) (x + 0x01C)
55#define SLC_IEN(x) (x + 0x020)
56#define SLC_ISR(x) (x + 0x024)
57#define SLC_ICR(x) (x + 0x028)
58#define SLC_TAC(x) (x + 0x02C)
59#define SLC_TC(x) (x + 0x030)
60#define SLC_ECC(x) (x + 0x034)
61#define SLC_DMA_DATA(x) (x + 0x038)
62
63/**********************************************************************
64* slc_ctrl register definitions
65**********************************************************************/
66#define SLCCTRL_SW_RESET (1 << 2) /* Reset the NAND controller bit */
67#define SLCCTRL_ECC_CLEAR (1 << 1) /* Reset ECC bit */
68#define SLCCTRL_DMA_START (1 << 0) /* Start DMA channel bit */
69
70/**********************************************************************
71* slc_cfg register definitions
72**********************************************************************/
73#define SLCCFG_CE_LOW (1 << 5) /* Force CE low bit */
74#define SLCCFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */
75#define SLCCFG_ECC_EN (1 << 3) /* ECC enable bit */
76#define SLCCFG_DMA_BURST (1 << 2) /* DMA burst bit */
77#define SLCCFG_DMA_DIR (1 << 1) /* DMA write(0)/read(1) bit */
78#define SLCCFG_WIDTH (1 << 0) /* External device width, 0=8bit */
79
80/**********************************************************************
81* slc_stat register definitions
82**********************************************************************/
83#define SLCSTAT_DMA_FIFO (1 << 2) /* DMA FIFO has data bit */
84#define SLCSTAT_SLC_FIFO (1 << 1) /* SLC FIFO has data bit */
85#define SLCSTAT_NAND_READY (1 << 0) /* NAND device is ready bit */
86
87/**********************************************************************
88* slc_int_stat, slc_ien, slc_isr, and slc_icr register definitions
89**********************************************************************/
90#define SLCSTAT_INT_TC (1 << 1) /* Transfer count bit */
91#define SLCSTAT_INT_RDY_EN (1 << 0) /* Ready interrupt bit */
92
93/**********************************************************************
94* slc_tac register definitions
95**********************************************************************/
Vladimir Zapolskiy641f6342015-10-01 02:23:35 +030096/* Computation of clock cycles on basis of controller and device clock rates */
Vladimir Zapolskiyd54e8802015-10-01 02:23:37 +030097#define SLCTAC_CLOCKS(c, n, s) (min_t(u32, DIV_ROUND_UP(c, n) - 1, 0xF) << s)
Vladimir Zapolskiy641f6342015-10-01 02:23:35 +030098
Roland Stigge2944a442012-06-07 12:22:15 +020099/* Clock setting for RDY write sample wait time in 2*n clocks */
100#define SLCTAC_WDR(n) (((n) & 0xF) << 28)
101/* Write pulse width in clock cycles, 1 to 16 clocks */
Vladimir Zapolskiy641f6342015-10-01 02:23:35 +0300102#define SLCTAC_WWIDTH(c, n) (SLCTAC_CLOCKS(c, n, 24))
Roland Stigge2944a442012-06-07 12:22:15 +0200103/* Write hold time of control and data signals, 1 to 16 clocks */
Vladimir Zapolskiy641f6342015-10-01 02:23:35 +0300104#define SLCTAC_WHOLD(c, n) (SLCTAC_CLOCKS(c, n, 20))
Roland Stigge2944a442012-06-07 12:22:15 +0200105/* Write setup time of control and data signals, 1 to 16 clocks */
Vladimir Zapolskiy641f6342015-10-01 02:23:35 +0300106#define SLCTAC_WSETUP(c, n) (SLCTAC_CLOCKS(c, n, 16))
Roland Stigge2944a442012-06-07 12:22:15 +0200107/* Clock setting for RDY read sample wait time in 2*n clocks */
108#define SLCTAC_RDR(n) (((n) & 0xF) << 12)
109/* Read pulse width in clock cycles, 1 to 16 clocks */
Vladimir Zapolskiy641f6342015-10-01 02:23:35 +0300110#define SLCTAC_RWIDTH(c, n) (SLCTAC_CLOCKS(c, n, 8))
Roland Stigge2944a442012-06-07 12:22:15 +0200111/* Read hold time of control and data signals, 1 to 16 clocks */
Vladimir Zapolskiy641f6342015-10-01 02:23:35 +0300112#define SLCTAC_RHOLD(c, n) (SLCTAC_CLOCKS(c, n, 4))
Roland Stigge2944a442012-06-07 12:22:15 +0200113/* Read setup time of control and data signals, 1 to 16 clocks */
Vladimir Zapolskiy641f6342015-10-01 02:23:35 +0300114#define SLCTAC_RSETUP(c, n) (SLCTAC_CLOCKS(c, n, 0))
Roland Stigge2944a442012-06-07 12:22:15 +0200115
116/**********************************************************************
117* slc_ecc register definitions
118**********************************************************************/
119/* ECC line party fetch macro */
120#define SLCECC_TO_LINEPAR(n) (((n) >> 6) & 0x7FFF)
121#define SLCECC_TO_COLPAR(n) ((n) & 0x3F)
122
123/*
124 * DMA requires storage space for the DMA local buffer and the hardware ECC
125 * storage area. The DMA local buffer is only used if DMA mapping fails
126 * during runtime.
127 */
128#define LPC32XX_DMA_DATA_SIZE 4096
129#define LPC32XX_ECC_SAVE_SIZE ((4096 / 256) * 4)
130
131/* Number of bytes used for ECC stored in NAND per 256 bytes */
132#define LPC32XX_SLC_DEV_ECC_BYTES 3
133
134/*
135 * If the NAND base clock frequency can't be fetched, this frequency will be
136 * used instead as the base. This rate is used to setup the timing registers
137 * used for NAND accesses.
138 */
139#define LPC32XX_DEF_BUS_RATE 133250000
140
141/* Milliseconds for DMA FIFO timeout (unlikely anyway) */
142#define LPC32XX_DMA_TIMEOUT 100
143
144/*
145 * NAND ECC Layout for small page NAND devices
146 * Note: For large and huge page devices, the default layouts are used
147 */
Boris Brezillond50b5232016-02-03 20:02:41 +0100148static int lpc32xx_ooblayout_ecc(struct mtd_info *mtd, int section,
149 struct mtd_oob_region *oobregion)
150{
151 if (section)
152 return -ERANGE;
153
154 oobregion->length = 6;
155 oobregion->offset = 10;
156
157 return 0;
158}
159
160static int lpc32xx_ooblayout_free(struct mtd_info *mtd, int section,
161 struct mtd_oob_region *oobregion)
162{
163 if (section > 1)
164 return -ERANGE;
165
166 if (!section) {
167 oobregion->offset = 0;
168 oobregion->length = 4;
169 } else {
170 oobregion->offset = 6;
171 oobregion->length = 4;
172 }
173
174 return 0;
175}
176
177static const struct mtd_ooblayout_ops lpc32xx_ooblayout_ops = {
178 .ecc = lpc32xx_ooblayout_ecc,
179 .free = lpc32xx_ooblayout_free,
Roland Stigge2944a442012-06-07 12:22:15 +0200180};
181
182static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
183static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
184
185/*
186 * Small page FLASH BBT descriptors, marker at offset 0, version at offset 6
187 * Note: Large page devices used the default layout
188 */
189static struct nand_bbt_descr bbt_smallpage_main_descr = {
190 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
191 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
192 .offs = 0,
193 .len = 4,
194 .veroffs = 6,
195 .maxblocks = 4,
196 .pattern = bbt_pattern
197};
198
199static struct nand_bbt_descr bbt_smallpage_mirror_descr = {
200 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
201 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
202 .offs = 0,
203 .len = 4,
204 .veroffs = 6,
205 .maxblocks = 4,
206 .pattern = mirror_pattern
207};
208
209/*
210 * NAND platform configuration structure
211 */
212struct lpc32xx_nand_cfg_slc {
213 uint32_t wdr_clks;
214 uint32_t wwidth;
215 uint32_t whold;
216 uint32_t wsetup;
217 uint32_t rdr_clks;
218 uint32_t rwidth;
219 uint32_t rhold;
220 uint32_t rsetup;
Alexandre Pereira da Silvadf63fe72012-06-27 17:51:13 +0200221 int wp_gpio;
Roland Stigge2944a442012-06-07 12:22:15 +0200222 struct mtd_partition *parts;
223 unsigned num_parts;
224};
225
226struct lpc32xx_nand_host {
227 struct nand_chip nand_chip;
Roland Stiggede20c222012-08-16 15:15:34 +0200228 struct lpc32xx_slc_platform_data *pdata;
Roland Stigge2944a442012-06-07 12:22:15 +0200229 struct clk *clk;
Roland Stigge2944a442012-06-07 12:22:15 +0200230 void __iomem *io_base;
231 struct lpc32xx_nand_cfg_slc *ncfg;
232
233 struct completion comp;
234 struct dma_chan *dma_chan;
235 uint32_t dma_buf_len;
236 struct dma_slave_config dma_slave_config;
237 struct scatterlist sgl;
238
239 /*
240 * DMA and CPU addresses of ECC work area and data buffer
241 */
242 uint32_t *ecc_buf;
243 uint8_t *data_buf;
244 dma_addr_t io_base_dma;
245};
246
247static void lpc32xx_nand_setup(struct lpc32xx_nand_host *host)
248{
249 uint32_t clkrate, tmp;
250
251 /* Reset SLC controller */
252 writel(SLCCTRL_SW_RESET, SLC_CTRL(host->io_base));
253 udelay(1000);
254
255 /* Basic setup */
256 writel(0, SLC_CFG(host->io_base));
257 writel(0, SLC_IEN(host->io_base));
258 writel((SLCSTAT_INT_TC | SLCSTAT_INT_RDY_EN),
259 SLC_ICR(host->io_base));
260
261 /* Get base clock for SLC block */
262 clkrate = clk_get_rate(host->clk);
263 if (clkrate == 0)
264 clkrate = LPC32XX_DEF_BUS_RATE;
265
266 /* Compute clock setup values */
267 tmp = SLCTAC_WDR(host->ncfg->wdr_clks) |
Vladimir Zapolskiy641f6342015-10-01 02:23:35 +0300268 SLCTAC_WWIDTH(clkrate, host->ncfg->wwidth) |
269 SLCTAC_WHOLD(clkrate, host->ncfg->whold) |
270 SLCTAC_WSETUP(clkrate, host->ncfg->wsetup) |
Roland Stigge2944a442012-06-07 12:22:15 +0200271 SLCTAC_RDR(host->ncfg->rdr_clks) |
Vladimir Zapolskiy641f6342015-10-01 02:23:35 +0300272 SLCTAC_RWIDTH(clkrate, host->ncfg->rwidth) |
273 SLCTAC_RHOLD(clkrate, host->ncfg->rhold) |
274 SLCTAC_RSETUP(clkrate, host->ncfg->rsetup);
Roland Stigge2944a442012-06-07 12:22:15 +0200275 writel(tmp, SLC_TAC(host->io_base));
276}
277
278/*
279 * Hardware specific access to control lines
280 */
281static void lpc32xx_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
282 unsigned int ctrl)
283{
284 uint32_t tmp;
Boris BREZILLON4bd4ebc2015-12-01 12:03:04 +0100285 struct nand_chip *chip = mtd_to_nand(mtd);
Boris BREZILLONd699ed22015-12-10 09:00:41 +0100286 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
Roland Stigge2944a442012-06-07 12:22:15 +0200287
288 /* Does CE state need to be changed? */
289 tmp = readl(SLC_CFG(host->io_base));
290 if (ctrl & NAND_NCE)
291 tmp |= SLCCFG_CE_LOW;
292 else
293 tmp &= ~SLCCFG_CE_LOW;
294 writel(tmp, SLC_CFG(host->io_base));
295
296 if (cmd != NAND_CMD_NONE) {
297 if (ctrl & NAND_CLE)
298 writel(cmd, SLC_CMD(host->io_base));
299 else
300 writel(cmd, SLC_ADDR(host->io_base));
301 }
302}
303
304/*
305 * Read the Device Ready pin
306 */
307static int lpc32xx_nand_device_ready(struct mtd_info *mtd)
308{
Boris BREZILLON4bd4ebc2015-12-01 12:03:04 +0100309 struct nand_chip *chip = mtd_to_nand(mtd);
Boris BREZILLONd699ed22015-12-10 09:00:41 +0100310 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
Roland Stigge2944a442012-06-07 12:22:15 +0200311 int rdy = 0;
312
313 if ((readl(SLC_STAT(host->io_base)) & SLCSTAT_NAND_READY) != 0)
314 rdy = 1;
315
316 return rdy;
317}
318
319/*
320 * Enable NAND write protect
321 */
322static void lpc32xx_wp_enable(struct lpc32xx_nand_host *host)
323{
Alexandre Pereira da Silvadf63fe72012-06-27 17:51:13 +0200324 if (gpio_is_valid(host->ncfg->wp_gpio))
325 gpio_set_value(host->ncfg->wp_gpio, 0);
Roland Stigge2944a442012-06-07 12:22:15 +0200326}
327
328/*
329 * Disable NAND write protect
330 */
331static void lpc32xx_wp_disable(struct lpc32xx_nand_host *host)
332{
Alexandre Pereira da Silvadf63fe72012-06-27 17:51:13 +0200333 if (gpio_is_valid(host->ncfg->wp_gpio))
334 gpio_set_value(host->ncfg->wp_gpio, 1);
Roland Stigge2944a442012-06-07 12:22:15 +0200335}
336
337/*
338 * Prepares SLC for transfers with H/W ECC enabled
339 */
Boris Brezillonec476362018-09-06 14:05:17 +0200340static void lpc32xx_nand_ecc_enable(struct nand_chip *chip, int mode)
Roland Stigge2944a442012-06-07 12:22:15 +0200341{
342 /* Hardware ECC is enabled automatically in hardware as needed */
343}
344
345/*
346 * Calculates the ECC for the data
347 */
Boris Brezillonaf37d2c2018-09-06 14:05:18 +0200348static int lpc32xx_nand_ecc_calculate(struct nand_chip *chip,
Roland Stigge2944a442012-06-07 12:22:15 +0200349 const unsigned char *buf,
350 unsigned char *code)
351{
352 /*
353 * ECC is calculated automatically in hardware during syndrome read
354 * and write operations, so it doesn't need to be calculated here.
355 */
356 return 0;
357}
358
359/*
360 * Read a single byte from NAND device
361 */
362static uint8_t lpc32xx_nand_read_byte(struct mtd_info *mtd)
363{
Boris BREZILLON4bd4ebc2015-12-01 12:03:04 +0100364 struct nand_chip *chip = mtd_to_nand(mtd);
Boris BREZILLONd699ed22015-12-10 09:00:41 +0100365 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
Roland Stigge2944a442012-06-07 12:22:15 +0200366
367 return (uint8_t)readl(SLC_DATA(host->io_base));
368}
369
370/*
371 * Simple device read without ECC
372 */
373static void lpc32xx_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
374{
Boris BREZILLON4bd4ebc2015-12-01 12:03:04 +0100375 struct nand_chip *chip = mtd_to_nand(mtd);
Boris BREZILLONd699ed22015-12-10 09:00:41 +0100376 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
Roland Stigge2944a442012-06-07 12:22:15 +0200377
378 /* Direct device read with no ECC */
379 while (len-- > 0)
380 *buf++ = (uint8_t)readl(SLC_DATA(host->io_base));
381}
382
383/*
384 * Simple device write without ECC
385 */
386static void lpc32xx_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
387{
Boris BREZILLON4bd4ebc2015-12-01 12:03:04 +0100388 struct nand_chip *chip = mtd_to_nand(mtd);
Boris BREZILLONd699ed22015-12-10 09:00:41 +0100389 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
Roland Stigge2944a442012-06-07 12:22:15 +0200390
391 /* Direct device write with no ECC */
392 while (len-- > 0)
393 writel((uint32_t)*buf++, SLC_DATA(host->io_base));
394}
395
396/*
Roland Stigge2944a442012-06-07 12:22:15 +0200397 * Read the OOB data from the device without ECC using FIFO method
398 */
Boris Brezillonb9761682018-09-06 14:05:20 +0200399static int lpc32xx_nand_read_oob_syndrome(struct nand_chip *chip, int page)
Roland Stigge2944a442012-06-07 12:22:15 +0200400{
Boris Brezillonb9761682018-09-06 14:05:20 +0200401 struct mtd_info *mtd = nand_to_mtd(chip);
402
Boris Brezillon97d90da2017-11-30 18:01:29 +0100403 return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
Roland Stigge2944a442012-06-07 12:22:15 +0200404}
405
406/*
407 * Write the OOB data to the device without ECC using FIFO method
408 */
409static int lpc32xx_nand_write_oob_syndrome(struct mtd_info *mtd,
410 struct nand_chip *chip, int page)
411{
Boris Brezillon97d90da2017-11-30 18:01:29 +0100412 return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi,
413 mtd->oobsize);
Roland Stigge2944a442012-06-07 12:22:15 +0200414}
415
416/*
417 * Fills in the ECC fields in the OOB buffer with the hardware generated ECC
418 */
419static void lpc32xx_slc_ecc_copy(uint8_t *spare, const uint32_t *ecc, int count)
420{
421 int i;
422
423 for (i = 0; i < (count * 3); i += 3) {
424 uint32_t ce = ecc[i / 3];
425 ce = ~(ce << 2) & 0xFFFFFF;
426 spare[i + 2] = (uint8_t)(ce & 0xFF);
427 ce >>= 8;
428 spare[i + 1] = (uint8_t)(ce & 0xFF);
429 ce >>= 8;
430 spare[i] = (uint8_t)(ce & 0xFF);
431 }
432}
433
434static void lpc32xx_dma_complete_func(void *completion)
435{
436 complete(completion);
437}
438
439static int lpc32xx_xmit_dma(struct mtd_info *mtd, dma_addr_t dma,
440 void *mem, int len, enum dma_transfer_direction dir)
441{
Boris BREZILLON4bd4ebc2015-12-01 12:03:04 +0100442 struct nand_chip *chip = mtd_to_nand(mtd);
Boris BREZILLONd699ed22015-12-10 09:00:41 +0100443 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
Roland Stigge2944a442012-06-07 12:22:15 +0200444 struct dma_async_tx_descriptor *desc;
445 int flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
446 int res;
447
448 host->dma_slave_config.direction = dir;
449 host->dma_slave_config.src_addr = dma;
450 host->dma_slave_config.dst_addr = dma;
451 host->dma_slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
452 host->dma_slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
453 host->dma_slave_config.src_maxburst = 4;
454 host->dma_slave_config.dst_maxburst = 4;
455 /* DMA controller does flow control: */
456 host->dma_slave_config.device_fc = false;
457 if (dmaengine_slave_config(host->dma_chan, &host->dma_slave_config)) {
458 dev_err(mtd->dev.parent, "Failed to setup DMA slave\n");
459 return -ENXIO;
460 }
461
462 sg_init_one(&host->sgl, mem, len);
463
464 res = dma_map_sg(host->dma_chan->device->dev, &host->sgl, 1,
465 DMA_BIDIRECTIONAL);
466 if (res != 1) {
467 dev_err(mtd->dev.parent, "Failed to map sg list\n");
468 return -ENXIO;
469 }
470 desc = dmaengine_prep_slave_sg(host->dma_chan, &host->sgl, 1, dir,
471 flags);
472 if (!desc) {
473 dev_err(mtd->dev.parent, "Failed to prepare slave sg\n");
474 goto out1;
475 }
476
477 init_completion(&host->comp);
478 desc->callback = lpc32xx_dma_complete_func;
479 desc->callback_param = &host->comp;
480
481 dmaengine_submit(desc);
482 dma_async_issue_pending(host->dma_chan);
483
484 wait_for_completion_timeout(&host->comp, msecs_to_jiffies(1000));
485
486 dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
487 DMA_BIDIRECTIONAL);
488
489 return 0;
490out1:
491 dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
492 DMA_BIDIRECTIONAL);
493 return -ENXIO;
494}
495
496/*
497 * DMA read/write transfers with ECC support
498 */
499static int lpc32xx_xfer(struct mtd_info *mtd, uint8_t *buf, int eccsubpages,
500 int read)
501{
Boris BREZILLON4bd4ebc2015-12-01 12:03:04 +0100502 struct nand_chip *chip = mtd_to_nand(mtd);
Boris BREZILLONd699ed22015-12-10 09:00:41 +0100503 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
Roland Stigge2944a442012-06-07 12:22:15 +0200504 int i, status = 0;
505 unsigned long timeout;
506 int res;
507 enum dma_transfer_direction dir =
508 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
509 uint8_t *dma_buf;
510 bool dma_mapped;
511
512 if ((void *)buf <= high_memory) {
513 dma_buf = buf;
514 dma_mapped = true;
515 } else {
516 dma_buf = host->data_buf;
517 dma_mapped = false;
518 if (!read)
519 memcpy(host->data_buf, buf, mtd->writesize);
520 }
521
522 if (read) {
523 writel(readl(SLC_CFG(host->io_base)) |
524 SLCCFG_DMA_DIR | SLCCFG_ECC_EN | SLCCFG_DMA_ECC |
525 SLCCFG_DMA_BURST, SLC_CFG(host->io_base));
526 } else {
527 writel((readl(SLC_CFG(host->io_base)) |
528 SLCCFG_ECC_EN | SLCCFG_DMA_ECC | SLCCFG_DMA_BURST) &
529 ~SLCCFG_DMA_DIR,
530 SLC_CFG(host->io_base));
531 }
532
533 /* Clear initial ECC */
534 writel(SLCCTRL_ECC_CLEAR, SLC_CTRL(host->io_base));
535
536 /* Transfer size is data area only */
537 writel(mtd->writesize, SLC_TC(host->io_base));
538
539 /* Start transfer in the NAND controller */
540 writel(readl(SLC_CTRL(host->io_base)) | SLCCTRL_DMA_START,
541 SLC_CTRL(host->io_base));
542
543 for (i = 0; i < chip->ecc.steps; i++) {
544 /* Data */
545 res = lpc32xx_xmit_dma(mtd, SLC_DMA_DATA(host->io_base_dma),
546 dma_buf + i * chip->ecc.size,
547 mtd->writesize / chip->ecc.steps, dir);
548 if (res)
549 return res;
550
551 /* Always _read_ ECC */
552 if (i == chip->ecc.steps - 1)
553 break;
554 if (!read) /* ECC availability delayed on write */
555 udelay(10);
556 res = lpc32xx_xmit_dma(mtd, SLC_ECC(host->io_base_dma),
557 &host->ecc_buf[i], 4, DMA_DEV_TO_MEM);
558 if (res)
559 return res;
560 }
561
562 /*
563 * According to NXP, the DMA can be finished here, but the NAND
564 * controller may still have buffered data. After porting to using the
565 * dmaengine DMA driver (amba-pl080), the condition (DMA_FIFO empty)
566 * appears to be always true, according to tests. Keeping the check for
567 * safety reasons for now.
568 */
569 if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) {
570 dev_warn(mtd->dev.parent, "FIFO not empty!\n");
571 timeout = jiffies + msecs_to_jiffies(LPC32XX_DMA_TIMEOUT);
572 while ((readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) &&
573 time_before(jiffies, timeout))
574 cpu_relax();
575 if (!time_before(jiffies, timeout)) {
576 dev_err(mtd->dev.parent, "FIFO held data too long\n");
577 status = -EIO;
578 }
579 }
580
581 /* Read last calculated ECC value */
582 if (!read)
583 udelay(10);
584 host->ecc_buf[chip->ecc.steps - 1] =
585 readl(SLC_ECC(host->io_base));
586
587 /* Flush DMA */
588 dmaengine_terminate_all(host->dma_chan);
589
590 if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO ||
591 readl(SLC_TC(host->io_base))) {
592 /* Something is left in the FIFO, something is wrong */
593 dev_err(mtd->dev.parent, "DMA FIFO failure\n");
594 status = -EIO;
595 }
596
597 /* Stop DMA & HW ECC */
598 writel(readl(SLC_CTRL(host->io_base)) & ~SLCCTRL_DMA_START,
599 SLC_CTRL(host->io_base));
600 writel(readl(SLC_CFG(host->io_base)) &
601 ~(SLCCFG_DMA_DIR | SLCCFG_ECC_EN | SLCCFG_DMA_ECC |
602 SLCCFG_DMA_BURST), SLC_CFG(host->io_base));
603
604 if (!dma_mapped && read)
605 memcpy(buf, host->data_buf, mtd->writesize);
606
607 return status;
608}
609
610/*
611 * Read the data and OOB data from the device, use ECC correction with the
612 * data, disable ECC for the OOB data
613 */
Boris Brezillonb9761682018-09-06 14:05:20 +0200614static int lpc32xx_nand_read_page_syndrome(struct nand_chip *chip, uint8_t *buf,
Roland Stigge2944a442012-06-07 12:22:15 +0200615 int oob_required, int page)
616{
Boris Brezillonb9761682018-09-06 14:05:20 +0200617 struct mtd_info *mtd = nand_to_mtd(chip);
Boris BREZILLONd699ed22015-12-10 09:00:41 +0100618 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
Boris Brezillonb9c0f652016-02-03 20:12:04 +0100619 struct mtd_oob_region oobregion = { };
620 int stat, i, status, error;
Roland Stigge2944a442012-06-07 12:22:15 +0200621 uint8_t *oobecc, tmpecc[LPC32XX_ECC_SAVE_SIZE];
622
623 /* Issue read command */
Boris Brezillon97d90da2017-11-30 18:01:29 +0100624 nand_read_page_op(chip, page, 0, NULL, 0);
Roland Stigge2944a442012-06-07 12:22:15 +0200625
626 /* Read data and oob, calculate ECC */
627 status = lpc32xx_xfer(mtd, buf, chip->ecc.steps, 1);
628
629 /* Get OOB data */
630 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
631
632 /* Convert to stored ECC format */
633 lpc32xx_slc_ecc_copy(tmpecc, (uint32_t *) host->ecc_buf, chip->ecc.steps);
634
635 /* Pointer to ECC data retrieved from NAND spare area */
Boris Brezillonb9c0f652016-02-03 20:12:04 +0100636 error = mtd_ooblayout_ecc(mtd, 0, &oobregion);
637 if (error)
638 return error;
639
640 oobecc = chip->oob_poi + oobregion.offset;
Roland Stigge2944a442012-06-07 12:22:15 +0200641
642 for (i = 0; i < chip->ecc.steps; i++) {
Boris Brezillon00da2ea2018-09-06 14:05:19 +0200643 stat = chip->ecc.correct(chip, buf, oobecc,
Roland Stigge2944a442012-06-07 12:22:15 +0200644 &tmpecc[i * chip->ecc.bytes]);
645 if (stat < 0)
646 mtd->ecc_stats.failed++;
647 else
648 mtd->ecc_stats.corrected += stat;
649
650 buf += chip->ecc.size;
651 oobecc += chip->ecc.bytes;
652 }
653
654 return status;
655}
656
657/*
658 * Read the data and OOB data from the device, no ECC correction with the
659 * data or OOB data
660 */
Boris Brezillonb9761682018-09-06 14:05:20 +0200661static int lpc32xx_nand_read_page_raw_syndrome(struct nand_chip *chip,
Roland Stigge2944a442012-06-07 12:22:15 +0200662 uint8_t *buf, int oob_required,
663 int page)
664{
Boris Brezillonb9761682018-09-06 14:05:20 +0200665 struct mtd_info *mtd = nand_to_mtd(chip);
666
Roland Stigge2944a442012-06-07 12:22:15 +0200667 /* Issue read command */
Boris Brezillon97d90da2017-11-30 18:01:29 +0100668 nand_read_page_op(chip, page, 0, NULL, 0);
Roland Stigge2944a442012-06-07 12:22:15 +0200669
670 /* Raw reads can just use the FIFO interface */
671 chip->read_buf(mtd, buf, chip->ecc.size * chip->ecc.steps);
672 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
673
674 return 0;
675}
676
677/*
678 * Write the data and OOB data to the device, use ECC with the data,
679 * disable ECC for the OOB data
680 */
681static int lpc32xx_nand_write_page_syndrome(struct mtd_info *mtd,
682 struct nand_chip *chip,
Boris BREZILLON45aaeff2015-10-13 11:22:18 +0200683 const uint8_t *buf,
684 int oob_required, int page)
Roland Stigge2944a442012-06-07 12:22:15 +0200685{
Boris BREZILLONd699ed22015-12-10 09:00:41 +0100686 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
Boris Brezillonb9c0f652016-02-03 20:12:04 +0100687 struct mtd_oob_region oobregion = { };
688 uint8_t *pb;
Roland Stigge2944a442012-06-07 12:22:15 +0200689 int error;
690
Boris Brezillon25f815f2017-11-30 18:01:30 +0100691 nand_prog_page_begin_op(chip, page, 0, NULL, 0);
692
Roland Stigge2944a442012-06-07 12:22:15 +0200693 /* Write data, calculate ECC on outbound data */
694 error = lpc32xx_xfer(mtd, (uint8_t *)buf, chip->ecc.steps, 0);
695 if (error)
696 return error;
697
698 /*
699 * The calculated ECC needs some manual work done to it before
700 * committing it to NAND. Process the calculated ECC and place
701 * the resultant values directly into the OOB buffer. */
Boris Brezillonb9c0f652016-02-03 20:12:04 +0100702 error = mtd_ooblayout_ecc(mtd, 0, &oobregion);
703 if (error)
704 return error;
705
706 pb = chip->oob_poi + oobregion.offset;
Roland Stigge2944a442012-06-07 12:22:15 +0200707 lpc32xx_slc_ecc_copy(pb, (uint32_t *)host->ecc_buf, chip->ecc.steps);
708
709 /* Write ECC data to device */
710 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
Boris Brezillon25f815f2017-11-30 18:01:30 +0100711
712 return nand_prog_page_end_op(chip);
Roland Stigge2944a442012-06-07 12:22:15 +0200713}
714
715/*
716 * Write the data and OOB data to the device, no ECC correction with the
717 * data or OOB data
718 */
719static int lpc32xx_nand_write_page_raw_syndrome(struct mtd_info *mtd,
720 struct nand_chip *chip,
721 const uint8_t *buf,
Boris BREZILLON45aaeff2015-10-13 11:22:18 +0200722 int oob_required, int page)
Roland Stigge2944a442012-06-07 12:22:15 +0200723{
724 /* Raw writes can just use the FIFO interface */
Boris Brezillon25f815f2017-11-30 18:01:30 +0100725 nand_prog_page_begin_op(chip, page, 0, buf,
726 chip->ecc.size * chip->ecc.steps);
Roland Stigge2944a442012-06-07 12:22:15 +0200727 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
Boris Brezillon25f815f2017-11-30 18:01:30 +0100728
729 return nand_prog_page_end_op(chip);
Roland Stigge2944a442012-06-07 12:22:15 +0200730}
731
Roland Stigge2944a442012-06-07 12:22:15 +0200732static int lpc32xx_nand_dma_setup(struct lpc32xx_nand_host *host)
733{
Boris BREZILLON0faf8c32015-12-10 09:00:10 +0100734 struct mtd_info *mtd = nand_to_mtd(&host->nand_chip);
Roland Stigge2944a442012-06-07 12:22:15 +0200735 dma_cap_mask_t mask;
736
Roland Stiggede20c222012-08-16 15:15:34 +0200737 if (!host->pdata || !host->pdata->dma_filter) {
738 dev_err(mtd->dev.parent, "no DMA platform data\n");
739 return -ENOENT;
740 }
741
Roland Stigge2944a442012-06-07 12:22:15 +0200742 dma_cap_zero(mask);
743 dma_cap_set(DMA_SLAVE, mask);
Roland Stiggede20c222012-08-16 15:15:34 +0200744 host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter,
745 "nand-slc");
Roland Stigge2944a442012-06-07 12:22:15 +0200746 if (!host->dma_chan) {
747 dev_err(mtd->dev.parent, "Failed to request DMA channel\n");
748 return -EBUSY;
749 }
750
751 return 0;
752}
753
Roland Stigge2944a442012-06-07 12:22:15 +0200754static struct lpc32xx_nand_cfg_slc *lpc32xx_parse_dt(struct device *dev)
755{
Roland Stigge10594f62012-08-24 15:06:51 +0200756 struct lpc32xx_nand_cfg_slc *ncfg;
Roland Stigge2944a442012-06-07 12:22:15 +0200757 struct device_node *np = dev->of_node;
758
Roland Stigge10594f62012-08-24 15:06:51 +0200759 ncfg = devm_kzalloc(dev, sizeof(*ncfg), GFP_KERNEL);
Jingoo Han8ecb66b2013-12-26 12:18:56 +0900760 if (!ncfg)
Roland Stigge2944a442012-06-07 12:22:15 +0200761 return NULL;
Roland Stigge2944a442012-06-07 12:22:15 +0200762
Roland Stigge10594f62012-08-24 15:06:51 +0200763 of_property_read_u32(np, "nxp,wdr-clks", &ncfg->wdr_clks);
764 of_property_read_u32(np, "nxp,wwidth", &ncfg->wwidth);
765 of_property_read_u32(np, "nxp,whold", &ncfg->whold);
766 of_property_read_u32(np, "nxp,wsetup", &ncfg->wsetup);
767 of_property_read_u32(np, "nxp,rdr-clks", &ncfg->rdr_clks);
768 of_property_read_u32(np, "nxp,rwidth", &ncfg->rwidth);
769 of_property_read_u32(np, "nxp,rhold", &ncfg->rhold);
770 of_property_read_u32(np, "nxp,rsetup", &ncfg->rsetup);
Roland Stigge2944a442012-06-07 12:22:15 +0200771
Roland Stigge10594f62012-08-24 15:06:51 +0200772 if (!ncfg->wdr_clks || !ncfg->wwidth || !ncfg->whold ||
773 !ncfg->wsetup || !ncfg->rdr_clks || !ncfg->rwidth ||
774 !ncfg->rhold || !ncfg->rsetup) {
Roland Stigge2944a442012-06-07 12:22:15 +0200775 dev_err(dev, "chip parameters not specified correctly\n");
776 return NULL;
777 }
778
Roland Stigge10594f62012-08-24 15:06:51 +0200779 ncfg->wp_gpio = of_get_named_gpio(np, "gpios", 0);
Roland Stigge2944a442012-06-07 12:22:15 +0200780
Roland Stigge10594f62012-08-24 15:06:51 +0200781 return ncfg;
Roland Stigge2944a442012-06-07 12:22:15 +0200782}
Roland Stigge2944a442012-06-07 12:22:15 +0200783
Miquel Raynalf4a48d72018-07-20 17:15:04 +0200784static int lpc32xx_nand_attach_chip(struct nand_chip *chip)
785{
786 struct mtd_info *mtd = nand_to_mtd(chip);
787 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
788
789 /* OOB and ECC CPU and DMA work areas */
790 host->ecc_buf = (uint32_t *)(host->data_buf + LPC32XX_DMA_DATA_SIZE);
791
792 /*
793 * Small page FLASH has a unique OOB layout, but large and huge
794 * page FLASH use the standard layout. Small page FLASH uses a
795 * custom BBT marker layout.
796 */
797 if (mtd->writesize <= 512)
798 mtd_set_ooblayout(mtd, &lpc32xx_ooblayout_ops);
799
800 /* These sizes remain the same regardless of page size */
801 chip->ecc.size = 256;
802 chip->ecc.bytes = LPC32XX_SLC_DEV_ECC_BYTES;
803 chip->ecc.prepad = 0;
804 chip->ecc.postpad = 0;
805
806 /*
807 * Use a custom BBT marker setup for small page FLASH that
808 * won't interfere with the ECC layout. Large and huge page
809 * FLASH use the standard layout.
810 */
811 if ((chip->bbt_options & NAND_BBT_USE_FLASH) &&
812 mtd->writesize <= 512) {
813 chip->bbt_td = &bbt_smallpage_main_descr;
814 chip->bbt_md = &bbt_smallpage_mirror_descr;
815 }
816
817 return 0;
818}
819
820static const struct nand_controller_ops lpc32xx_nand_controller_ops = {
821 .attach_chip = lpc32xx_nand_attach_chip,
822};
823
Roland Stigge2944a442012-06-07 12:22:15 +0200824/*
825 * Probe for NAND controller
826 */
Bill Pemberton06f25512012-11-19 13:23:07 -0500827static int lpc32xx_nand_probe(struct platform_device *pdev)
Roland Stigge2944a442012-06-07 12:22:15 +0200828{
829 struct lpc32xx_nand_host *host;
830 struct mtd_info *mtd;
831 struct nand_chip *chip;
832 struct resource *rc;
Roland Stigge2944a442012-06-07 12:22:15 +0200833 int res;
834
Roland Stigge2944a442012-06-07 12:22:15 +0200835 /* Allocate memory for the device structure (and zero it) */
836 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
Jingoo Han8ecb66b2013-12-26 12:18:56 +0900837 if (!host)
Roland Stigge2944a442012-06-07 12:22:15 +0200838 return -ENOMEM;
Roland Stigge2944a442012-06-07 12:22:15 +0200839
Fabio Estevam4339b7f2016-11-29 13:28:52 -0200840 rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Thierry Redingb0de7742013-01-21 11:09:12 +0100841 host->io_base = devm_ioremap_resource(&pdev->dev, rc);
842 if (IS_ERR(host->io_base))
843 return PTR_ERR(host->io_base);
Roland Stigge2944a442012-06-07 12:22:15 +0200844
Fabio Estevam4339b7f2016-11-29 13:28:52 -0200845 host->io_base_dma = rc->start;
Roland Stigge2944a442012-06-07 12:22:15 +0200846 if (pdev->dev.of_node)
847 host->ncfg = lpc32xx_parse_dt(&pdev->dev);
Roland Stigge2944a442012-06-07 12:22:15 +0200848 if (!host->ncfg) {
Roland Stigge10594f62012-08-24 15:06:51 +0200849 dev_err(&pdev->dev,
850 "Missing or bad NAND config from device tree\n");
Roland Stigge2944a442012-06-07 12:22:15 +0200851 return -ENOENT;
852 }
Roland Stigged5842ab2012-06-27 17:51:15 +0200853 if (host->ncfg->wp_gpio == -EPROBE_DEFER)
854 return -EPROBE_DEFER;
Jingoo Han133432a2013-12-26 10:44:30 +0900855 if (gpio_is_valid(host->ncfg->wp_gpio) && devm_gpio_request(&pdev->dev,
856 host->ncfg->wp_gpio, "NAND WP")) {
Roland Stigge2944a442012-06-07 12:22:15 +0200857 dev_err(&pdev->dev, "GPIO not available\n");
858 return -EBUSY;
859 }
860 lpc32xx_wp_disable(host);
861
Jingoo Han453810b2013-07-30 17:18:33 +0900862 host->pdata = dev_get_platdata(&pdev->dev);
Roland Stiggede20c222012-08-16 15:15:34 +0200863
Roland Stigge2944a442012-06-07 12:22:15 +0200864 chip = &host->nand_chip;
Boris BREZILLON0faf8c32015-12-10 09:00:10 +0100865 mtd = nand_to_mtd(chip);
Boris BREZILLONd699ed22015-12-10 09:00:41 +0100866 nand_set_controller_data(chip, host);
Brian Norrisa61ae812015-10-30 20:33:25 -0700867 nand_set_flash_node(chip, pdev->dev.of_node);
Roland Stigge2944a442012-06-07 12:22:15 +0200868 mtd->owner = THIS_MODULE;
869 mtd->dev.parent = &pdev->dev;
870
871 /* Get NAND clock */
Jingoo Han133432a2013-12-26 10:44:30 +0900872 host->clk = devm_clk_get(&pdev->dev, NULL);
Roland Stigge2944a442012-06-07 12:22:15 +0200873 if (IS_ERR(host->clk)) {
874 dev_err(&pdev->dev, "Clock failure\n");
875 res = -ENOENT;
Miquel Raynale0ea20b2018-04-21 20:00:42 +0200876 goto enable_wp;
Roland Stigge2944a442012-06-07 12:22:15 +0200877 }
Arvind Yadav7c941282017-08-01 17:08:06 +0530878 res = clk_prepare_enable(host->clk);
879 if (res)
Miquel Raynale0ea20b2018-04-21 20:00:42 +0200880 goto enable_wp;
Roland Stigge2944a442012-06-07 12:22:15 +0200881
882 /* Set NAND IO addresses and command/ready functions */
883 chip->IO_ADDR_R = SLC_DATA(host->io_base);
884 chip->IO_ADDR_W = SLC_DATA(host->io_base);
885 chip->cmd_ctrl = lpc32xx_nand_cmd_ctrl;
886 chip->dev_ready = lpc32xx_nand_device_ready;
887 chip->chip_delay = 20; /* 20us command delay time */
888
889 /* Init NAND controller */
890 lpc32xx_nand_setup(host);
891
892 platform_set_drvdata(pdev, host);
893
894 /* NAND callbacks for LPC32xx SLC hardware */
895 chip->ecc.mode = NAND_ECC_HW_SYNDROME;
896 chip->read_byte = lpc32xx_nand_read_byte;
897 chip->read_buf = lpc32xx_nand_read_buf;
898 chip->write_buf = lpc32xx_nand_write_buf;
899 chip->ecc.read_page_raw = lpc32xx_nand_read_page_raw_syndrome;
900 chip->ecc.read_page = lpc32xx_nand_read_page_syndrome;
901 chip->ecc.write_page_raw = lpc32xx_nand_write_page_raw_syndrome;
902 chip->ecc.write_page = lpc32xx_nand_write_page_syndrome;
903 chip->ecc.write_oob = lpc32xx_nand_write_oob_syndrome;
904 chip->ecc.read_oob = lpc32xx_nand_read_oob_syndrome;
905 chip->ecc.calculate = lpc32xx_nand_ecc_calculate;
906 chip->ecc.correct = nand_correct_data;
907 chip->ecc.strength = 1;
908 chip->ecc.hwctl = lpc32xx_nand_ecc_enable;
Roland Stigge2944a442012-06-07 12:22:15 +0200909
Roland Stigge2944a442012-06-07 12:22:15 +0200910 /*
911 * Allocate a large enough buffer for a single huge page plus
912 * extra space for the spare area and ECC storage area
913 */
914 host->dma_buf_len = LPC32XX_DMA_DATA_SIZE + LPC32XX_ECC_SAVE_SIZE;
915 host->data_buf = devm_kzalloc(&pdev->dev, host->dma_buf_len,
916 GFP_KERNEL);
917 if (host->data_buf == NULL) {
Roland Stigge2944a442012-06-07 12:22:15 +0200918 res = -ENOMEM;
Miquel Raynale0ea20b2018-04-21 20:00:42 +0200919 goto unprepare_clk;
Roland Stigge2944a442012-06-07 12:22:15 +0200920 }
921
922 res = lpc32xx_nand_dma_setup(host);
923 if (res) {
924 res = -EIO;
Miquel Raynale0ea20b2018-04-21 20:00:42 +0200925 goto unprepare_clk;
Roland Stigge2944a442012-06-07 12:22:15 +0200926 }
927
928 /* Find NAND device */
Miquel Raynalf4a48d72018-07-20 17:15:04 +0200929 chip->dummy_controller.ops = &lpc32xx_nand_controller_ops;
Boris Brezillon00ad3782018-09-06 14:05:14 +0200930 res = nand_scan(chip, 1);
Masahiro Yamadab04bafc2016-11-04 19:43:01 +0900931 if (res)
Miquel Raynale0ea20b2018-04-21 20:00:42 +0200932 goto release_dma;
Roland Stigge2944a442012-06-07 12:22:15 +0200933
Roland Stigge2944a442012-06-07 12:22:15 +0200934 mtd->name = "nxp_lpc3220_slc";
Brian Norrisa61ae812015-10-30 20:33:25 -0700935 res = mtd_device_register(mtd, host->ncfg->parts,
936 host->ncfg->num_parts);
Miquel Raynale0ea20b2018-04-21 20:00:42 +0200937 if (res)
Miquel Raynal553b0c62018-04-21 20:00:43 +0200938 goto cleanup_nand;
Roland Stigge2944a442012-06-07 12:22:15 +0200939
Miquel Raynale0ea20b2018-04-21 20:00:42 +0200940 return 0;
941
Miquel Raynal553b0c62018-04-21 20:00:43 +0200942cleanup_nand:
943 nand_cleanup(chip);
Miquel Raynale0ea20b2018-04-21 20:00:42 +0200944release_dma:
Roland Stigge2944a442012-06-07 12:22:15 +0200945 dma_release_channel(host->dma_chan);
Miquel Raynale0ea20b2018-04-21 20:00:42 +0200946unprepare_clk:
Vladimir Zapolskiy44cab9c2015-10-17 21:09:29 +0300947 clk_disable_unprepare(host->clk);
Miquel Raynale0ea20b2018-04-21 20:00:42 +0200948enable_wp:
Roland Stigge2944a442012-06-07 12:22:15 +0200949 lpc32xx_wp_enable(host);
Roland Stigge2944a442012-06-07 12:22:15 +0200950
951 return res;
952}
953
954/*
955 * Remove NAND device.
956 */
Bill Pemberton810b7e02012-11-19 13:26:04 -0500957static int lpc32xx_nand_remove(struct platform_device *pdev)
Roland Stigge2944a442012-06-07 12:22:15 +0200958{
959 uint32_t tmp;
960 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
Roland Stigge2944a442012-06-07 12:22:15 +0200961
Boris Brezillon59ac2762018-09-06 14:05:15 +0200962 nand_release(&host->nand_chip);
Roland Stigge2944a442012-06-07 12:22:15 +0200963 dma_release_channel(host->dma_chan);
964
965 /* Force CE high */
966 tmp = readl(SLC_CTRL(host->io_base));
967 tmp &= ~SLCCFG_CE_LOW;
968 writel(tmp, SLC_CTRL(host->io_base));
969
Vladimir Zapolskiy44cab9c2015-10-17 21:09:29 +0300970 clk_disable_unprepare(host->clk);
Roland Stigge2944a442012-06-07 12:22:15 +0200971 lpc32xx_wp_enable(host);
Roland Stigge2944a442012-06-07 12:22:15 +0200972
973 return 0;
974}
975
976#ifdef CONFIG_PM
977static int lpc32xx_nand_resume(struct platform_device *pdev)
978{
979 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
Arvind Yadav7c941282017-08-01 17:08:06 +0530980 int ret;
Roland Stigge2944a442012-06-07 12:22:15 +0200981
982 /* Re-enable NAND clock */
Arvind Yadav7c941282017-08-01 17:08:06 +0530983 ret = clk_prepare_enable(host->clk);
984 if (ret)
985 return ret;
Roland Stigge2944a442012-06-07 12:22:15 +0200986
987 /* Fresh init of NAND controller */
988 lpc32xx_nand_setup(host);
989
990 /* Disable write protect */
991 lpc32xx_wp_disable(host);
992
993 return 0;
994}
995
996static int lpc32xx_nand_suspend(struct platform_device *pdev, pm_message_t pm)
997{
998 uint32_t tmp;
999 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
1000
1001 /* Force CE high */
1002 tmp = readl(SLC_CTRL(host->io_base));
1003 tmp &= ~SLCCFG_CE_LOW;
1004 writel(tmp, SLC_CTRL(host->io_base));
1005
1006 /* Enable write protect for safety */
1007 lpc32xx_wp_enable(host);
1008
1009 /* Disable clock */
Vladimir Zapolskiy44cab9c2015-10-17 21:09:29 +03001010 clk_disable_unprepare(host->clk);
Roland Stigge2944a442012-06-07 12:22:15 +02001011
1012 return 0;
1013}
1014
1015#else
1016#define lpc32xx_nand_resume NULL
1017#define lpc32xx_nand_suspend NULL
1018#endif
1019
Roland Stigge2944a442012-06-07 12:22:15 +02001020static const struct of_device_id lpc32xx_nand_match[] = {
1021 { .compatible = "nxp,lpc3220-slc" },
1022 { /* sentinel */ },
1023};
1024MODULE_DEVICE_TABLE(of, lpc32xx_nand_match);
Roland Stigge2944a442012-06-07 12:22:15 +02001025
1026static struct platform_driver lpc32xx_nand_driver = {
1027 .probe = lpc32xx_nand_probe,
Bill Pemberton5153b882012-11-19 13:21:24 -05001028 .remove = lpc32xx_nand_remove,
Roland Stigge2944a442012-06-07 12:22:15 +02001029 .resume = lpc32xx_nand_resume,
1030 .suspend = lpc32xx_nand_suspend,
1031 .driver = {
1032 .name = LPC32XX_MODNAME,
Sachin Kamatfea7b562013-09-30 15:10:23 +05301033 .of_match_table = lpc32xx_nand_match,
Roland Stigge2944a442012-06-07 12:22:15 +02001034 },
1035};
1036
1037module_platform_driver(lpc32xx_nand_driver);
1038
1039MODULE_LICENSE("GPL");
1040MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
1041MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
1042MODULE_DESCRIPTION("NAND driver for the NXP LPC32XX SLC controller");