blob: 29a1c65661e99d21a4c11754bb94aa379baba181 [file] [log] [blame]
Thomas Gleixner97fb5e82019-05-29 07:17:58 -07001// SPDX-License-Identifier: GPL-2.0-only
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -07002/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -07003 */
Josh Cartwright5a418552014-04-03 14:50:13 -07004#include <linux/of.h>
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -07005#include <linux/module.h>
6#include <linux/init.h>
7#include <linux/rtc.h>
Josh Cartwright5d7dc4c2014-04-03 14:50:11 -07008#include <linux/platform_device.h>
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -07009#include <linux/pm.h>
Josh Cartwright5d7dc4c2014-04-03 14:50:11 -070010#include <linux/regmap.h>
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -070011#include <linux/slab.h>
12#include <linux/spinlock.h>
13
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -070014/* RTC Register offsets from RTC CTRL REG */
15#define PM8XXX_ALARM_CTRL_OFFSET 0x01
16#define PM8XXX_RTC_WRITE_OFFSET 0x02
17#define PM8XXX_RTC_READ_OFFSET 0x06
18#define PM8XXX_ALARM_RW_OFFSET 0x0A
19
20/* RTC_CTRL register bit fields */
21#define PM8xxx_RTC_ENABLE BIT(7)
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -070022#define PM8xxx_RTC_ALARM_CLEAR BIT(0)
Guixiong Wei121f54e2020-12-24 19:28:57 +080023#define PM8xxx_RTC_ALARM_ENABLE BIT(7)
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -070024
25#define NUM_8_BIT_RTC_REGS 0x4
26
27/**
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -070028 * struct pm8xxx_rtc_regs - describe RTC registers per PMIC versions
29 * @ctrl: base address of control register
30 * @write: base address of write register
31 * @read: base address of read register
32 * @alarm_ctrl: base address of alarm control register
33 * @alarm_ctrl2: base address of alarm control2 register
34 * @alarm_rw: base address of alarm read-write register
35 * @alarm_en: alarm enable mask
36 */
37struct pm8xxx_rtc_regs {
38 unsigned int ctrl;
39 unsigned int write;
40 unsigned int read;
41 unsigned int alarm_ctrl;
42 unsigned int alarm_ctrl2;
43 unsigned int alarm_rw;
44 unsigned int alarm_en;
45};
46
47/**
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -070048 * struct pm8xxx_rtc - rtc driver internal structure
49 * @rtc: rtc device for this driver.
Josh Cartwright5d7dc4c2014-04-03 14:50:11 -070050 * @regmap: regmap used to access RTC registers
Josh Cartwright5a418552014-04-03 14:50:13 -070051 * @allow_set_time: indicates whether writing to the RTC is allowed
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -070052 * @rtc_alarm_irq: rtc alarm irq number.
Alexandre Belloni863d7b12019-11-22 11:22:10 +010053 * @regs: rtc registers description.
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -070054 * @rtc_dev: device structure.
55 * @ctrl_reg_lock: spinlock protecting access to ctrl_reg.
56 */
57struct pm8xxx_rtc {
58 struct rtc_device *rtc;
Josh Cartwright5d7dc4c2014-04-03 14:50:11 -070059 struct regmap *regmap;
Josh Cartwright5a418552014-04-03 14:50:13 -070060 bool allow_set_time;
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -070061 int rtc_alarm_irq;
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -070062 const struct pm8xxx_rtc_regs *regs;
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -070063 struct device *rtc_dev;
64 spinlock_t ctrl_reg_lock;
65};
66
67/*
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -070068 * Steps to write the RTC registers.
69 * 1. Disable alarm if enabled.
Mohit Aggarwal83220bf2018-03-05 14:35:58 +053070 * 2. Disable rtc if enabled.
71 * 3. Write 0x00 to LSB.
72 * 4. Write Byte[1], Byte[2], Byte[3] then Byte[0].
73 * 5. Enable rtc if disabled in step 2.
74 * 6. Enable alarm if disabled in step 1.
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -070075 */
76static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
77{
78 int rc, i;
79 unsigned long secs, irq_flags;
Mohit Aggarwal83220bf2018-03-05 14:35:58 +053080 u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0, rtc_disabled = 0;
81 unsigned int ctrl_reg, rtc_ctrl_reg;
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -070082 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -070083 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -070084
Josh Cartwright5a418552014-04-03 14:50:13 -070085 if (!rtc_dd->allow_set_time)
86 return -EACCES;
87
Alexandre Belloni4c470b22020-03-06 08:37:57 +010088 secs = rtc_tm_to_time64(tm);
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -070089
Mohit Aggarwal83220bf2018-03-05 14:35:58 +053090 dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs);
91
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -070092 for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
93 value[i] = secs & 0xFF;
94 secs >>= 8;
95 }
96
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -070097 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -070098
Mohit Aggarwal83220bf2018-03-05 14:35:58 +053099 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700100 if (rc)
101 goto rtc_rw_fail;
102
103 if (ctrl_reg & regs->alarm_en) {
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700104 alarm_enabled = 1;
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700105 ctrl_reg &= ~regs->alarm_en;
Mohit Aggarwal83220bf2018-03-05 14:35:58 +0530106 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
107 if (rc) {
108 dev_err(dev, "Write to RTC Alarm control register failed\n");
109 goto rtc_rw_fail;
110 }
111 }
112
113 /* Disable RTC H/w before writing on RTC register */
114 rc = regmap_read(rtc_dd->regmap, regs->ctrl, &rtc_ctrl_reg);
115 if (rc)
116 goto rtc_rw_fail;
117
118 if (rtc_ctrl_reg & PM8xxx_RTC_ENABLE) {
119 rtc_disabled = 1;
120 rtc_ctrl_reg &= ~PM8xxx_RTC_ENABLE;
121 rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg);
Josh Cartwright5d7dc4c2014-04-03 14:50:11 -0700122 if (rc) {
Josh Cartwright5bed8112014-04-03 14:50:10 -0700123 dev_err(dev, "Write to RTC control register failed\n");
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700124 goto rtc_rw_fail;
125 }
Josh Cartwright5bed8112014-04-03 14:50:10 -0700126 }
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700127
128 /* Write 0 to Byte[0] */
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700129 rc = regmap_write(rtc_dd->regmap, regs->write, 0);
Josh Cartwright5d7dc4c2014-04-03 14:50:11 -0700130 if (rc) {
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700131 dev_err(dev, "Write to RTC write data register failed\n");
132 goto rtc_rw_fail;
133 }
134
135 /* Write Byte[1], Byte[2], Byte[3] */
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700136 rc = regmap_bulk_write(rtc_dd->regmap, regs->write + 1,
Josh Cartwright5d7dc4c2014-04-03 14:50:11 -0700137 &value[1], sizeof(value) - 1);
138 if (rc) {
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700139 dev_err(dev, "Write to RTC write data register failed\n");
140 goto rtc_rw_fail;
141 }
142
143 /* Write Byte[0] */
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700144 rc = regmap_write(rtc_dd->regmap, regs->write, value[0]);
Josh Cartwright5d7dc4c2014-04-03 14:50:11 -0700145 if (rc) {
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700146 dev_err(dev, "Write to RTC write data register failed\n");
147 goto rtc_rw_fail;
148 }
149
Mohit Aggarwal83220bf2018-03-05 14:35:58 +0530150 /* Enable RTC H/w after writing on RTC register */
151 if (rtc_disabled) {
152 rtc_ctrl_reg |= PM8xxx_RTC_ENABLE;
153 rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg);
Josh Cartwright5d7dc4c2014-04-03 14:50:11 -0700154 if (rc) {
Josh Cartwright5bed8112014-04-03 14:50:10 -0700155 dev_err(dev, "Write to RTC control register failed\n");
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700156 goto rtc_rw_fail;
157 }
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700158 }
159
Mohit Aggarwal83220bf2018-03-05 14:35:58 +0530160 if (alarm_enabled) {
161 ctrl_reg |= regs->alarm_en;
162 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
163 if (rc) {
164 dev_err(dev, "Write to RTC Alarm control register failed\n");
165 goto rtc_rw_fail;
166 }
167 }
168
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700169rtc_rw_fail:
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700170 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700171
172 return rc;
173}
174
175static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
176{
177 int rc;
Josh Cartwright5d7dc4c2014-04-03 14:50:11 -0700178 u8 value[NUM_8_BIT_RTC_REGS];
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700179 unsigned long secs;
Josh Cartwright5d7dc4c2014-04-03 14:50:11 -0700180 unsigned int reg;
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700181 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700182 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700183
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700184 rc = regmap_bulk_read(rtc_dd->regmap, regs->read, value, sizeof(value));
Josh Cartwright5d7dc4c2014-04-03 14:50:11 -0700185 if (rc) {
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700186 dev_err(dev, "RTC read data register failed\n");
187 return rc;
188 }
189
190 /*
191 * Read the LSB again and check if there has been a carry over.
192 * If there is, redo the read operation.
193 */
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700194 rc = regmap_read(rtc_dd->regmap, regs->read, &reg);
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700195 if (rc < 0) {
196 dev_err(dev, "RTC read data register failed\n");
197 return rc;
198 }
199
200 if (unlikely(reg < value[0])) {
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700201 rc = regmap_bulk_read(rtc_dd->regmap, regs->read,
Josh Cartwright5d7dc4c2014-04-03 14:50:11 -0700202 value, sizeof(value));
203 if (rc) {
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700204 dev_err(dev, "RTC read data register failed\n");
205 return rc;
206 }
207 }
208
Colin Ian Kinge4228082019-02-06 10:31:02 +0000209 secs = value[0] | (value[1] << 8) | (value[2] << 16) |
210 ((unsigned long)value[3] << 24);
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700211
Alexandre Belloni4c470b22020-03-06 08:37:57 +0100212 rtc_time64_to_tm(secs, tm);
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700213
Andy Shevchenko4f5ef6e2018-12-04 23:23:20 +0200214 dev_dbg(dev, "secs = %lu, h:m:s == %ptRt, y-m-d = %ptRdr\n", secs, tm, tm);
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700215
216 return 0;
217}
218
219static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
220{
221 int rc, i;
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700222 u8 value[NUM_8_BIT_RTC_REGS];
223 unsigned int ctrl_reg;
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700224 unsigned long secs, irq_flags;
225 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700226 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700227
Alexandre Belloni4c470b22020-03-06 08:37:57 +0100228 secs = rtc_tm_to_time64(&alarm->time);
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700229
230 for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
231 value[i] = secs & 0xFF;
232 secs >>= 8;
233 }
234
235 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
236
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700237 rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
Josh Cartwright5d7dc4c2014-04-03 14:50:11 -0700238 sizeof(value));
239 if (rc) {
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700240 dev_err(dev, "Write to RTC ALARM register failed\n");
241 goto rtc_rw_fail;
242 }
243
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700244 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
245 if (rc)
246 goto rtc_rw_fail;
Josh Cartwright5bed8112014-04-03 14:50:10 -0700247
248 if (alarm->enabled)
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700249 ctrl_reg |= regs->alarm_en;
Josh Cartwright5bed8112014-04-03 14:50:10 -0700250 else
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700251 ctrl_reg &= ~regs->alarm_en;
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700252
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700253 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
Josh Cartwright5d7dc4c2014-04-03 14:50:11 -0700254 if (rc) {
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700255 dev_err(dev, "Write to RTC alarm control register failed\n");
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700256 goto rtc_rw_fail;
257 }
258
Andy Shevchenko4f5ef6e2018-12-04 23:23:20 +0200259 dev_dbg(dev, "Alarm Set for h:m:s=%ptRt, y-m-d=%ptRdr\n",
260 &alarm->time, &alarm->time);
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700261rtc_rw_fail:
262 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
263 return rc;
264}
265
266static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
267{
268 int rc;
Guixiong Wei121f54e2020-12-24 19:28:57 +0800269 unsigned int ctrl_reg;
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700270 u8 value[NUM_8_BIT_RTC_REGS];
271 unsigned long secs;
272 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700273 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700274
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700275 rc = regmap_bulk_read(rtc_dd->regmap, regs->alarm_rw, value,
Josh Cartwright5d7dc4c2014-04-03 14:50:11 -0700276 sizeof(value));
277 if (rc) {
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700278 dev_err(dev, "RTC alarm time read failed\n");
279 return rc;
280 }
281
Colin Ian Kinge4228082019-02-06 10:31:02 +0000282 secs = value[0] | (value[1] << 8) | (value[2] << 16) |
283 ((unsigned long)value[3] << 24);
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700284
Alexandre Belloni4c470b22020-03-06 08:37:57 +0100285 rtc_time64_to_tm(secs, &alarm->time);
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700286
Guixiong Wei121f54e2020-12-24 19:28:57 +0800287 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
288 if (rc) {
289 dev_err(dev, "Read from RTC alarm control register failed\n");
290 return rc;
291 }
292 alarm->enabled = !!(ctrl_reg & PM8xxx_RTC_ALARM_ENABLE);
293
Andy Shevchenko4f5ef6e2018-12-04 23:23:20 +0200294 dev_dbg(dev, "Alarm set for - h:m:s=%ptRt, y-m-d=%ptRdr\n",
295 &alarm->time, &alarm->time);
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700296
297 return 0;
298}
299
300static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
301{
302 int rc;
303 unsigned long irq_flags;
304 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700305 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
306 unsigned int ctrl_reg;
韩科才34ce2972020-03-21 19:50:17 +0800307 u8 value[NUM_8_BIT_RTC_REGS] = {0};
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700308
309 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
Josh Cartwright5bed8112014-04-03 14:50:10 -0700310
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700311 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
312 if (rc)
313 goto rtc_rw_fail;
Josh Cartwright5bed8112014-04-03 14:50:10 -0700314
315 if (enable)
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700316 ctrl_reg |= regs->alarm_en;
Josh Cartwright5bed8112014-04-03 14:50:10 -0700317 else
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700318 ctrl_reg &= ~regs->alarm_en;
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700319
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700320 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
Josh Cartwright5d7dc4c2014-04-03 14:50:11 -0700321 if (rc) {
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700322 dev_err(dev, "Write to RTC control register failed\n");
323 goto rtc_rw_fail;
324 }
325
韩科才34ce2972020-03-21 19:50:17 +0800326 /* Clear Alarm register */
327 if (!enable) {
328 rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
329 sizeof(value));
330 if (rc) {
331 dev_err(dev, "Clear RTC ALARM register failed\n");
332 goto rtc_rw_fail;
333 }
334 }
335
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700336rtc_rw_fail:
337 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
338 return rc;
339}
340
Josh Cartwright5a418552014-04-03 14:50:13 -0700341static const struct rtc_class_ops pm8xxx_rtc_ops = {
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700342 .read_time = pm8xxx_rtc_read_time,
Josh Cartwright5a418552014-04-03 14:50:13 -0700343 .set_time = pm8xxx_rtc_set_time,
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700344 .set_alarm = pm8xxx_rtc_set_alarm,
345 .read_alarm = pm8xxx_rtc_read_alarm,
346 .alarm_irq_enable = pm8xxx_rtc_alarm_irq_enable,
347};
348
349static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id)
350{
351 struct pm8xxx_rtc *rtc_dd = dev_id;
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700352 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
Josh Cartwright5d7dc4c2014-04-03 14:50:11 -0700353 unsigned int ctrl_reg;
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700354 int rc;
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700355
356 rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC_AF);
357
Xiaofei Tan51317972021-02-03 20:39:37 +0800358 spin_lock(&rtc_dd->ctrl_reg_lock);
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700359
360 /* Clear the alarm enable bit */
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700361 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
362 if (rc) {
Xiaofei Tan51317972021-02-03 20:39:37 +0800363 spin_unlock(&rtc_dd->ctrl_reg_lock);
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700364 goto rtc_alarm_handled;
365 }
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700366
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700367 ctrl_reg &= ~regs->alarm_en;
368
369 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
Josh Cartwright5d7dc4c2014-04-03 14:50:11 -0700370 if (rc) {
Xiaofei Tan51317972021-02-03 20:39:37 +0800371 spin_unlock(&rtc_dd->ctrl_reg_lock);
Josh Cartwright5bed8112014-04-03 14:50:10 -0700372 dev_err(rtc_dd->rtc_dev,
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700373 "Write to alarm control register failed\n");
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700374 goto rtc_alarm_handled;
375 }
376
Xiaofei Tan51317972021-02-03 20:39:37 +0800377 spin_unlock(&rtc_dd->ctrl_reg_lock);
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700378
379 /* Clear RTC alarm register */
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700380 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl2, &ctrl_reg);
Josh Cartwright5d7dc4c2014-04-03 14:50:11 -0700381 if (rc) {
Josh Cartwright5bed8112014-04-03 14:50:10 -0700382 dev_err(rtc_dd->rtc_dev,
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700383 "RTC Alarm control2 register read failed\n");
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700384 goto rtc_alarm_handled;
385 }
386
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700387 ctrl_reg |= PM8xxx_RTC_ALARM_CLEAR;
388 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl2, ctrl_reg);
Josh Cartwright5d7dc4c2014-04-03 14:50:11 -0700389 if (rc)
Josh Cartwright5bed8112014-04-03 14:50:10 -0700390 dev_err(rtc_dd->rtc_dev,
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700391 "Write to RTC Alarm control2 register failed\n");
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700392
393rtc_alarm_handled:
394 return IRQ_HANDLED;
395}
396
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700397static int pm8xxx_rtc_enable(struct pm8xxx_rtc *rtc_dd)
398{
399 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
400 unsigned int ctrl_reg;
401 int rc;
402
403 /* Check if the RTC is on, else turn it on */
404 rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg);
405 if (rc)
406 return rc;
407
408 if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) {
409 ctrl_reg |= PM8xxx_RTC_ENABLE;
410 rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
411 if (rc)
412 return rc;
413 }
414
415 return 0;
416}
417
418static const struct pm8xxx_rtc_regs pm8921_regs = {
419 .ctrl = 0x11d,
420 .write = 0x11f,
421 .read = 0x123,
422 .alarm_rw = 0x127,
423 .alarm_ctrl = 0x11d,
424 .alarm_ctrl2 = 0x11e,
425 .alarm_en = BIT(1),
426};
427
428static const struct pm8xxx_rtc_regs pm8058_regs = {
429 .ctrl = 0x1e8,
430 .write = 0x1ea,
431 .read = 0x1ee,
432 .alarm_rw = 0x1f2,
433 .alarm_ctrl = 0x1e8,
434 .alarm_ctrl2 = 0x1e9,
435 .alarm_en = BIT(1),
436};
437
438static const struct pm8xxx_rtc_regs pm8941_regs = {
439 .ctrl = 0x6046,
440 .write = 0x6040,
441 .read = 0x6048,
442 .alarm_rw = 0x6140,
443 .alarm_ctrl = 0x6146,
444 .alarm_ctrl2 = 0x6148,
445 .alarm_en = BIT(7),
446};
447
satya priyac8f0ca82021-04-09 19:29:23 +0530448static const struct pm8xxx_rtc_regs pmk8350_regs = {
449 .ctrl = 0x6146,
450 .write = 0x6140,
451 .read = 0x6148,
452 .alarm_rw = 0x6240,
453 .alarm_ctrl = 0x6246,
454 .alarm_ctrl2 = 0x6248,
455 .alarm_en = BIT(7),
456};
457
Josh Cartwright5a418552014-04-03 14:50:13 -0700458/*
459 * Hardcoded RTC bases until IORESOURCE_REG mapping is figured out
460 */
461static const struct of_device_id pm8xxx_id_table[] = {
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700462 { .compatible = "qcom,pm8921-rtc", .data = &pm8921_regs },
Neil Armstrong08655bc2016-08-11 15:16:44 +0200463 { .compatible = "qcom,pm8018-rtc", .data = &pm8921_regs },
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700464 { .compatible = "qcom,pm8058-rtc", .data = &pm8058_regs },
465 { .compatible = "qcom,pm8941-rtc", .data = &pm8941_regs },
satya priyac8f0ca82021-04-09 19:29:23 +0530466 { .compatible = "qcom,pmk8350-rtc", .data = &pmk8350_regs },
Josh Cartwright5a418552014-04-03 14:50:13 -0700467 { },
468};
469MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
470
Greg Kroah-Hartman5a167f42012-12-21 13:09:38 -0800471static int pm8xxx_rtc_probe(struct platform_device *pdev)
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700472{
473 int rc;
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700474 struct pm8xxx_rtc *rtc_dd;
Josh Cartwright5a418552014-04-03 14:50:13 -0700475 const struct of_device_id *match;
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700476
Josh Cartwright5a418552014-04-03 14:50:13 -0700477 match = of_match_node(pm8xxx_id_table, pdev->dev.of_node);
478 if (!match)
479 return -ENXIO;
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700480
Jingoo Hanc4172992013-07-03 15:07:09 -0700481 rtc_dd = devm_kzalloc(&pdev->dev, sizeof(*rtc_dd), GFP_KERNEL);
Jingoo Han49ae4252014-04-03 14:49:43 -0700482 if (rtc_dd == NULL)
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700483 return -ENOMEM;
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700484
485 /* Initialise spinlock to protect RTC control register */
486 spin_lock_init(&rtc_dd->ctrl_reg_lock);
487
Josh Cartwright5d7dc4c2014-04-03 14:50:11 -0700488 rtc_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL);
489 if (!rtc_dd->regmap) {
490 dev_err(&pdev->dev, "Parent regmap unavailable.\n");
491 return -ENXIO;
492 }
493
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700494 rtc_dd->rtc_alarm_irq = platform_get_irq(pdev, 0);
Stephen Boydfaac9102019-07-30 11:15:39 -0700495 if (rtc_dd->rtc_alarm_irq < 0)
Jingoo Hanc4172992013-07-03 15:07:09 -0700496 return -ENXIO;
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700497
Josh Cartwright5a418552014-04-03 14:50:13 -0700498 rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node,
499 "allow-set-time");
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700500
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700501 rtc_dd->regs = match->data;
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700502 rtc_dd->rtc_dev = &pdev->dev;
503
Stanimir Varbanovc8d523a2014-10-29 14:50:33 -0700504 rc = pm8xxx_rtc_enable(rtc_dd);
505 if (rc)
Jingoo Hanc4172992013-07-03 15:07:09 -0700506 return rc;
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700507
508 platform_set_drvdata(pdev, rtc_dd);
509
Josh Cartwrightfda99092014-04-03 14:50:14 -0700510 device_init_wakeup(&pdev->dev, 1);
511
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700512 /* Register the RTC device */
Alexandre Bellonid5d55b72020-03-06 08:37:55 +0100513 rtc_dd->rtc = devm_rtc_allocate_device(&pdev->dev);
514 if (IS_ERR(rtc_dd->rtc))
Jingoo Hanc4172992013-07-03 15:07:09 -0700515 return PTR_ERR(rtc_dd->rtc);
Alexandre Bellonid5d55b72020-03-06 08:37:55 +0100516
517 rtc_dd->rtc->ops = &pm8xxx_rtc_ops;
Alexandre Belloni3cfe5262020-03-06 08:37:56 +0100518 rtc_dd->rtc->range_max = U32_MAX;
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700519
520 /* Request the alarm IRQ */
Josh Cartwrightbffcbc02014-04-03 14:50:12 -0700521 rc = devm_request_any_context_irq(&pdev->dev, rtc_dd->rtc_alarm_irq,
522 pm8xxx_alarm_trigger,
523 IRQF_TRIGGER_RISING,
524 "pm8xxx_rtc_alarm", rtc_dd);
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700525 if (rc < 0) {
526 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", rc);
Jingoo Hanc4172992013-07-03 15:07:09 -0700527 return rc;
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700528 }
529
Bartosz Golaszewskifdcfd852020-11-09 17:34:08 +0100530 return devm_rtc_register_device(rtc_dd->rtc);
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700531}
532
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700533#ifdef CONFIG_PM_SLEEP
534static int pm8xxx_rtc_resume(struct device *dev)
535{
536 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
537
538 if (device_may_wakeup(dev))
539 disable_irq_wake(rtc_dd->rtc_alarm_irq);
540
541 return 0;
542}
543
544static int pm8xxx_rtc_suspend(struct device *dev)
545{
546 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
547
548 if (device_may_wakeup(dev))
549 enable_irq_wake(rtc_dd->rtc_alarm_irq);
550
551 return 0;
552}
553#endif
554
Josh Cartwright5bed8112014-04-03 14:50:10 -0700555static SIMPLE_DEV_PM_OPS(pm8xxx_rtc_pm_ops,
556 pm8xxx_rtc_suspend,
557 pm8xxx_rtc_resume);
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700558
559static struct platform_driver pm8xxx_rtc_driver = {
560 .probe = pm8xxx_rtc_probe,
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700561 .driver = {
Josh Cartwright5a418552014-04-03 14:50:13 -0700562 .name = "rtc-pm8xxx",
Josh Cartwright5a418552014-04-03 14:50:13 -0700563 .pm = &pm8xxx_rtc_pm_ops,
564 .of_match_table = pm8xxx_id_table,
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700565 },
566};
567
Axel Lin0c4eae62012-01-10 15:10:48 -0800568module_platform_driver(pm8xxx_rtc_driver);
Anirudh Ghayal9a9a54a2011-07-25 17:13:33 -0700569
570MODULE_ALIAS("platform:rtc-pm8xxx");
571MODULE_DESCRIPTION("PMIC8xxx RTC driver");
572MODULE_LICENSE("GPL v2");
573MODULE_AUTHOR("Anirudh Ghayal <aghayal@codeaurora.org>");