blob: c7b217d4d1c1e3c1c714e1525416fcd63983f1a1 [file] [log] [blame]
Kuninori Morimotocfa66a82013-07-24 00:36:51 -07001/*
2 * Bock-W board support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/of_platform.h>
Kuninori Morimotocfa66a82013-07-24 00:36:51 -070022#include <mach/common.h>
23#include <mach/r8a7778.h>
24#include <asm/mach/arch.h>
25
26/*
27 * see board-bock.c for checking detail of dip-switch
28 */
29
30static const struct pinctrl_map bockw_pinctrl_map[] = {
31 /* SCIF0 */
32 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
33 "scif0_data_a", "scif0"),
34 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
35 "scif0_ctrl", "scif0"),
36};
37
Kuninori Morimoto90357fc2013-10-02 01:33:36 -070038#define FPGA 0x18200000
39#define IRQ0MR 0x30
40#define COMCTLR 0x101c
Kuninori Morimotocfa66a82013-07-24 00:36:51 -070041static void __init bockw_init(void)
42{
Kuninori Morimotob6d3eba2013-10-10 23:35:06 -070043 void __iomem *fpga;
Kuninori Morimoto90357fc2013-10-02 01:33:36 -070044
Kuninori Morimotocfa66a82013-07-24 00:36:51 -070045 r8a7778_clock_init();
Kuninori Morimoto90357fc2013-10-02 01:33:36 -070046 r8a7778_init_irq_extpin_dt(1);
Kuninori Morimotocfa66a82013-07-24 00:36:51 -070047
48 pinctrl_register_mappings(bockw_pinctrl_map,
49 ARRAY_SIZE(bockw_pinctrl_map));
50 r8a7778_pinmux_init();
51 r8a7778_add_dt_devices();
52
Kuninori Morimoto90357fc2013-10-02 01:33:36 -070053 fpga = ioremap_nocache(FPGA, SZ_1M);
54 if (fpga) {
55 /*
56 * CAUTION
57 *
58 * IRQ0/1 is cascaded interrupt from FPGA.
59 * it should be cared in the future
60 * Now, it is assuming IRQ0 was used only from SMSC.
61 */
62 u16 val = ioread16(fpga + IRQ0MR);
63 val &= ~(1 << 4); /* enable SMSC911x */
64 iowrite16(val, fpga + IRQ0MR);
Kuninori Morimotob6d3eba2013-10-10 23:35:06 -070065
66 iounmap(fpga);
Kuninori Morimoto90357fc2013-10-02 01:33:36 -070067 }
68
Kuninori Morimotocfa66a82013-07-24 00:36:51 -070069 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
70}
71
72static const char *bockw_boards_compat_dt[] __initdata = {
73 "renesas,bockw-reference",
74 NULL,
75};
76
77DT_MACHINE_START(BOCKW_DT, "bockw")
78 .init_early = r8a7778_init_delay,
79 .init_irq = r8a7778_init_irq_dt,
80 .init_machine = bockw_init,
Kuninori Morimotocfa66a82013-07-24 00:36:51 -070081 .dt_compat = bockw_boards_compat_dt,
82MACHINE_END