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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / b6a32a28cd6c99cd13ce6e72fcd7080e76c7e259 / . / drivers / pinctrl / pinctrl-sunxi-pins.h
blob: 6fd8d4d951406aec5f01c021c2c80b84ebf4f4b0 [file] [log] [blame]
Maxime Ripard44abb932013-06-09 18:36:03 +0200[diff] [blame]1/*
2 * Allwinner A1X SoCs pinctrl driver.
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#ifndef __PINCTRL_SUNXI_PINS_H
14#define __PINCTRL_SUNXI_PINS_H
15
16#include "pinctrl-sunxi.h"
17
18static const struct sunxi_desc_pin sun4i_a10_pins[] = {
19 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
20 SUNXI_FUNCTION(0x0, "gpio_in"),
21 SUNXI_FUNCTION(0x1, "gpio_out"),
22 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
23 SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
24 SUNXI_FUNCTION(0x4, "uart2")), /* RTS */
25 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1,
26 SUNXI_FUNCTION(0x0, "gpio_in"),
27 SUNXI_FUNCTION(0x1, "gpio_out"),
28 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
29 SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
30 SUNXI_FUNCTION(0x4, "uart2")), /* CTS */
31 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2,
32 SUNXI_FUNCTION(0x0, "gpio_in"),
33 SUNXI_FUNCTION(0x1, "gpio_out"),
34 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
35 SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
36 SUNXI_FUNCTION(0x4, "uart2")), /* TX */
37 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3,
38 SUNXI_FUNCTION(0x0, "gpio_in"),
39 SUNXI_FUNCTION(0x1, "gpio_out"),
40 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
41 SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
42 SUNXI_FUNCTION(0x4, "uart2")), /* RX */
43 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4,
44 SUNXI_FUNCTION(0x0, "gpio_in"),
45 SUNXI_FUNCTION(0x1, "gpio_out"),
46 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
47 SUNXI_FUNCTION(0x3, "spi1")), /* CS1 */
48 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5,
49 SUNXI_FUNCTION(0x0, "gpio_in"),
50 SUNXI_FUNCTION(0x1, "gpio_out"),
51 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
52 SUNXI_FUNCTION(0x3, "spi3")), /* CS0 */
53 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6,
54 SUNXI_FUNCTION(0x0, "gpio_in"),
55 SUNXI_FUNCTION(0x1, "gpio_out"),
56 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
57 SUNXI_FUNCTION(0x3, "spi3")), /* CLK */
58 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7,
59 SUNXI_FUNCTION(0x0, "gpio_in"),
60 SUNXI_FUNCTION(0x1, "gpio_out"),
61 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
62 SUNXI_FUNCTION(0x3, "spi3")), /* MOSI */
63 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8,
64 SUNXI_FUNCTION(0x0, "gpio_in"),
65 SUNXI_FUNCTION(0x1, "gpio_out"),
66 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
67 SUNXI_FUNCTION(0x3, "spi3")), /* MISO */
68 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9,
69 SUNXI_FUNCTION(0x0, "gpio_in"),
70 SUNXI_FUNCTION(0x1, "gpio_out"),
71 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
72 SUNXI_FUNCTION(0x3, "spi3")), /* CS1 */
73 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10,
74 SUNXI_FUNCTION(0x0, "gpio_in"),
75 SUNXI_FUNCTION(0x1, "gpio_out"),
76 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
77 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
78 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11,
79 SUNXI_FUNCTION(0x0, "gpio_in"),
80 SUNXI_FUNCTION(0x1, "gpio_out"),
81 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
82 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
83 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12,
84 SUNXI_FUNCTION(0x0, "gpio_in"),
85 SUNXI_FUNCTION(0x1, "gpio_out"),
86 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */
87 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
88 SUNXI_FUNCTION(0x4, "uart1")), /* RTS */
89 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13,
90 SUNXI_FUNCTION(0x0, "gpio_in"),
91 SUNXI_FUNCTION(0x1, "gpio_out"),
92 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */
93 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
94 SUNXI_FUNCTION(0x4, "uart1")), /* CTS */
95 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14,
96 SUNXI_FUNCTION(0x0, "gpio_in"),
97 SUNXI_FUNCTION(0x1, "gpio_out"),
98 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */
99 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
100 SUNXI_FUNCTION(0x4, "uart1")), /* DTR */
101 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15,
102 SUNXI_FUNCTION(0x0, "gpio_in"),
103 SUNXI_FUNCTION(0x1, "gpio_out"),
104 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */
105 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
106 SUNXI_FUNCTION(0x4, "uart1")), /* DSR */
107 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16,
108 SUNXI_FUNCTION(0x0, "gpio_in"),
109 SUNXI_FUNCTION(0x1, "gpio_out"),
110 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */
111 SUNXI_FUNCTION(0x3, "can"), /* TX */
112 SUNXI_FUNCTION(0x4, "uart1")), /* DCD */
113 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17,
114 SUNXI_FUNCTION(0x0, "gpio_in"),
115 SUNXI_FUNCTION(0x1, "gpio_out"),
116 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */
117 SUNXI_FUNCTION(0x3, "can"), /* RX */
118 SUNXI_FUNCTION(0x4, "uart1")), /* RING */
119 /* Hole */
120 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
121 SUNXI_FUNCTION(0x0, "gpio_in"),
122 SUNXI_FUNCTION(0x1, "gpio_out"),
123 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
124 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
125 SUNXI_FUNCTION(0x0, "gpio_in"),
126 SUNXI_FUNCTION(0x1, "gpio_out"),
127 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
128 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
129 SUNXI_FUNCTION(0x0, "gpio_in"),
130 SUNXI_FUNCTION(0x1, "gpio_out"),
131 SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */
132 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
133 SUNXI_FUNCTION(0x0, "gpio_in"),
134 SUNXI_FUNCTION(0x1, "gpio_out"),
135 SUNXI_FUNCTION(0x2, "ir0")), /* TX */
136 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
137 SUNXI_FUNCTION(0x0, "gpio_in"),
138 SUNXI_FUNCTION(0x1, "gpio_out"),
139 SUNXI_FUNCTION(0x2, "ir0")), /* RX */
140 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5,
141 SUNXI_FUNCTION(0x0, "gpio_in"),
142 SUNXI_FUNCTION(0x1, "gpio_out"),
143 SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
144 SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */
145 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6,
146 SUNXI_FUNCTION(0x0, "gpio_in"),
147 SUNXI_FUNCTION(0x1, "gpio_out"),
148 SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */
149 SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */
150 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7,
151 SUNXI_FUNCTION(0x0, "gpio_in"),
152 SUNXI_FUNCTION(0x1, "gpio_out"),
153 SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */
154 SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */
155 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8,
156 SUNXI_FUNCTION(0x0, "gpio_in"),
157 SUNXI_FUNCTION(0x1, "gpio_out"),
158 SUNXI_FUNCTION(0x2, "i2s"), /* DO0 */
159 SUNXI_FUNCTION(0x3, "ac97")), /* DO */
160 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9,
161 SUNXI_FUNCTION(0x0, "gpio_in"),
162 SUNXI_FUNCTION(0x1, "gpio_out"),
163 SUNXI_FUNCTION(0x2, "i2s")), /* DO1 */
164 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
165 SUNXI_FUNCTION(0x0, "gpio_in"),
166 SUNXI_FUNCTION(0x1, "gpio_out"),
167 SUNXI_FUNCTION(0x2, "i2s")), /* DO2 */
168 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11,
169 SUNXI_FUNCTION(0x0, "gpio_in"),
170 SUNXI_FUNCTION(0x1, "gpio_out"),
171 SUNXI_FUNCTION(0x2, "i2s")), /* DO3 */
172 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12,
173 SUNXI_FUNCTION(0x0, "gpio_in"),
174 SUNXI_FUNCTION(0x1, "gpio_out"),
175 SUNXI_FUNCTION(0x2, "i2s"), /* DI */
176 SUNXI_FUNCTION(0x3, "ac97")), /* DI */
177 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13,
178 SUNXI_FUNCTION(0x0, "gpio_in"),
179 SUNXI_FUNCTION(0x1, "gpio_out"),
180 SUNXI_FUNCTION(0x2, "spi2")), /* CS1 */
181 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14,
182 SUNXI_FUNCTION(0x0, "gpio_in"),
183 SUNXI_FUNCTION(0x1, "gpio_out"),
184 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
185 SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */
186 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
187 SUNXI_FUNCTION(0x0, "gpio_in"),
188 SUNXI_FUNCTION(0x1, "gpio_out"),
189 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
190 SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */
191 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
192 SUNXI_FUNCTION(0x0, "gpio_in"),
193 SUNXI_FUNCTION(0x1, "gpio_out"),
194 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
195 SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */
196 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
197 SUNXI_FUNCTION(0x0, "gpio_in"),
198 SUNXI_FUNCTION(0x1, "gpio_out"),
199 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
200 SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */
201 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
202 SUNXI_FUNCTION(0x0, "gpio_in"),
203 SUNXI_FUNCTION(0x1, "gpio_out"),
204 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
205 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19,
206 SUNXI_FUNCTION(0x0, "gpio_in"),
207 SUNXI_FUNCTION(0x1, "gpio_out"),
208 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
209 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20,
210 SUNXI_FUNCTION(0x0, "gpio_in"),
211 SUNXI_FUNCTION(0x1, "gpio_out"),
212 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
213 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB21,
214 SUNXI_FUNCTION(0x0, "gpio_in"),
215 SUNXI_FUNCTION(0x1, "gpio_out"),
216 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
217 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB22,
218 SUNXI_FUNCTION(0x0, "gpio_in"),
219 SUNXI_FUNCTION(0x1, "gpio_out"),
220 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
221 SUNXI_FUNCTION(0x3, "ir1")), /* TX */
222 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB23,
223 SUNXI_FUNCTION(0x0, "gpio_in"),
224 SUNXI_FUNCTION(0x1, "gpio_out"),
225 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
226 SUNXI_FUNCTION(0x3, "ir1")), /* RX */
227 /* Hole */
228 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
229 SUNXI_FUNCTION(0x0, "gpio_in"),
230 SUNXI_FUNCTION(0x1, "gpio_out"),
231 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
232 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
233 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
234 SUNXI_FUNCTION(0x0, "gpio_in"),
235 SUNXI_FUNCTION(0x1, "gpio_out"),
236 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
237 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
238 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
239 SUNXI_FUNCTION(0x0, "gpio_in"),
240 SUNXI_FUNCTION(0x1, "gpio_out"),
241 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
242 SUNXI_FUNCTION(0x3, "spi0")), /* SCK */
243 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
244 SUNXI_FUNCTION(0x0, "gpio_in"),
245 SUNXI_FUNCTION(0x1, "gpio_out"),
246 SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */
247 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
248 SUNXI_FUNCTION(0x0, "gpio_in"),
249 SUNXI_FUNCTION(0x1, "gpio_out"),
250 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
251 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
252 SUNXI_FUNCTION(0x0, "gpio_in"),
253 SUNXI_FUNCTION(0x1, "gpio_out"),
254 SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */
255 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
256 SUNXI_FUNCTION(0x0, "gpio_in"),
257 SUNXI_FUNCTION(0x1, "gpio_out"),
258 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
259 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
260 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
261 SUNXI_FUNCTION(0x0, "gpio_in"),
262 SUNXI_FUNCTION(0x1, "gpio_out"),
263 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
264 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
265 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
266 SUNXI_FUNCTION(0x0, "gpio_in"),
267 SUNXI_FUNCTION(0x1, "gpio_out"),
268 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
269 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
270 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
271 SUNXI_FUNCTION(0x0, "gpio_in"),
272 SUNXI_FUNCTION(0x1, "gpio_out"),
273 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
274 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
275 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
276 SUNXI_FUNCTION(0x0, "gpio_in"),
277 SUNXI_FUNCTION(0x1, "gpio_out"),
278 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
279 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
280 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
281 SUNXI_FUNCTION(0x0, "gpio_in"),
282 SUNXI_FUNCTION(0x1, "gpio_out"),
283 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
284 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
285 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
286 SUNXI_FUNCTION(0x0, "gpio_in"),
287 SUNXI_FUNCTION(0x1, "gpio_out"),
288 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */
289 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
290 SUNXI_FUNCTION(0x0, "gpio_in"),
291 SUNXI_FUNCTION(0x1, "gpio_out"),
292 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */
293 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
294 SUNXI_FUNCTION(0x0, "gpio_in"),
295 SUNXI_FUNCTION(0x1, "gpio_out"),
296 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */
297 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
298 SUNXI_FUNCTION(0x0, "gpio_in"),
299 SUNXI_FUNCTION(0x1, "gpio_out"),
300 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */
301 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16,
302 SUNXI_FUNCTION(0x0, "gpio_in"),
303 SUNXI_FUNCTION(0x1, "gpio_out"),
304 SUNXI_FUNCTION(0x2, "nand0")), /* NWP */
305 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17,
306 SUNXI_FUNCTION(0x0, "gpio_in"),
307 SUNXI_FUNCTION(0x1, "gpio_out"),
308 SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */
309 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18,
310 SUNXI_FUNCTION(0x0, "gpio_in"),
311 SUNXI_FUNCTION(0x1, "gpio_out"),
312 SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */
313 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
314 SUNXI_FUNCTION(0x0, "gpio_in"),
315 SUNXI_FUNCTION(0x1, "gpio_out"),
316 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
317 SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */
318 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20,
319 SUNXI_FUNCTION(0x0, "gpio_in"),
320 SUNXI_FUNCTION(0x1, "gpio_out"),
321 SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */
322 SUNXI_FUNCTION(0x3, "spi2")), /* CLK */
323 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21,
324 SUNXI_FUNCTION(0x0, "gpio_in"),
325 SUNXI_FUNCTION(0x1, "gpio_out"),
326 SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */
327 SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */
328 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22,
329 SUNXI_FUNCTION(0x0, "gpio_in"),
330 SUNXI_FUNCTION(0x1, "gpio_out"),
331 SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */
332 SUNXI_FUNCTION(0x3, "spi2")), /* MISO */
333 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23,
334 SUNXI_FUNCTION(0x0, "gpio_in"),
335 SUNXI_FUNCTION(0x1, "gpio_out"),
336 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
337 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24,
338 SUNXI_FUNCTION(0x0, "gpio_in"),
339 SUNXI_FUNCTION(0x1, "gpio_out"),
340 SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */
341 /* Hole */
342 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0,
343 SUNXI_FUNCTION(0x0, "gpio_in"),
344 SUNXI_FUNCTION(0x1, "gpio_out"),
345 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
346 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
347 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1,
348 SUNXI_FUNCTION(0x0, "gpio_in"),
349 SUNXI_FUNCTION(0x1, "gpio_out"),
350 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
351 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
352 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
353 SUNXI_FUNCTION(0x0, "gpio_in"),
354 SUNXI_FUNCTION(0x1, "gpio_out"),
355 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
356 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
357 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
358 SUNXI_FUNCTION(0x0, "gpio_in"),
359 SUNXI_FUNCTION(0x1, "gpio_out"),
360 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
361 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
362 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
363 SUNXI_FUNCTION(0x0, "gpio_in"),
364 SUNXI_FUNCTION(0x1, "gpio_out"),
365 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
366 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
367 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
368 SUNXI_FUNCTION(0x0, "gpio_in"),
369 SUNXI_FUNCTION(0x1, "gpio_out"),
370 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
371 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
372 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
373 SUNXI_FUNCTION(0x0, "gpio_in"),
374 SUNXI_FUNCTION(0x1, "gpio_out"),
375 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
376 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
377 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
378 SUNXI_FUNCTION(0x0, "gpio_in"),
379 SUNXI_FUNCTION(0x1, "gpio_out"),
380 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
381 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
382 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8,
383 SUNXI_FUNCTION(0x0, "gpio_in"),
384 SUNXI_FUNCTION(0x1, "gpio_out"),
385 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
386 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
387 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9,
388 SUNXI_FUNCTION(0x0, "gpio_in"),
389 SUNXI_FUNCTION(0x1, "gpio_out"),
390 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
391 SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */
392 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
393 SUNXI_FUNCTION(0x0, "gpio_in"),
394 SUNXI_FUNCTION(0x1, "gpio_out"),
395 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
396 SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */
397 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
398 SUNXI_FUNCTION(0x0, "gpio_in"),
399 SUNXI_FUNCTION(0x1, "gpio_out"),
400 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
401 SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */
402 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
403 SUNXI_FUNCTION(0x0, "gpio_in"),
404 SUNXI_FUNCTION(0x1, "gpio_out"),
405 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
406 SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */
407 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
408 SUNXI_FUNCTION(0x0, "gpio_in"),
409 SUNXI_FUNCTION(0x1, "gpio_out"),
410 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
411 SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */
412 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
413 SUNXI_FUNCTION(0x0, "gpio_in"),
414 SUNXI_FUNCTION(0x1, "gpio_out"),
415 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
416 SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */
417 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
418 SUNXI_FUNCTION(0x0, "gpio_in"),
419 SUNXI_FUNCTION(0x1, "gpio_out"),
420 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
421 SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */
422 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16,
423 SUNXI_FUNCTION(0x0, "gpio_in"),
424 SUNXI_FUNCTION(0x1, "gpio_out"),
425 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
426 SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */
427 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17,
428 SUNXI_FUNCTION(0x0, "gpio_in"),
429 SUNXI_FUNCTION(0x1, "gpio_out"),
430 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
431 SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */
432 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
433 SUNXI_FUNCTION(0x0, "gpio_in"),
434 SUNXI_FUNCTION(0x1, "gpio_out"),
435 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
436 SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */
437 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
438 SUNXI_FUNCTION(0x0, "gpio_in"),
439 SUNXI_FUNCTION(0x1, "gpio_out"),
440 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
441 SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */
442 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
443 SUNXI_FUNCTION(0x0, "gpio_in"),
444 SUNXI_FUNCTION(0x1, "gpio_out"),
445 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
446 SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */
447 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
448 SUNXI_FUNCTION(0x0, "gpio_in"),
449 SUNXI_FUNCTION(0x1, "gpio_out"),
450 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
451 SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */
452 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
453 SUNXI_FUNCTION(0x0, "gpio_in"),
454 SUNXI_FUNCTION(0x1, "gpio_out"),
455 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
456 SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */
457 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
458 SUNXI_FUNCTION(0x0, "gpio_in"),
459 SUNXI_FUNCTION(0x1, "gpio_out"),
460 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
461 SUNXI_FUNCTION(0x3, "sim")), /* DET */
462 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
463 SUNXI_FUNCTION(0x0, "gpio_in"),
464 SUNXI_FUNCTION(0x1, "gpio_out"),
465 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
466 SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */
467 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
468 SUNXI_FUNCTION(0x0, "gpio_in"),
469 SUNXI_FUNCTION(0x1, "gpio_out"),
470 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
471 SUNXI_FUNCTION(0x3, "sim")), /* RST */
472 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
473 SUNXI_FUNCTION(0x0, "gpio_in"),
474 SUNXI_FUNCTION(0x1, "gpio_out"),
475 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
476 SUNXI_FUNCTION(0x3, "sim")), /* SCK */
477 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
478 SUNXI_FUNCTION(0x0, "gpio_in"),
479 SUNXI_FUNCTION(0x1, "gpio_out"),
480 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
481 SUNXI_FUNCTION(0x3, "sim")), /* SDA */
482 /* Hole */
483 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
484 SUNXI_FUNCTION(0x0, "gpio_in"),
485 SUNXI_FUNCTION(0x1, "gpio_out"),
486 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
487 SUNXI_FUNCTION(0x3, "csi0")), /* PCK */
488 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
489 SUNXI_FUNCTION(0x0, "gpio_in"),
490 SUNXI_FUNCTION(0x1, "gpio_out"),
491 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
492 SUNXI_FUNCTION(0x3, "csi0")), /* CK */
493 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
494 SUNXI_FUNCTION(0x0, "gpio_in"),
495 SUNXI_FUNCTION(0x1, "gpio_out"),
496 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
497 SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */
498 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
499 SUNXI_FUNCTION(0x0, "gpio_in"),
500 SUNXI_FUNCTION(0x1, "gpio_out"),
501 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
502 SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */
503 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
504 SUNXI_FUNCTION(0x0, "gpio_in"),
505 SUNXI_FUNCTION(0x1, "gpio_out"),
506 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
507 SUNXI_FUNCTION(0x3, "csi0")), /* D0 */
508 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
509 SUNXI_FUNCTION(0x0, "gpio_in"),
510 SUNXI_FUNCTION(0x1, "gpio_out"),
511 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
512 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
513 SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */
514 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
515 SUNXI_FUNCTION(0x0, "gpio_in"),
516 SUNXI_FUNCTION(0x1, "gpio_out"),
517 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
518 SUNXI_FUNCTION(0x3, "csi0")), /* D2 */
519 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
520 SUNXI_FUNCTION(0x0, "gpio_in"),
521 SUNXI_FUNCTION(0x1, "gpio_out"),
522 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
523 SUNXI_FUNCTION(0x3, "csi0")), /* D3 */
524 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
525 SUNXI_FUNCTION(0x0, "gpio_in"),
526 SUNXI_FUNCTION(0x1, "gpio_out"),
527 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
528 SUNXI_FUNCTION(0x3, "csi0")), /* D4 */
529 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
530 SUNXI_FUNCTION(0x0, "gpio_in"),
531 SUNXI_FUNCTION(0x1, "gpio_out"),
532 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
533 SUNXI_FUNCTION(0x3, "csi0")), /* D5 */
534 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
535 SUNXI_FUNCTION(0x0, "gpio_in"),
536 SUNXI_FUNCTION(0x1, "gpio_out"),
537 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
538 SUNXI_FUNCTION(0x3, "csi0")), /* D6 */
539 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
540 SUNXI_FUNCTION(0x0, "gpio_in"),
541 SUNXI_FUNCTION(0x1, "gpio_out"),
542 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
543 SUNXI_FUNCTION(0x3, "csi0")), /* D7 */
544 /* Hole */
545 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
546 SUNXI_FUNCTION(0x0, "gpio_in"),
547 SUNXI_FUNCTION(0x1, "gpio_out"),
548 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
549 SUNXI_FUNCTION(0x4, "jtag")), /* MSI */
550 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
551 SUNXI_FUNCTION(0x0, "gpio_in"),
552 SUNXI_FUNCTION(0x1, "gpio_out"),
553 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
554 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
555 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
556 SUNXI_FUNCTION(0x0, "gpio_in"),
557 SUNXI_FUNCTION(0x1, "gpio_out"),
558 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
559 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
560 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
561 SUNXI_FUNCTION(0x0, "gpio_in"),
562 SUNXI_FUNCTION(0x1, "gpio_out"),
563 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
564 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
565 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
566 SUNXI_FUNCTION(0x0, "gpio_in"),
567 SUNXI_FUNCTION(0x1, "gpio_out"),
568 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
569 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
570 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
571 SUNXI_FUNCTION(0x0, "gpio_in"),
572 SUNXI_FUNCTION(0x1, "gpio_out"),
573 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
574 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
575 /* Hole */
576 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
577 SUNXI_FUNCTION(0x0, "gpio_in"),
578 SUNXI_FUNCTION(0x1, "gpio_out"),
579 SUNXI_FUNCTION(0x2, "ts1"), /* CLK */
580 SUNXI_FUNCTION(0x3, "csi1"), /* PCK */
581 SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */
582 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
583 SUNXI_FUNCTION(0x0, "gpio_in"),
584 SUNXI_FUNCTION(0x1, "gpio_out"),
585 SUNXI_FUNCTION(0x2, "ts1"), /* ERR */
586 SUNXI_FUNCTION(0x3, "csi1"), /* CK */
587 SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */
588 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
589 SUNXI_FUNCTION(0x0, "gpio_in"),
590 SUNXI_FUNCTION(0x1, "gpio_out"),
591 SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */
592 SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */
593 SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */
594 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
595 SUNXI_FUNCTION(0x0, "gpio_in"),
596 SUNXI_FUNCTION(0x1, "gpio_out"),
597 SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */
598 SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */
599 SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */
600 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
601 SUNXI_FUNCTION(0x0, "gpio_in"),
602 SUNXI_FUNCTION(0x1, "gpio_out"),
603 SUNXI_FUNCTION(0x2, "ts1"), /* D0 */
604 SUNXI_FUNCTION(0x3, "csi1"), /* D0 */
605 SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */
606 SUNXI_FUNCTION(0x5, "csi0")), /* D8 */
607 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5,
608 SUNXI_FUNCTION(0x0, "gpio_in"),
609 SUNXI_FUNCTION(0x1, "gpio_out"),
610 SUNXI_FUNCTION(0x2, "ts1"), /* D1 */
611 SUNXI_FUNCTION(0x3, "csi1"), /* D1 */
612 SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */
613 SUNXI_FUNCTION(0x5, "csi0")), /* D9 */
614 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6,
615 SUNXI_FUNCTION(0x0, "gpio_in"),
616 SUNXI_FUNCTION(0x1, "gpio_out"),
617 SUNXI_FUNCTION(0x2, "ts1"), /* D2 */
618 SUNXI_FUNCTION(0x3, "csi1"), /* D2 */
619 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
620 SUNXI_FUNCTION(0x5, "csi0")), /* D10 */
621 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7,
622 SUNXI_FUNCTION(0x0, "gpio_in"),
623 SUNXI_FUNCTION(0x1, "gpio_out"),
624 SUNXI_FUNCTION(0x2, "ts1"), /* D3 */
625 SUNXI_FUNCTION(0x3, "csi1"), /* D3 */
626 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
627 SUNXI_FUNCTION(0x5, "csi0")), /* D11 */
628 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8,
629 SUNXI_FUNCTION(0x0, "gpio_in"),
630 SUNXI_FUNCTION(0x1, "gpio_out"),
631 SUNXI_FUNCTION(0x2, "ts1"), /* D4 */
632 SUNXI_FUNCTION(0x3, "csi1"), /* D4 */
633 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
634 SUNXI_FUNCTION(0x5, "csi0")), /* D12 */
635 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
636 SUNXI_FUNCTION(0x0, "gpio_in"),
637 SUNXI_FUNCTION(0x1, "gpio_out"),
638 SUNXI_FUNCTION(0x2, "ts1"), /* D5 */
639 SUNXI_FUNCTION(0x3, "csi1"), /* D5 */
640 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
641 SUNXI_FUNCTION(0x5, "csi0")), /* D13 */
642 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
643 SUNXI_FUNCTION(0x0, "gpio_in"),
644 SUNXI_FUNCTION(0x1, "gpio_out"),
645 SUNXI_FUNCTION(0x2, "ts1"), /* D6 */
646 SUNXI_FUNCTION(0x3, "csi1"), /* D6 */
647 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
648 SUNXI_FUNCTION(0x5, "csi0")), /* D14 */
649 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
650 SUNXI_FUNCTION(0x0, "gpio_in"),
651 SUNXI_FUNCTION(0x1, "gpio_out"),
652 SUNXI_FUNCTION(0x2, "ts1"), /* D7 */
653 SUNXI_FUNCTION(0x3, "csi1"), /* D7 */
654 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
655 SUNXI_FUNCTION(0x5, "csi0")), /* D15 */
656 /* Hole */
657 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0,
658 SUNXI_FUNCTION(0x0, "gpio_in"),
659 SUNXI_FUNCTION(0x1, "gpio_out"),
660 SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */
661 SUNXI_FUNCTION(0x3, "pata"), /* ATAA0 */
662 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
663 SUNXI_FUNCTION_IRQ(0x6, 0), /* EINT0 */
664 SUNXI_FUNCTION(0x7, "csi1")), /* D0 */
665 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1,
666 SUNXI_FUNCTION(0x0, "gpio_in"),
667 SUNXI_FUNCTION(0x1, "gpio_out"),
668 SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */
669 SUNXI_FUNCTION(0x3, "pata"), /* ATAA1 */
670 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
671 SUNXI_FUNCTION_IRQ(0x6, 1), /* EINT1 */
672 SUNXI_FUNCTION(0x7, "csi1")), /* D1 */
673 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2,
674 SUNXI_FUNCTION(0x0, "gpio_in"),
675 SUNXI_FUNCTION(0x1, "gpio_out"),
676 SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */
677 SUNXI_FUNCTION(0x3, "pata"), /* ATAA2 */
678 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
679 SUNXI_FUNCTION_IRQ(0x6, 2), /* EINT2 */
680 SUNXI_FUNCTION(0x7, "csi1")), /* D2 */
681 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3,
682 SUNXI_FUNCTION(0x0, "gpio_in"),
683 SUNXI_FUNCTION(0x1, "gpio_out"),
684 SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */
685 SUNXI_FUNCTION(0x3, "pata"), /* ATAIRQ */
686 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
687 SUNXI_FUNCTION_IRQ(0x6, 3), /* EINT3 */
688 SUNXI_FUNCTION(0x7, "csi1")), /* D3 */
689 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4,
690 SUNXI_FUNCTION(0x0, "gpio_in"),
691 SUNXI_FUNCTION(0x1, "gpio_out"),
692 SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */
693 SUNXI_FUNCTION(0x3, "pata"), /* ATAD0 */
694 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
695 SUNXI_FUNCTION_IRQ(0x6, 4), /* EINT4 */
696 SUNXI_FUNCTION(0x7, "csi1")), /* D4 */
697 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5,
698 SUNXI_FUNCTION(0x0, "gpio_in"),
699 SUNXI_FUNCTION(0x1, "gpio_out"),
700 SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */
701 SUNXI_FUNCTION(0x3, "pata"), /* ATAD1 */
702 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
703 SUNXI_FUNCTION_IRQ(0x6, 5), /* EINT5 */
704 SUNXI_FUNCTION(0x7, "csi1")), /* D5 */
705 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6,
706 SUNXI_FUNCTION(0x0, "gpio_in"),
707 SUNXI_FUNCTION(0x1, "gpio_out"),
708 SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */
709 SUNXI_FUNCTION(0x3, "pata"), /* ATAD2 */
710 SUNXI_FUNCTION(0x4, "uart5"), /* TX */
711 SUNXI_FUNCTION(0x5, "ms"), /* BS */
712 SUNXI_FUNCTION_IRQ(0x6, 6), /* EINT6 */
713 SUNXI_FUNCTION(0x7, "csi1")), /* D6 */
714 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7,
715 SUNXI_FUNCTION(0x0, "gpio_in"),
716 SUNXI_FUNCTION(0x1, "gpio_out"),
717 SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */
718 SUNXI_FUNCTION(0x3, "pata"), /* ATAD3 */
719 SUNXI_FUNCTION(0x4, "uart5"), /* RX */
720 SUNXI_FUNCTION(0x5, "ms"), /* CLK */
721 SUNXI_FUNCTION_IRQ(0x6, 7), /* EINT7 */
722 SUNXI_FUNCTION(0x7, "csi1")), /* D7 */
723 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8,
724 SUNXI_FUNCTION(0x0, "gpio_in"),
725 SUNXI_FUNCTION(0x1, "gpio_out"),
726 SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */
727 SUNXI_FUNCTION(0x3, "pata"), /* ATAD4 */
728 SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */
729 SUNXI_FUNCTION(0x5, "ms"), /* D0 */
730 SUNXI_FUNCTION_IRQ(0x6, 8), /* EINT8 */
731 SUNXI_FUNCTION(0x7, "csi1")), /* D8 */
732 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9,
733 SUNXI_FUNCTION(0x0, "gpio_in"),
734 SUNXI_FUNCTION(0x1, "gpio_out"),
735 SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */
736 SUNXI_FUNCTION(0x3, "pata"), /* ATAD5 */
737 SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */
738 SUNXI_FUNCTION(0x5, "ms"), /* D1 */
739 SUNXI_FUNCTION_IRQ(0x6, 9), /* EINT9 */
740 SUNXI_FUNCTION(0x7, "csi1")), /* D9 */
741 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10,
742 SUNXI_FUNCTION(0x0, "gpio_in"),
743 SUNXI_FUNCTION(0x1, "gpio_out"),
744 SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */
745 SUNXI_FUNCTION(0x3, "pata"), /* ATAD6 */
746 SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */
747 SUNXI_FUNCTION(0x5, "ms"), /* D2 */
748 SUNXI_FUNCTION_IRQ(0x6, 10), /* EINT10 */
749 SUNXI_FUNCTION(0x7, "csi1")), /* D10 */
750 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11,
751 SUNXI_FUNCTION(0x0, "gpio_in"),
752 SUNXI_FUNCTION(0x1, "gpio_out"),
753 SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */
754 SUNXI_FUNCTION(0x3, "pata"), /* ATAD7 */
755 SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */
756 SUNXI_FUNCTION(0x5, "ms"), /* D3 */
757 SUNXI_FUNCTION_IRQ(0x6, 11), /* EINT11 */
758 SUNXI_FUNCTION(0x7, "csi1")), /* D11 */
759 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12,
760 SUNXI_FUNCTION(0x0, "gpio_in"),
761 SUNXI_FUNCTION(0x1, "gpio_out"),
762 SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */
763 SUNXI_FUNCTION(0x3, "pata"), /* ATAD8 */
764 SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */
765 SUNXI_FUNCTION_IRQ(0x6, 12), /* EINT12 */
766 SUNXI_FUNCTION(0x7, "csi1")), /* D12 */
767 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13,
768 SUNXI_FUNCTION(0x0, "gpio_in"),
769 SUNXI_FUNCTION(0x1, "gpio_out"),
770 SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */
771 SUNXI_FUNCTION(0x3, "pata"), /* ATAD9 */
772 SUNXI_FUNCTION(0x4, "ps2"), /* SDA1 */
773 SUNXI_FUNCTION(0x5, "sim"), /* RST */
774 SUNXI_FUNCTION_IRQ(0x6, 13), /* EINT13 */
775 SUNXI_FUNCTION(0x7, "csi1")), /* D13 */
776 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14,
777 SUNXI_FUNCTION(0x0, "gpio_in"),
778 SUNXI_FUNCTION(0x1, "gpio_out"),
779 SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */
780 SUNXI_FUNCTION(0x3, "pata"), /* ATAD10 */
781 SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */
782 SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */
783 SUNXI_FUNCTION_IRQ(0x6, 14), /* EINT14 */
784 SUNXI_FUNCTION(0x7, "csi1")), /* D14 */
785 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15,
786 SUNXI_FUNCTION(0x0, "gpio_in"),
787 SUNXI_FUNCTION(0x1, "gpio_out"),
788 SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */
789 SUNXI_FUNCTION(0x3, "pata"), /* ATAD11 */
790 SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */
791 SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */
792 SUNXI_FUNCTION_IRQ(0x6, 15), /* EINT15 */
793 SUNXI_FUNCTION(0x7, "csi1")), /* D15 */
794 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16,
795 SUNXI_FUNCTION(0x0, "gpio_in"),
796 SUNXI_FUNCTION(0x1, "gpio_out"),
797 SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */
798 SUNXI_FUNCTION(0x3, "pata"), /* ATAD12 */
799 SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */
800 SUNXI_FUNCTION_IRQ(0x6, 16), /* EINT16 */
801 SUNXI_FUNCTION(0x7, "csi1")), /* D16 */
802 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17,
803 SUNXI_FUNCTION(0x0, "gpio_in"),
804 SUNXI_FUNCTION(0x1, "gpio_out"),
805 SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */
806 SUNXI_FUNCTION(0x3, "pata"), /* ATAD13 */
807 SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */
808 SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */
Maxime Ripard30e71662013-08-04 11:58:46 +0200[diff] [blame]809 SUNXI_FUNCTION_IRQ(0x6, 17), /* EINT17 */
Maxime Ripard44abb932013-06-09 18:36:03 +0200[diff] [blame]810 SUNXI_FUNCTION(0x7, "csi1")), /* D17 */
811 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18,
812 SUNXI_FUNCTION(0x0, "gpio_in"),
813 SUNXI_FUNCTION(0x1, "gpio_out"),
814 SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */
815 SUNXI_FUNCTION(0x3, "pata"), /* ATAD14 */
816 SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */
817 SUNXI_FUNCTION(0x5, "sim"), /* SCK */
Maxime Ripard30e71662013-08-04 11:58:46 +0200[diff] [blame]818 SUNXI_FUNCTION_IRQ(0x6, 18), /* EINT18 */
Maxime Ripard44abb932013-06-09 18:36:03 +0200[diff] [blame]819 SUNXI_FUNCTION(0x7, "csi1")), /* D18 */
820 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19,
821 SUNXI_FUNCTION(0x0, "gpio_in"),
822 SUNXI_FUNCTION(0x1, "gpio_out"),
823 SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */
824 SUNXI_FUNCTION(0x3, "pata"), /* ATAD15 */
825 SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */
826 SUNXI_FUNCTION(0x5, "sim"), /* SDA */
Maxime Ripard30e71662013-08-04 11:58:46 +0200[diff] [blame]827 SUNXI_FUNCTION_IRQ(0x6, 19), /* EINT19 */
Maxime Ripard44abb932013-06-09 18:36:03 +0200[diff] [blame]828 SUNXI_FUNCTION(0x7, "csi1")), /* D19 */
829 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20,
830 SUNXI_FUNCTION(0x0, "gpio_in"),
831 SUNXI_FUNCTION(0x1, "gpio_out"),
832 SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */
833 SUNXI_FUNCTION(0x3, "pata"), /* ATAOE */
834 SUNXI_FUNCTION(0x4, "can"), /* TX */
Maxime Ripard30e71662013-08-04 11:58:46 +0200[diff] [blame]835 SUNXI_FUNCTION_IRQ(0x6, 20), /* EINT20 */
Maxime Ripard44abb932013-06-09 18:36:03 +0200[diff] [blame]836 SUNXI_FUNCTION(0x7, "csi1")), /* D20 */
837 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21,
838 SUNXI_FUNCTION(0x0, "gpio_in"),
839 SUNXI_FUNCTION(0x1, "gpio_out"),
840 SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */
841 SUNXI_FUNCTION(0x3, "pata"), /* ATADREQ */
842 SUNXI_FUNCTION(0x4, "can"), /* RX */
Maxime Ripard30e71662013-08-04 11:58:46 +0200[diff] [blame]843 SUNXI_FUNCTION_IRQ(0x6, 21), /* EINT21 */
Maxime Ripard44abb932013-06-09 18:36:03 +0200[diff] [blame]844 SUNXI_FUNCTION(0x7, "csi1")), /* D21 */
845 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22,
846 SUNXI_FUNCTION(0x0, "gpio_in"),
847 SUNXI_FUNCTION(0x1, "gpio_out"),
848 SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */
849 SUNXI_FUNCTION(0x3, "pata"), /* ATADACK */
850 SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */
851 SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */
852 SUNXI_FUNCTION(0x7, "csi1")), /* D22 */
853 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23,
854 SUNXI_FUNCTION(0x0, "gpio_in"),
855 SUNXI_FUNCTION(0x1, "gpio_out"),
856 SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */
857 SUNXI_FUNCTION(0x3, "pata"), /* ATACS0 */
858 SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */
859 SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */
860 SUNXI_FUNCTION(0x7, "csi1")), /* D23 */
861 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24,
862 SUNXI_FUNCTION(0x0, "gpio_in"),
863 SUNXI_FUNCTION(0x1, "gpio_out"),
864 SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */
865 SUNXI_FUNCTION(0x3, "pata"), /* ATACS1 */
866 SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */
867 SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */
868 SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */
869 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25,
870 SUNXI_FUNCTION(0x0, "gpio_in"),
871 SUNXI_FUNCTION(0x1, "gpio_out"),
872 SUNXI_FUNCTION(0x2, "lcd1"), /* DE */
873 SUNXI_FUNCTION(0x3, "pata"), /* ATAIORDY */
874 SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */
875 SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */
876 SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */
877 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26,
878 SUNXI_FUNCTION(0x0, "gpio_in"),
879 SUNXI_FUNCTION(0x1, "gpio_out"),
880 SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */
881 SUNXI_FUNCTION(0x3, "pata"), /* ATAIOR */
882 SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */
883 SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */
884 SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */
885 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27,
886 SUNXI_FUNCTION(0x0, "gpio_in"),
887 SUNXI_FUNCTION(0x1, "gpio_out"),
888 SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */
889 SUNXI_FUNCTION(0x3, "pata"), /* ATAIOW */
890 SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */
891 SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */
892 SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */
893 /* Hole */
894 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI0,
895 SUNXI_FUNCTION(0x0, "gpio_in"),
896 SUNXI_FUNCTION(0x1, "gpio_out")),
897 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI1,
898 SUNXI_FUNCTION(0x0, "gpio_in"),
899 SUNXI_FUNCTION(0x1, "gpio_out")),
900 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI2,
901 SUNXI_FUNCTION(0x0, "gpio_in"),
902 SUNXI_FUNCTION(0x1, "gpio_out")),
903 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI3,
904 SUNXI_FUNCTION(0x0, "gpio_in"),
905 SUNXI_FUNCTION(0x1, "gpio_out"),
906 SUNXI_FUNCTION(0x2, "pwm")), /* PWM1 */
907 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI4,
908 SUNXI_FUNCTION(0x0, "gpio_in"),
909 SUNXI_FUNCTION(0x1, "gpio_out"),
910 SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */
911 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI5,
912 SUNXI_FUNCTION(0x0, "gpio_in"),
913 SUNXI_FUNCTION(0x1, "gpio_out"),
914 SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */
915 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI6,
916 SUNXI_FUNCTION(0x0, "gpio_in"),
917 SUNXI_FUNCTION(0x1, "gpio_out"),
918 SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */
919 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI7,
920 SUNXI_FUNCTION(0x0, "gpio_in"),
921 SUNXI_FUNCTION(0x1, "gpio_out"),
922 SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */
923 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI8,
924 SUNXI_FUNCTION(0x0, "gpio_in"),
925 SUNXI_FUNCTION(0x1, "gpio_out"),
926 SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */
927 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI9,
928 SUNXI_FUNCTION(0x0, "gpio_in"),
929 SUNXI_FUNCTION(0x1, "gpio_out"),
930 SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */
931 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI10,
932 SUNXI_FUNCTION(0x0, "gpio_in"),
933 SUNXI_FUNCTION(0x1, "gpio_out"),
934 SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
935 SUNXI_FUNCTION(0x3, "uart5"), /* TX */
936 SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */
937 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI11,
938 SUNXI_FUNCTION(0x0, "gpio_in"),
939 SUNXI_FUNCTION(0x1, "gpio_out"),
940 SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
941 SUNXI_FUNCTION(0x3, "uart5"), /* RX */
942 SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */
943 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI12,
944 SUNXI_FUNCTION(0x0, "gpio_in"),
945 SUNXI_FUNCTION(0x1, "gpio_out"),
946 SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
947 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
948 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
949 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13,
950 SUNXI_FUNCTION(0x0, "gpio_in"),
951 SUNXI_FUNCTION(0x1, "gpio_out"),
952 SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
953 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
954 SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */
955 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14,
956 SUNXI_FUNCTION(0x0, "gpio_in"),
957 SUNXI_FUNCTION(0x1, "gpio_out"),
958 SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */
959 SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */
960 SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */
961 SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */
962 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI15,
963 SUNXI_FUNCTION(0x0, "gpio_in"),
964 SUNXI_FUNCTION(0x1, "gpio_out"),
965 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
966 SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */
967 SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */
968 SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */
969 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI16,
970 SUNXI_FUNCTION(0x0, "gpio_in"),
971 SUNXI_FUNCTION(0x1, "gpio_out"),
972 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
973 SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
974 SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */
975 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI17,
976 SUNXI_FUNCTION(0x0, "gpio_in"),
977 SUNXI_FUNCTION(0x1, "gpio_out"),
978 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
979 SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
980 SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */
981 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI18,
982 SUNXI_FUNCTION(0x0, "gpio_in"),
983 SUNXI_FUNCTION(0x1, "gpio_out"),
984 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
985 SUNXI_FUNCTION(0x3, "uart2"), /* TX */
986 SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */
987 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI19,
988 SUNXI_FUNCTION(0x0, "gpio_in"),
989 SUNXI_FUNCTION(0x1, "gpio_out"),
990 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
991 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
992 SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */
993 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI20,
994 SUNXI_FUNCTION(0x0, "gpio_in"),
995 SUNXI_FUNCTION(0x1, "gpio_out"),
996 SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */
997 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
998 SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */
999 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI21,
1000 SUNXI_FUNCTION(0x0, "gpio_in"),
1001 SUNXI_FUNCTION(0x1, "gpio_out"),
1002 SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */
1003 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
1004 SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */
1005};
1006
Maxime Ripardac689362013-06-09 18:36:04 +0200[diff] [blame]1007static const struct sunxi_desc_pin sun5i_a10s_pins[] = {
1008 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
1009 SUNXI_FUNCTION(0x0, "gpio_in"),
1010 SUNXI_FUNCTION(0x1, "gpio_out"),
1011 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
1012 SUNXI_FUNCTION(0x3, "ts0"), /* CLK */
1013 SUNXI_FUNCTION(0x5, "keypad")), /* IN0 */
1014 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1,
1015 SUNXI_FUNCTION(0x0, "gpio_in"),
1016 SUNXI_FUNCTION(0x1, "gpio_out"),
1017 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
1018 SUNXI_FUNCTION(0x3, "ts0"), /* ERR */
1019 SUNXI_FUNCTION(0x5, "keypad")), /* IN1 */
1020 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2,
1021 SUNXI_FUNCTION(0x0, "gpio_in"),
1022 SUNXI_FUNCTION(0x1, "gpio_out"),
1023 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
1024 SUNXI_FUNCTION(0x3, "ts0"), /* SYNC */
1025 SUNXI_FUNCTION(0x5, "keypad")), /* IN2 */
1026 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3,
1027 SUNXI_FUNCTION(0x0, "gpio_in"),
1028 SUNXI_FUNCTION(0x1, "gpio_out"),
1029 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
1030 SUNXI_FUNCTION(0x3, "ts0"), /* DLVD */
1031 SUNXI_FUNCTION(0x5, "keypad")), /* IN3 */
1032 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4,
1033 SUNXI_FUNCTION(0x0, "gpio_in"),
1034 SUNXI_FUNCTION(0x1, "gpio_out"),
1035 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
1036 SUNXI_FUNCTION(0x3, "ts0"), /* D0 */
1037 SUNXI_FUNCTION(0x5, "keypad")), /* IN4 */
1038 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5,
1039 SUNXI_FUNCTION(0x0, "gpio_in"),
1040 SUNXI_FUNCTION(0x1, "gpio_out"),
1041 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
1042 SUNXI_FUNCTION(0x3, "ts0"), /* D1 */
1043 SUNXI_FUNCTION(0x5, "keypad")), /* IN5 */
1044 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6,
1045 SUNXI_FUNCTION(0x0, "gpio_in"),
1046 SUNXI_FUNCTION(0x1, "gpio_out"),
1047 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
1048 SUNXI_FUNCTION(0x3, "ts0"), /* D2 */
1049 SUNXI_FUNCTION(0x5, "keypad")), /* IN6 */
1050 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7,
1051 SUNXI_FUNCTION(0x0, "gpio_in"),
1052 SUNXI_FUNCTION(0x1, "gpio_out"),
1053 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
1054 SUNXI_FUNCTION(0x3, "ts0"), /* D3 */
1055 SUNXI_FUNCTION(0x5, "keypad")), /* IN7 */
1056 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8,
1057 SUNXI_FUNCTION(0x0, "gpio_in"),
1058 SUNXI_FUNCTION(0x1, "gpio_out"),
1059 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
1060 SUNXI_FUNCTION(0x3, "ts0"), /* D4 */
1061 SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
1062 SUNXI_FUNCTION(0x5, "keypad")), /* OUT0 */
1063 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9,
1064 SUNXI_FUNCTION(0x0, "gpio_in"),
1065 SUNXI_FUNCTION(0x1, "gpio_out"),
1066 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
1067 SUNXI_FUNCTION(0x3, "ts0"), /* D5 */
1068 SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
1069 SUNXI_FUNCTION(0x5, "keypad")), /* OUT1 */
1070 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10,
1071 SUNXI_FUNCTION(0x0, "gpio_in"),
1072 SUNXI_FUNCTION(0x1, "gpio_out"),
1073 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
1074 SUNXI_FUNCTION(0x3, "ts0"), /* D6 */
1075 SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
1076 SUNXI_FUNCTION(0x5, "keypad")), /* OUT2 */
1077 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11,
1078 SUNXI_FUNCTION(0x0, "gpio_in"),
1079 SUNXI_FUNCTION(0x1, "gpio_out"),
1080 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
1081 SUNXI_FUNCTION(0x3, "ts0"), /* D7 */
1082 SUNXI_FUNCTION(0x4, "uart1"), /* RING */
1083 SUNXI_FUNCTION(0x5, "keypad")), /* OUT3 */
1084 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12,
1085 SUNXI_FUNCTION(0x0, "gpio_in"),
1086 SUNXI_FUNCTION(0x1, "gpio_out"),
1087 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */
1088 SUNXI_FUNCTION(0x3, "uart1"), /* TX */
1089 SUNXI_FUNCTION(0x5, "keypad")), /* OUT4 */
1090 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13,
1091 SUNXI_FUNCTION(0x0, "gpio_in"),
1092 SUNXI_FUNCTION(0x1, "gpio_out"),
1093 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */
1094 SUNXI_FUNCTION(0x3, "uart1"), /* RX */
1095 SUNXI_FUNCTION(0x5, "keypad")), /* OUT5 */
1096 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14,
1097 SUNXI_FUNCTION(0x0, "gpio_in"),
1098 SUNXI_FUNCTION(0x1, "gpio_out"),
1099 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */
1100 SUNXI_FUNCTION(0x3, "uart1"), /* CTS */
1101 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
1102 SUNXI_FUNCTION(0x5, "keypad")), /* OUT6 */
1103 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15,
1104 SUNXI_FUNCTION(0x0, "gpio_in"),
1105 SUNXI_FUNCTION(0x1, "gpio_out"),
1106 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */
1107 SUNXI_FUNCTION(0x3, "uart1"), /* RTS */
1108 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
1109 SUNXI_FUNCTION(0x5, "keypad")), /* OUT7 */
1110 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16,
1111 SUNXI_FUNCTION(0x0, "gpio_in"),
1112 SUNXI_FUNCTION(0x1, "gpio_out"),
1113 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */
1114 SUNXI_FUNCTION(0x3, "uart2")), /* TX */
1115 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17,
1116 SUNXI_FUNCTION(0x0, "gpio_in"),
1117 SUNXI_FUNCTION(0x1, "gpio_out"),
1118 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */
1119 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
1120 SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */
1121 /* Hole */
1122 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
1123 SUNXI_FUNCTION(0x0, "gpio_in"),
1124 SUNXI_FUNCTION(0x1, "gpio_out"),
1125 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
1126 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
1127 SUNXI_FUNCTION(0x0, "gpio_in"),
1128 SUNXI_FUNCTION(0x1, "gpio_out"),
1129 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
1130 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
1131 SUNXI_FUNCTION(0x0, "gpio_in"),
1132 SUNXI_FUNCTION(0x1, "gpio_out"),
1133 SUNXI_FUNCTION(0x2, "pwm"), /* PWM0 */
1134 SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */
1135 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
1136 SUNXI_FUNCTION(0x0, "gpio_in"),
1137 SUNXI_FUNCTION(0x1, "gpio_out"),
1138 SUNXI_FUNCTION(0x2, "ir0"), /* TX */
1139 SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */
1140 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
1141 SUNXI_FUNCTION(0x0, "gpio_in"),
1142 SUNXI_FUNCTION(0x1, "gpio_out"),
1143 SUNXI_FUNCTION(0x2, "ir0"), /* RX */
1144 SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */
1145 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5,
1146 SUNXI_FUNCTION(0x0, "gpio_in"),
1147 SUNXI_FUNCTION(0x1, "gpio_out"),
1148 SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
1149 SUNXI_FUNCTION_IRQ(0x6, 19)), /* EINT19 */
1150 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6,
1151 SUNXI_FUNCTION(0x0, "gpio_in"),
1152 SUNXI_FUNCTION(0x1, "gpio_out"),
1153 SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */
1154 SUNXI_FUNCTION_IRQ(0x6, 20)), /* EINT20 */
1155 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7,
1156 SUNXI_FUNCTION(0x0, "gpio_in"),
1157 SUNXI_FUNCTION(0x1, "gpio_out"),
1158 SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */
1159 SUNXI_FUNCTION_IRQ(0x6, 21)), /* EINT21 */
1160 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8,
1161 SUNXI_FUNCTION(0x0, "gpio_in"),
1162 SUNXI_FUNCTION(0x1, "gpio_out"),
1163 SUNXI_FUNCTION(0x2, "i2s"), /* DO */
1164 SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */
1165 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9,
1166 SUNXI_FUNCTION(0x0, "gpio_in"),
1167 SUNXI_FUNCTION(0x1, "gpio_out"),
1168 SUNXI_FUNCTION(0x2, "i2s"), /* DI */
1169 SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */
1170 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
1171 SUNXI_FUNCTION(0x0, "gpio_in"),
1172 SUNXI_FUNCTION(0x1, "gpio_out"),
1173 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
1174 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
1175 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11,
1176 SUNXI_FUNCTION(0x0, "gpio_in"),
1177 SUNXI_FUNCTION(0x1, "gpio_out"),
1178 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
1179 SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
1180 SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */
1181 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12,
1182 SUNXI_FUNCTION(0x0, "gpio_in"),
1183 SUNXI_FUNCTION(0x1, "gpio_out"),
1184 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
1185 SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
1186 SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */
1187 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13,
1188 SUNXI_FUNCTION(0x0, "gpio_in"),
1189 SUNXI_FUNCTION(0x1, "gpio_out"),
1190 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
1191 SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
1192 SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */
1193 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14,
1194 SUNXI_FUNCTION(0x0, "gpio_in"),
1195 SUNXI_FUNCTION(0x1, "gpio_out"),
1196 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
1197 SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
1198 SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */
1199 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
1200 SUNXI_FUNCTION(0x0, "gpio_in"),
1201 SUNXI_FUNCTION(0x1, "gpio_out"),
1202 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
1203 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
1204 SUNXI_FUNCTION(0x0, "gpio_in"),
1205 SUNXI_FUNCTION(0x1, "gpio_out"),
1206 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
1207 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
1208 SUNXI_FUNCTION(0x0, "gpio_in"),
1209 SUNXI_FUNCTION(0x1, "gpio_out"),
1210 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
1211 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
1212 SUNXI_FUNCTION(0x0, "gpio_in"),
1213 SUNXI_FUNCTION(0x1, "gpio_out"),
1214 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
1215 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19,
1216 SUNXI_FUNCTION(0x0, "gpio_in"),
1217 SUNXI_FUNCTION(0x1, "gpio_out"),
1218 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
1219 SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */
1220 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20,
1221 SUNXI_FUNCTION(0x0, "gpio_in"),
1222 SUNXI_FUNCTION(0x1, "gpio_out"),
1223 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
1224 SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */
1225 /* Hole */
1226 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
1227 SUNXI_FUNCTION(0x0, "gpio_in"),
1228 SUNXI_FUNCTION(0x1, "gpio_out"),
1229 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
1230 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
1231 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
1232 SUNXI_FUNCTION(0x0, "gpio_in"),
1233 SUNXI_FUNCTION(0x1, "gpio_out"),
1234 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
1235 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
1236 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
1237 SUNXI_FUNCTION(0x0, "gpio_in"),
1238 SUNXI_FUNCTION(0x1, "gpio_out"),
1239 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
1240 SUNXI_FUNCTION(0x3, "spi0")), /* SCK */
1241 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
1242 SUNXI_FUNCTION(0x0, "gpio_in"),
1243 SUNXI_FUNCTION(0x1, "gpio_out"),
1244 SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
1245 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
1246 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
1247 SUNXI_FUNCTION(0x0, "gpio_in"),
1248 SUNXI_FUNCTION(0x1, "gpio_out"),
1249 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
1250 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
1251 SUNXI_FUNCTION(0x0, "gpio_in"),
1252 SUNXI_FUNCTION(0x1, "gpio_out"),
1253 SUNXI_FUNCTION(0x2, "nand0")), /* NRE */
1254 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
1255 SUNXI_FUNCTION(0x0, "gpio_in"),
1256 SUNXI_FUNCTION(0x1, "gpio_out"),
1257 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
1258 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
1259 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
1260 SUNXI_FUNCTION(0x0, "gpio_in"),
1261 SUNXI_FUNCTION(0x1, "gpio_out"),
1262 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
1263 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
1264 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
1265 SUNXI_FUNCTION(0x0, "gpio_in"),
1266 SUNXI_FUNCTION(0x1, "gpio_out"),
1267 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
1268 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
1269 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
1270 SUNXI_FUNCTION(0x0, "gpio_in"),
1271 SUNXI_FUNCTION(0x1, "gpio_out"),
1272 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
1273 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
1274 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
1275 SUNXI_FUNCTION(0x0, "gpio_in"),
1276 SUNXI_FUNCTION(0x1, "gpio_out"),
1277 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
1278 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
1279 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
1280 SUNXI_FUNCTION(0x0, "gpio_in"),
1281 SUNXI_FUNCTION(0x1, "gpio_out"),
1282 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
1283 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
1284 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
1285 SUNXI_FUNCTION(0x0, "gpio_in"),
1286 SUNXI_FUNCTION(0x1, "gpio_out"),
1287 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
1288 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
1289 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
1290 SUNXI_FUNCTION(0x0, "gpio_in"),
1291 SUNXI_FUNCTION(0x1, "gpio_out"),
1292 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
1293 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
1294 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
1295 SUNXI_FUNCTION(0x0, "gpio_in"),
1296 SUNXI_FUNCTION(0x1, "gpio_out"),
1297 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
1298 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
1299 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
1300 SUNXI_FUNCTION(0x0, "gpio_in"),
1301 SUNXI_FUNCTION(0x1, "gpio_out"),
1302 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
1303 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
1304 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16,
1305 SUNXI_FUNCTION(0x0, "gpio_in"),
1306 SUNXI_FUNCTION(0x1, "gpio_out"),
1307 SUNXI_FUNCTION(0x2, "nand0"), /* NWP */
1308 SUNXI_FUNCTION(0x4, "uart3")), /* TX */
1309 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17,
1310 SUNXI_FUNCTION(0x0, "gpio_in"),
1311 SUNXI_FUNCTION(0x1, "gpio_out"),
1312 SUNXI_FUNCTION(0x2, "nand0"), /* NCE2 */
1313 SUNXI_FUNCTION(0x4, "uart3")), /* RX */
1314 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18,
1315 SUNXI_FUNCTION(0x0, "gpio_in"),
1316 SUNXI_FUNCTION(0x1, "gpio_out"),
1317 SUNXI_FUNCTION(0x2, "nand0"), /* NCE3 */
1318 SUNXI_FUNCTION(0x3, "uart2"), /* TX */
1319 SUNXI_FUNCTION(0x4, "uart3")), /* CTS */
1320 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
1321 SUNXI_FUNCTION(0x0, "gpio_in"),
1322 SUNXI_FUNCTION(0x1, "gpio_out"),
1323 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
1324 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
1325 SUNXI_FUNCTION(0x4, "uart3")), /* RTS */
1326 /* Hole */
1327 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0,
1328 SUNXI_FUNCTION(0x0, "gpio_in"),
1329 SUNXI_FUNCTION(0x1, "gpio_out"),
1330 SUNXI_FUNCTION(0x2, "lcd0")), /* D0 */
1331 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1,
1332 SUNXI_FUNCTION(0x0, "gpio_in"),
1333 SUNXI_FUNCTION(0x1, "gpio_out"),
1334 SUNXI_FUNCTION(0x2, "lcd0")), /* D1 */
1335 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
1336 SUNXI_FUNCTION(0x0, "gpio_in"),
1337 SUNXI_FUNCTION(0x1, "gpio_out"),
1338 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
1339 SUNXI_FUNCTION(0x3, "uart2")), /* TX */
1340 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
1341 SUNXI_FUNCTION(0x0, "gpio_in"),
1342 SUNXI_FUNCTION(0x1, "gpio_out"),
1343 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
1344 SUNXI_FUNCTION(0x3, "uart2")), /* RX */
1345 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
1346 SUNXI_FUNCTION(0x0, "gpio_in"),
1347 SUNXI_FUNCTION(0x1, "gpio_out"),
1348 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
1349 SUNXI_FUNCTION(0x3, "uart2")), /* CTS */
1350 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
1351 SUNXI_FUNCTION(0x0, "gpio_in"),
1352 SUNXI_FUNCTION(0x1, "gpio_out"),
1353 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
1354 SUNXI_FUNCTION(0x3, "uart2")), /* RTS */
1355 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
1356 SUNXI_FUNCTION(0x0, "gpio_in"),
1357 SUNXI_FUNCTION(0x1, "gpio_out"),
1358 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
1359 SUNXI_FUNCTION(0x3, "emac")), /* ECRS */
1360 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
1361 SUNXI_FUNCTION(0x0, "gpio_in"),
1362 SUNXI_FUNCTION(0x1, "gpio_out"),
1363 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
1364 SUNXI_FUNCTION(0x3, "emac")), /* ECOL */
1365 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8,
1366 SUNXI_FUNCTION(0x0, "gpio_in"),
1367 SUNXI_FUNCTION(0x1, "gpio_out"),
1368 SUNXI_FUNCTION(0x2, "lcd0")), /* D8 */
1369 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9,
1370 SUNXI_FUNCTION(0x0, "gpio_in"),
1371 SUNXI_FUNCTION(0x1, "gpio_out"),
1372 SUNXI_FUNCTION(0x2, "lcd0")), /* D9 */
1373 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
1374 SUNXI_FUNCTION(0x0, "gpio_in"),
1375 SUNXI_FUNCTION(0x1, "gpio_out"),
1376 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
1377 SUNXI_FUNCTION(0x3, "emac")), /* ERXD0 */
1378 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
1379 SUNXI_FUNCTION(0x0, "gpio_in"),
1380 SUNXI_FUNCTION(0x1, "gpio_out"),
1381 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
1382 SUNXI_FUNCTION(0x3, "emac")), /* ERXD1 */
1383 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
1384 SUNXI_FUNCTION(0x0, "gpio_in"),
1385 SUNXI_FUNCTION(0x1, "gpio_out"),
1386 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
1387 SUNXI_FUNCTION(0x3, "emac")), /* ERXD2 */
1388 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
1389 SUNXI_FUNCTION(0x0, "gpio_in"),
1390 SUNXI_FUNCTION(0x1, "gpio_out"),
1391 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
1392 SUNXI_FUNCTION(0x3, "emac")), /* ERXD3 */
1393 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
1394 SUNXI_FUNCTION(0x0, "gpio_in"),
1395 SUNXI_FUNCTION(0x1, "gpio_out"),
1396 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
1397 SUNXI_FUNCTION(0x3, "emac")), /* ERXCK */
1398 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
1399 SUNXI_FUNCTION(0x0, "gpio_in"),
1400 SUNXI_FUNCTION(0x1, "gpio_out"),
1401 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
1402 SUNXI_FUNCTION(0x3, "emac")), /* ERXERR */
1403 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16,
1404 SUNXI_FUNCTION(0x0, "gpio_in"),
1405 SUNXI_FUNCTION(0x1, "gpio_out"),
1406 SUNXI_FUNCTION(0x2, "lcd0")), /* D16 */
1407 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17,
1408 SUNXI_FUNCTION(0x0, "gpio_in"),
1409 SUNXI_FUNCTION(0x1, "gpio_out"),
1410 SUNXI_FUNCTION(0x2, "lcd0")), /* D17 */
1411 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
1412 SUNXI_FUNCTION(0x0, "gpio_in"),
1413 SUNXI_FUNCTION(0x1, "gpio_out"),
1414 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
1415 SUNXI_FUNCTION(0x3, "emac")), /* ERXDV */
1416 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
1417 SUNXI_FUNCTION(0x0, "gpio_in"),
1418 SUNXI_FUNCTION(0x1, "gpio_out"),
1419 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
1420 SUNXI_FUNCTION(0x3, "emac")), /* ETXD0 */
1421 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
1422 SUNXI_FUNCTION(0x0, "gpio_in"),
1423 SUNXI_FUNCTION(0x1, "gpio_out"),
1424 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
1425 SUNXI_FUNCTION(0x3, "emac")), /* ETXD1 */
1426 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
1427 SUNXI_FUNCTION(0x0, "gpio_in"),
1428 SUNXI_FUNCTION(0x1, "gpio_out"),
1429 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
1430 SUNXI_FUNCTION(0x3, "emac")), /* ETXD2 */
1431 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
1432 SUNXI_FUNCTION(0x0, "gpio_in"),
1433 SUNXI_FUNCTION(0x1, "gpio_out"),
1434 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
1435 SUNXI_FUNCTION(0x3, "emac")), /* ETXD3 */
1436 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
1437 SUNXI_FUNCTION(0x0, "gpio_in"),
1438 SUNXI_FUNCTION(0x1, "gpio_out"),
1439 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
1440 SUNXI_FUNCTION(0x3, "emac")), /* ETXEN */
1441 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
1442 SUNXI_FUNCTION(0x0, "gpio_in"),
1443 SUNXI_FUNCTION(0x1, "gpio_out"),
1444 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
1445 SUNXI_FUNCTION(0x3, "emac")), /* ETXCK */
1446 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
1447 SUNXI_FUNCTION(0x0, "gpio_in"),
1448 SUNXI_FUNCTION(0x1, "gpio_out"),
1449 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
1450 SUNXI_FUNCTION(0x3, "emac")), /* ETXERR */
1451 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
1452 SUNXI_FUNCTION(0x0, "gpio_in"),
1453 SUNXI_FUNCTION(0x1, "gpio_out"),
1454 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
1455 SUNXI_FUNCTION(0x3, "emac")), /* EMDC */
1456 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
1457 SUNXI_FUNCTION(0x0, "gpio_in"),
1458 SUNXI_FUNCTION(0x1, "gpio_out"),
1459 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
1460 SUNXI_FUNCTION(0x3, "emac")), /* EMDIO */
1461 /* Hole */
1462 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
1463 SUNXI_FUNCTION(0x0, "gpio_in"),
1464 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
1465 SUNXI_FUNCTION(0x3, "csi0"), /* PCK */
1466 SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */
1467 SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
1468 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
1469 SUNXI_FUNCTION(0x0, "gpio_in"),
1470 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
1471 SUNXI_FUNCTION(0x3, "csi0"), /* CK */
1472 SUNXI_FUNCTION(0x4, "spi2"), /* CLK */
1473 SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
1474 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
1475 SUNXI_FUNCTION(0x0, "gpio_in"),
1476 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
1477 SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */
1478 SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */
1479 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
1480 SUNXI_FUNCTION(0x0, "gpio_in"),
1481 SUNXI_FUNCTION(0x1, "gpio_out"),
1482 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
1483 SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */
1484 SUNXI_FUNCTION(0x4, "spi2")), /* MISO */
1485 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
1486 SUNXI_FUNCTION(0x0, "gpio_in"),
1487 SUNXI_FUNCTION(0x1, "gpio_out"),
1488 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
1489 SUNXI_FUNCTION(0x3, "csi0"), /* D0 */
1490 SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */
1491 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
1492 SUNXI_FUNCTION(0x0, "gpio_in"),
1493 SUNXI_FUNCTION(0x1, "gpio_out"),
1494 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
1495 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
1496 SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */
1497 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
1498 SUNXI_FUNCTION(0x0, "gpio_in"),
1499 SUNXI_FUNCTION(0x1, "gpio_out"),
1500 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
1501 SUNXI_FUNCTION(0x3, "csi0"), /* D2 */
1502 SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */
1503 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
1504 SUNXI_FUNCTION(0x0, "gpio_in"),
1505 SUNXI_FUNCTION(0x1, "gpio_out"),
1506 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
1507 SUNXI_FUNCTION(0x3, "csi0"), /* D3 */
1508 SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */
1509 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
1510 SUNXI_FUNCTION(0x0, "gpio_in"),
1511 SUNXI_FUNCTION(0x1, "gpio_out"),
1512 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
1513 SUNXI_FUNCTION(0x3, "csi0"), /* D4 */
1514 SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */
1515 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
1516 SUNXI_FUNCTION(0x0, "gpio_in"),
1517 SUNXI_FUNCTION(0x1, "gpio_out"),
1518 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
1519 SUNXI_FUNCTION(0x3, "csi0"), /* D5 */
1520 SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */
1521 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
1522 SUNXI_FUNCTION(0x0, "gpio_in"),
1523 SUNXI_FUNCTION(0x1, "gpio_out"),
1524 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
1525 SUNXI_FUNCTION(0x3, "csi0"), /* D6 */
1526 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
1527 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
1528 SUNXI_FUNCTION(0x0, "gpio_in"),
1529 SUNXI_FUNCTION(0x1, "gpio_out"),
1530 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
1531 SUNXI_FUNCTION(0x3, "csi0"), /* D7 */
1532 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
1533 /* Hole */
1534 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
1535 SUNXI_FUNCTION(0x0, "gpio_in"),
1536 SUNXI_FUNCTION(0x1, "gpio_out"),
1537 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
1538 SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */
1539 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
1540 SUNXI_FUNCTION(0x0, "gpio_in"),
1541 SUNXI_FUNCTION(0x1, "gpio_out"),
1542 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
1543 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
1544 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
1545 SUNXI_FUNCTION(0x0, "gpio_in"),
1546 SUNXI_FUNCTION(0x1, "gpio_out"),
1547 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
1548 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
1549 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
1550 SUNXI_FUNCTION(0x0, "gpio_in"),
1551 SUNXI_FUNCTION(0x1, "gpio_out"),
1552 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
1553 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
1554 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
1555 SUNXI_FUNCTION(0x0, "gpio_in"),
1556 SUNXI_FUNCTION(0x1, "gpio_out"),
1557 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
1558 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
1559 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
1560 SUNXI_FUNCTION(0x0, "gpio_in"),
1561 SUNXI_FUNCTION(0x1, "gpio_out"),
1562 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
1563 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
1564 /* Hole */
1565 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
1566 SUNXI_FUNCTION(0x0, "gpio_in"),
1567 SUNXI_FUNCTION(0x2, "gps"), /* CLK */
1568 SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */
1569 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
1570 SUNXI_FUNCTION(0x0, "gpio_in"),
1571 SUNXI_FUNCTION(0x2, "gps"), /* SIGN */
1572 SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */
1573 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
1574 SUNXI_FUNCTION(0x0, "gpio_in"),
1575 SUNXI_FUNCTION(0x2, "gps"), /* MAG */
1576 SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */
1577 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
1578 SUNXI_FUNCTION(0x0, "gpio_in"),
1579 SUNXI_FUNCTION(0x1, "gpio_out"),
1580 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
1581 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
1582 SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */
1583 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
1584 SUNXI_FUNCTION(0x0, "gpio_in"),
1585 SUNXI_FUNCTION(0x1, "gpio_out"),
1586 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
1587 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
1588 SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */
1589 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5,
1590 SUNXI_FUNCTION(0x0, "gpio_in"),
1591 SUNXI_FUNCTION(0x1, "gpio_out"),
1592 SUNXI_FUNCTION(0x2, "mmc1"), /* DO */
1593 SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
1594 SUNXI_FUNCTION_IRQ(0x6, 5)), /* EINT5 */
1595 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6,
1596 SUNXI_FUNCTION(0x0, "gpio_in"),
1597 SUNXI_FUNCTION(0x1, "gpio_out"),
1598 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
1599 SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
1600 SUNXI_FUNCTION(0x5, "uart2"), /* RTS */
1601 SUNXI_FUNCTION_IRQ(0x6, 6)), /* EINT6 */
1602 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7,
1603 SUNXI_FUNCTION(0x0, "gpio_in"),
1604 SUNXI_FUNCTION(0x1, "gpio_out"),
1605 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
1606 SUNXI_FUNCTION(0x5, "uart2"), /* TX */
1607 SUNXI_FUNCTION_IRQ(0x6, 7)), /* EINT7 */
1608 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8,
1609 SUNXI_FUNCTION(0x0, "gpio_in"),
1610 SUNXI_FUNCTION(0x1, "gpio_out"),
1611 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
1612 SUNXI_FUNCTION(0x5, "uart2"), /* RX */
1613 SUNXI_FUNCTION_IRQ(0x6, 8)), /* EINT8 */
1614 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
1615 SUNXI_FUNCTION(0x0, "gpio_in"),
1616 SUNXI_FUNCTION(0x1, "gpio_out"),
1617 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
1618 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
1619 SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */
1620 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
1621 SUNXI_FUNCTION(0x0, "gpio_in"),
1622 SUNXI_FUNCTION(0x1, "gpio_out"),
1623 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
1624 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
1625 SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */
1626 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
1627 SUNXI_FUNCTION(0x0, "gpio_in"),
1628 SUNXI_FUNCTION(0x1, "gpio_out"),
1629 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
1630 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
1631 SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */
1632 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12,
1633 SUNXI_FUNCTION(0x0, "gpio_in"),
1634 SUNXI_FUNCTION(0x1, "gpio_out"),
1635 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
1636 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
1637 SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
1638 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG13,
1639 SUNXI_FUNCTION(0x0, "gpio_in"),
1640 SUNXI_FUNCTION(0x1, "gpio_out"),
1641 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
1642 SUNXI_FUNCTION(0x3, "uart3"), /* PWM1 */
1643 SUNXI_FUNCTION(0x5, "uart2"), /* CTS */
1644 SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */
1645};
1646
Maxime Ripard44abb932013-06-09 18:36:03 +0200[diff] [blame]1647static const struct sunxi_desc_pin sun5i_a13_pins[] = {
1648 /* Hole */
1649 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
1650 SUNXI_FUNCTION(0x0, "gpio_in"),
1651 SUNXI_FUNCTION(0x1, "gpio_out"),
1652 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
1653 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
1654 SUNXI_FUNCTION(0x0, "gpio_in"),
1655 SUNXI_FUNCTION(0x1, "gpio_out"),
1656 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
1657 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
1658 SUNXI_FUNCTION(0x0, "gpio_in"),
1659 SUNXI_FUNCTION(0x1, "gpio_out"),
1660 SUNXI_FUNCTION(0x2, "pwm"),
1661 SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */
1662 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
1663 SUNXI_FUNCTION(0x0, "gpio_in"),
1664 SUNXI_FUNCTION(0x1, "gpio_out"),
1665 SUNXI_FUNCTION(0x2, "ir0"), /* TX */
1666 SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */
1667 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
1668 SUNXI_FUNCTION(0x0, "gpio_in"),
1669 SUNXI_FUNCTION(0x1, "gpio_out"),
1670 SUNXI_FUNCTION(0x2, "ir0"), /* RX */
1671 SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */
1672 /* Hole */
1673 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
1674 SUNXI_FUNCTION(0x0, "gpio_in"),
1675 SUNXI_FUNCTION(0x1, "gpio_out"),
1676 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
1677 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
1678 /* Hole */
1679 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
1680 SUNXI_FUNCTION(0x0, "gpio_in"),
1681 SUNXI_FUNCTION(0x1, "gpio_out"),
1682 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
1683 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
1684 SUNXI_FUNCTION(0x0, "gpio_in"),
1685 SUNXI_FUNCTION(0x1, "gpio_out"),
1686 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
1687 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
1688 SUNXI_FUNCTION(0x0, "gpio_in"),
1689 SUNXI_FUNCTION(0x1, "gpio_out"),
1690 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
1691 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
1692 SUNXI_FUNCTION(0x0, "gpio_in"),
1693 SUNXI_FUNCTION(0x1, "gpio_out"),
1694 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
1695 /* Hole */
1696 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
1697 SUNXI_FUNCTION(0x0, "gpio_in"),
1698 SUNXI_FUNCTION(0x1, "gpio_out"),
1699 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
1700 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
1701 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
1702 SUNXI_FUNCTION(0x0, "gpio_in"),
1703 SUNXI_FUNCTION(0x1, "gpio_out"),
1704 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
1705 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
1706 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
1707 SUNXI_FUNCTION(0x0, "gpio_in"),
1708 SUNXI_FUNCTION(0x1, "gpio_out"),
1709 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
1710 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
1711 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
1712 SUNXI_FUNCTION(0x0, "gpio_in"),
1713 SUNXI_FUNCTION(0x1, "gpio_out"),
1714 SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
1715 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
1716 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
1717 SUNXI_FUNCTION(0x0, "gpio_in"),
1718 SUNXI_FUNCTION(0x1, "gpio_out"),
1719 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
1720 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
1721 SUNXI_FUNCTION(0x0, "gpio_in"),
1722 SUNXI_FUNCTION(0x1, "gpio_out"),
1723 SUNXI_FUNCTION(0x2, "nand0")), /* NRE */
1724 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
1725 SUNXI_FUNCTION(0x0, "gpio_in"),
1726 SUNXI_FUNCTION(0x1, "gpio_out"),
1727 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
1728 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
1729 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
1730 SUNXI_FUNCTION(0x0, "gpio_in"),
1731 SUNXI_FUNCTION(0x1, "gpio_out"),
1732 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
1733 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
1734 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
1735 SUNXI_FUNCTION(0x0, "gpio_in"),
1736 SUNXI_FUNCTION(0x1, "gpio_out"),
1737 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
1738 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
1739 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
1740 SUNXI_FUNCTION(0x0, "gpio_in"),
1741 SUNXI_FUNCTION(0x1, "gpio_out"),
1742 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
1743 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
1744 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
1745 SUNXI_FUNCTION(0x0, "gpio_in"),
1746 SUNXI_FUNCTION(0x1, "gpio_out"),
1747 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
1748 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
1749 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
1750 SUNXI_FUNCTION(0x0, "gpio_in"),
1751 SUNXI_FUNCTION(0x1, "gpio_out"),
1752 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
1753 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
1754 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
1755 SUNXI_FUNCTION(0x0, "gpio_in"),
1756 SUNXI_FUNCTION(0x1, "gpio_out"),
1757 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
1758 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
1759 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
1760 SUNXI_FUNCTION(0x0, "gpio_in"),
1761 SUNXI_FUNCTION(0x1, "gpio_out"),
1762 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
1763 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
1764 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
1765 SUNXI_FUNCTION(0x0, "gpio_in"),
1766 SUNXI_FUNCTION(0x1, "gpio_out"),
1767 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
1768 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
1769 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
1770 SUNXI_FUNCTION(0x0, "gpio_in"),
1771 SUNXI_FUNCTION(0x1, "gpio_out"),
1772 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
1773 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
1774 /* Hole */
1775 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
1776 SUNXI_FUNCTION(0x0, "gpio_in"),
1777 SUNXI_FUNCTION(0x1, "gpio_out"),
1778 SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */
1779 SUNXI_FUNCTION(0x4, "uart3")), /* RTS */
1780 /* Hole */
1781 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
1782 SUNXI_FUNCTION(0x0, "gpio_in"),
1783 SUNXI_FUNCTION(0x1, "gpio_out"),
1784 SUNXI_FUNCTION(0x2, "lcd0")), /* D2 */
1785 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
1786 SUNXI_FUNCTION(0x0, "gpio_in"),
1787 SUNXI_FUNCTION(0x1, "gpio_out"),
1788 SUNXI_FUNCTION(0x2, "lcd0")), /* D3 */
1789 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
1790 SUNXI_FUNCTION(0x0, "gpio_in"),
1791 SUNXI_FUNCTION(0x1, "gpio_out"),
1792 SUNXI_FUNCTION(0x2, "lcd0")), /* D4 */
1793 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
1794 SUNXI_FUNCTION(0x0, "gpio_in"),
1795 SUNXI_FUNCTION(0x1, "gpio_out"),
1796 SUNXI_FUNCTION(0x2, "lcd0")), /* D5 */
1797 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
1798 SUNXI_FUNCTION(0x0, "gpio_in"),
1799 SUNXI_FUNCTION(0x1, "gpio_out"),
1800 SUNXI_FUNCTION(0x2, "lcd0")), /* D6 */
1801 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
1802 SUNXI_FUNCTION(0x0, "gpio_in"),
1803 SUNXI_FUNCTION(0x1, "gpio_out"),
1804 SUNXI_FUNCTION(0x2, "lcd0")), /* D7 */
1805 /* Hole */
1806 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
1807 SUNXI_FUNCTION(0x0, "gpio_in"),
1808 SUNXI_FUNCTION(0x1, "gpio_out"),
1809 SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */
1810 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
1811 SUNXI_FUNCTION(0x0, "gpio_in"),
1812 SUNXI_FUNCTION(0x1, "gpio_out"),
1813 SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */
1814 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
1815 SUNXI_FUNCTION(0x0, "gpio_in"),
1816 SUNXI_FUNCTION(0x1, "gpio_out"),
1817 SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */
1818 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
1819 SUNXI_FUNCTION(0x0, "gpio_in"),
1820 SUNXI_FUNCTION(0x1, "gpio_out"),
1821 SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */
1822 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
1823 SUNXI_FUNCTION(0x0, "gpio_in"),
1824 SUNXI_FUNCTION(0x1, "gpio_out"),
1825 SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */
1826 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
1827 SUNXI_FUNCTION(0x0, "gpio_in"),
1828 SUNXI_FUNCTION(0x1, "gpio_out"),
1829 SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */
1830 /* Hole */
1831 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
1832 SUNXI_FUNCTION(0x0, "gpio_in"),
1833 SUNXI_FUNCTION(0x1, "gpio_out"),
1834 SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */
1835 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
1836 SUNXI_FUNCTION(0x0, "gpio_in"),
1837 SUNXI_FUNCTION(0x1, "gpio_out"),
1838 SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */
1839 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
1840 SUNXI_FUNCTION(0x0, "gpio_in"),
1841 SUNXI_FUNCTION(0x1, "gpio_out"),
1842 SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
1843 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
1844 SUNXI_FUNCTION(0x0, "gpio_in"),
1845 SUNXI_FUNCTION(0x1, "gpio_out"),
1846 SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
1847 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
1848 SUNXI_FUNCTION(0x0, "gpio_in"),
1849 SUNXI_FUNCTION(0x1, "gpio_out"),
1850 SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
1851 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
1852 SUNXI_FUNCTION(0x0, "gpio_in"),
1853 SUNXI_FUNCTION(0x1, "gpio_out"),
1854 SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
1855 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
1856 SUNXI_FUNCTION(0x0, "gpio_in"),
1857 SUNXI_FUNCTION(0x1, "gpio_out"),
1858 SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
1859 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
1860 SUNXI_FUNCTION(0x0, "gpio_in"),
1861 SUNXI_FUNCTION(0x1, "gpio_out"),
1862 SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
1863 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
1864 SUNXI_FUNCTION(0x0, "gpio_in"),
1865 SUNXI_FUNCTION(0x1, "gpio_out"),
1866 SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
1867 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
1868 SUNXI_FUNCTION(0x0, "gpio_in"),
1869 SUNXI_FUNCTION(0x1, "gpio_out"),
1870 SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
1871 /* Hole */
1872 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
1873 SUNXI_FUNCTION(0x0, "gpio_in"),
1874 SUNXI_FUNCTION(0x3, "csi0"), /* PCLK */
1875 SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */
1876 SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
1877 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
1878 SUNXI_FUNCTION(0x0, "gpio_in"),
1879 SUNXI_FUNCTION(0x3, "csi0"), /* MCLK */
1880 SUNXI_FUNCTION(0x4, "spi2"), /* CLK */
1881 SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
1882 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
1883 SUNXI_FUNCTION(0x0, "gpio_in"),
1884 SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */
1885 SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */
1886 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
1887 SUNXI_FUNCTION(0x0, "gpio_in"),
1888 SUNXI_FUNCTION(0x1, "gpio_out"),
1889 SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */
1890 SUNXI_FUNCTION(0x4, "spi2")), /* MISO */
1891 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
1892 SUNXI_FUNCTION(0x0, "gpio_in"),
1893 SUNXI_FUNCTION(0x1, "gpio_out"),
1894 SUNXI_FUNCTION(0x3, "csi0"), /* D0 */
1895 SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */
1896 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
1897 SUNXI_FUNCTION(0x0, "gpio_in"),
1898 SUNXI_FUNCTION(0x1, "gpio_out"),
1899 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
1900 SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */
1901 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
1902 SUNXI_FUNCTION(0x0, "gpio_in"),
1903 SUNXI_FUNCTION(0x1, "gpio_out"),
1904 SUNXI_FUNCTION(0x3, "csi0"), /* D2 */
1905 SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */
1906 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
1907 SUNXI_FUNCTION(0x0, "gpio_in"),
1908 SUNXI_FUNCTION(0x1, "gpio_out"),
1909 SUNXI_FUNCTION(0x3, "csi0"), /* D3 */
1910 SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */
1911 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
1912 SUNXI_FUNCTION(0x0, "gpio_in"),
1913 SUNXI_FUNCTION(0x1, "gpio_out"),
1914 SUNXI_FUNCTION(0x3, "csi0"), /* D4 */
1915 SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */
1916 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
1917 SUNXI_FUNCTION(0x0, "gpio_in"),
1918 SUNXI_FUNCTION(0x1, "gpio_out"),
1919 SUNXI_FUNCTION(0x3, "csi0"), /* D5 */
1920 SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */
1921 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
1922 SUNXI_FUNCTION(0x0, "gpio_in"),
1923 SUNXI_FUNCTION(0x1, "gpio_out"),
1924 SUNXI_FUNCTION(0x3, "csi0"), /* D6 */
1925 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
1926 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
1927 SUNXI_FUNCTION(0x0, "gpio_in"),
1928 SUNXI_FUNCTION(0x1, "gpio_out"),
1929 SUNXI_FUNCTION(0x3, "csi0"), /* D7 */
1930 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
1931 /* Hole */
1932 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
1933 SUNXI_FUNCTION(0x0, "gpio_in"),
1934 SUNXI_FUNCTION(0x1, "gpio_out"),
1935 SUNXI_FUNCTION(0x4, "mmc0")), /* D1 */
1936 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
1937 SUNXI_FUNCTION(0x0, "gpio_in"),
1938 SUNXI_FUNCTION(0x1, "gpio_out"),
1939 SUNXI_FUNCTION(0x4, "mmc0")), /* D0 */
1940 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
1941 SUNXI_FUNCTION(0x0, "gpio_in"),
1942 SUNXI_FUNCTION(0x1, "gpio_out"),
1943 SUNXI_FUNCTION(0x4, "mmc0")), /* CLK */
1944 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
1945 SUNXI_FUNCTION(0x0, "gpio_in"),
1946 SUNXI_FUNCTION(0x1, "gpio_out"),
1947 SUNXI_FUNCTION(0x4, "mmc0")), /* CMD */
1948 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
1949 SUNXI_FUNCTION(0x0, "gpio_in"),
1950 SUNXI_FUNCTION(0x1, "gpio_out"),
1951 SUNXI_FUNCTION(0x4, "mmc0")), /* D3 */
1952 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
1953 SUNXI_FUNCTION(0x0, "gpio_in"),
1954 SUNXI_FUNCTION(0x1, "gpio_out"),
1955 SUNXI_FUNCTION(0x4, "mmc0")), /* D2 */
1956 /* Hole */
1957 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
1958 SUNXI_FUNCTION(0x0, "gpio_in"),
1959 SUNXI_FUNCTION(0x1, "gpio_out"),
1960 SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */
1961 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
1962 SUNXI_FUNCTION(0x0, "gpio_in"),
1963 SUNXI_FUNCTION(0x1, "gpio_out"),
1964 SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */
1965 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
1966 SUNXI_FUNCTION(0x0, "gpio_in"),
1967 SUNXI_FUNCTION(0x1, "gpio_out"),
1968 SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */
1969 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
1970 SUNXI_FUNCTION(0x0, "gpio_in"),
1971 SUNXI_FUNCTION(0x1, "gpio_out"),
1972 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
1973 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
1974 SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */
1975 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
1976 SUNXI_FUNCTION(0x0, "gpio_in"),
1977 SUNXI_FUNCTION(0x1, "gpio_out"),
1978 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
1979 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
1980 SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */
1981 /* Hole */
1982 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
1983 SUNXI_FUNCTION(0x0, "gpio_in"),
1984 SUNXI_FUNCTION(0x1, "gpio_out"),
1985 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
1986 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
1987 SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */
1988 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
1989 SUNXI_FUNCTION(0x0, "gpio_in"),
1990 SUNXI_FUNCTION(0x1, "gpio_out"),
1991 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
1992 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
1993 SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */
1994 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
1995 SUNXI_FUNCTION(0x0, "gpio_in"),
1996 SUNXI_FUNCTION(0x1, "gpio_out"),
1997 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
1998 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
1999 SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */
2000 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12,
2001 SUNXI_FUNCTION(0x0, "gpio_in"),
2002 SUNXI_FUNCTION(0x1, "gpio_out"),
2003 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
2004 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
2005 SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
2006};
2007
Maxime Ripardde0c9022013-08-04 11:47:34 +0200[diff] [blame]2008static const struct sunxi_desc_pin sun6i_a31_pins[] = {
2009 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
2010 SUNXI_FUNCTION(0x0, "gpio_in"),
2011 SUNXI_FUNCTION(0x1, "gpio_out"),
2012 SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */
2013 SUNXI_FUNCTION(0x3, "lcd1"), /* D0 */
2014 SUNXI_FUNCTION(0x4, "uart1")), /* DTR */
2015 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1,
2016 SUNXI_FUNCTION(0x0, "gpio_in"),
2017 SUNXI_FUNCTION(0x1, "gpio_out"),
2018 SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */
2019 SUNXI_FUNCTION(0x3, "lcd1"), /* D1 */
2020 SUNXI_FUNCTION(0x4, "uart1")), /* DSR */
2021 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2,
2022 SUNXI_FUNCTION(0x0, "gpio_in"),
2023 SUNXI_FUNCTION(0x1, "gpio_out"),
2024 SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */
2025 SUNXI_FUNCTION(0x3, "lcd1"), /* D2 */
2026 SUNXI_FUNCTION(0x4, "uart1")), /* DCD */
2027 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3,
2028 SUNXI_FUNCTION(0x0, "gpio_in"),
2029 SUNXI_FUNCTION(0x1, "gpio_out"),
2030 SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */
2031 SUNXI_FUNCTION(0x3, "lcd1"), /* D3 */
2032 SUNXI_FUNCTION(0x4, "uart1")), /* RING */
2033 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4,
2034 SUNXI_FUNCTION(0x0, "gpio_in"),
2035 SUNXI_FUNCTION(0x1, "gpio_out"),
2036 SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */
2037 SUNXI_FUNCTION(0x3, "lcd1"), /* D4 */
2038 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
2039 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5,
2040 SUNXI_FUNCTION(0x0, "gpio_in"),
2041 SUNXI_FUNCTION(0x1, "gpio_out"),
2042 SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */
2043 SUNXI_FUNCTION(0x3, "lcd1"), /* D5 */
2044 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
2045 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6,
2046 SUNXI_FUNCTION(0x0, "gpio_in"),
2047 SUNXI_FUNCTION(0x1, "gpio_out"),
2048 SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */
2049 SUNXI_FUNCTION(0x3, "lcd1"), /* D6 */
2050 SUNXI_FUNCTION(0x4, "uart1")), /* RTS */
2051 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7,
2052 SUNXI_FUNCTION(0x0, "gpio_in"),
2053 SUNXI_FUNCTION(0x1, "gpio_out"),
2054 SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */
2055 SUNXI_FUNCTION(0x3, "lcd1"), /* D7 */
2056 SUNXI_FUNCTION(0x4, "uart1")), /* CTS */
2057 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8,
2058 SUNXI_FUNCTION(0x0, "gpio_in"),
2059 SUNXI_FUNCTION(0x1, "gpio_out"),
2060 SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */
2061 SUNXI_FUNCTION(0x3, "lcd1")), /* D8 */
2062 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9,
2063 SUNXI_FUNCTION(0x0, "gpio_in"),
2064 SUNXI_FUNCTION(0x1, "gpio_out"),
2065 SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */
2066 SUNXI_FUNCTION(0x3, "lcd1"), /* D9 */
2067 SUNXI_FUNCTION(0x4, "mmc3"), /* CMD */
2068 SUNXI_FUNCTION(0x5, "mmc2")), /* CMD */
2069 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10,
2070 SUNXI_FUNCTION(0x0, "gpio_in"),
2071 SUNXI_FUNCTION(0x1, "gpio_out"),
2072 SUNXI_FUNCTION(0x2, "gmac"), /* GTXCLK */
2073 SUNXI_FUNCTION(0x3, "lcd1"), /* D10 */
2074 SUNXI_FUNCTION(0x4, "mmc3"), /* CLK */
2075 SUNXI_FUNCTION(0x5, "mmc2")), /* CLK */
2076 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11,
2077 SUNXI_FUNCTION(0x0, "gpio_in"),
2078 SUNXI_FUNCTION(0x1, "gpio_out"),
2079 SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */
2080 SUNXI_FUNCTION(0x3, "lcd1"), /* D11 */
2081 SUNXI_FUNCTION(0x4, "mmc3"), /* D0 */
2082 SUNXI_FUNCTION(0x5, "mmc2")), /* D0 */
2083 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12,
2084 SUNXI_FUNCTION(0x0, "gpio_in"),
2085 SUNXI_FUNCTION(0x1, "gpio_out"),
2086 SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */
2087 SUNXI_FUNCTION(0x3, "lcd1"), /* D12 */
2088 SUNXI_FUNCTION(0x4, "mmc3"), /* D1 */
2089 SUNXI_FUNCTION(0x5, "mmc2")), /* D1 */
2090 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13,
2091 SUNXI_FUNCTION(0x0, "gpio_in"),
2092 SUNXI_FUNCTION(0x1, "gpio_out"),
2093 SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */
2094 SUNXI_FUNCTION(0x3, "lcd1"), /* D13 */
2095 SUNXI_FUNCTION(0x4, "mmc3"), /* D2 */
2096 SUNXI_FUNCTION(0x5, "mmc2")), /* D2 */
2097 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14,
2098 SUNXI_FUNCTION(0x0, "gpio_in"),
2099 SUNXI_FUNCTION(0x1, "gpio_out"),
2100 SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */
2101 SUNXI_FUNCTION(0x3, "lcd1"), /* D14 */
2102 SUNXI_FUNCTION(0x4, "mmc3"), /* D3 */
2103 SUNXI_FUNCTION(0x5, "mmc2")), /* D3 */
2104 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15,
2105 SUNXI_FUNCTION(0x0, "gpio_in"),
2106 SUNXI_FUNCTION(0x1, "gpio_out"),
2107 SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */
2108 SUNXI_FUNCTION(0x3, "lcd1")), /* D15 */
2109 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16,
2110 SUNXI_FUNCTION(0x0, "gpio_in"),
2111 SUNXI_FUNCTION(0x1, "gpio_out"),
2112 SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */
2113 SUNXI_FUNCTION(0x3, "lcd1")), /* D16 */
2114 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17,
2115 SUNXI_FUNCTION(0x0, "gpio_in"),
2116 SUNXI_FUNCTION(0x1, "gpio_out"),
2117 SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */
2118 SUNXI_FUNCTION(0x3, "lcd1")), /* D17 */
2119 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA18,
2120 SUNXI_FUNCTION(0x0, "gpio_in"),
2121 SUNXI_FUNCTION(0x1, "gpio_out"),
2122 SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */
2123 SUNXI_FUNCTION(0x3, "lcd1")), /* D18 */
2124 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA19,
2125 SUNXI_FUNCTION(0x0, "gpio_in"),
2126 SUNXI_FUNCTION(0x1, "gpio_out"),
2127 SUNXI_FUNCTION(0x2, "gmac"), /* RXDV */
2128 SUNXI_FUNCTION(0x3, "lcd1"), /* D19 */
2129 SUNXI_FUNCTION(0x4, "pwm3")), /* Positive */
2130 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA20,
2131 SUNXI_FUNCTION(0x0, "gpio_in"),
2132 SUNXI_FUNCTION(0x1, "gpio_out"),
2133 SUNXI_FUNCTION(0x2, "gmac"), /* RXCLK */
2134 SUNXI_FUNCTION(0x3, "lcd1"), /* D20 */
2135 SUNXI_FUNCTION(0x4, "pwm3")), /* Negative */
2136 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA21,
2137 SUNXI_FUNCTION(0x0, "gpio_in"),
2138 SUNXI_FUNCTION(0x1, "gpio_out"),
2139 SUNXI_FUNCTION(0x2, "gmac"), /* TXERR */
2140 SUNXI_FUNCTION(0x3, "lcd1"), /* D21 */
2141 SUNXI_FUNCTION(0x4, "spi3")), /* CS0 */
2142 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA22,
2143 SUNXI_FUNCTION(0x0, "gpio_in"),
2144 SUNXI_FUNCTION(0x1, "gpio_out"),
2145 SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */
2146 SUNXI_FUNCTION(0x3, "lcd1"), /* D22 */
2147 SUNXI_FUNCTION(0x4, "spi3")), /* CLK */
2148 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA23,
2149 SUNXI_FUNCTION(0x0, "gpio_in"),
2150 SUNXI_FUNCTION(0x1, "gpio_out"),
2151 SUNXI_FUNCTION(0x2, "gmac"), /* COL */
2152 SUNXI_FUNCTION(0x3, "lcd1"), /* D23 */
2153 SUNXI_FUNCTION(0x4, "spi3")), /* MOSI */
2154 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA24,
2155 SUNXI_FUNCTION(0x0, "gpio_in"),
2156 SUNXI_FUNCTION(0x1, "gpio_out"),
2157 SUNXI_FUNCTION(0x2, "gmac"), /* CRS */
2158 SUNXI_FUNCTION(0x3, "lcd1"), /* CLK */
2159 SUNXI_FUNCTION(0x4, "spi3")), /* MISO */
2160 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA25,
2161 SUNXI_FUNCTION(0x0, "gpio_in"),
2162 SUNXI_FUNCTION(0x1, "gpio_out"),
2163 SUNXI_FUNCTION(0x2, "gmac"), /* CLKIN */
2164 SUNXI_FUNCTION(0x3, "lcd1"), /* DE */
2165 SUNXI_FUNCTION(0x4, "spi3")), /* CS1 */
2166 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA26,
2167 SUNXI_FUNCTION(0x0, "gpio_in"),
2168 SUNXI_FUNCTION(0x1, "gpio_out"),
2169 SUNXI_FUNCTION(0x2, "gmac"), /* MDC */
2170 SUNXI_FUNCTION(0x3, "lcd1")), /* HSYNC */
2171 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA27,
2172 SUNXI_FUNCTION(0x0, "gpio_in"),
2173 SUNXI_FUNCTION(0x1, "gpio_out"),
2174 SUNXI_FUNCTION(0x2, "gmac"), /* MDIO */
2175 SUNXI_FUNCTION(0x3, "lcd1")), /* VSYNC */
2176 /* Hole */
2177 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
2178 SUNXI_FUNCTION(0x0, "gpio_in"),
2179 SUNXI_FUNCTION(0x1, "gpio_out"),
2180 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
2181 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
2182 SUNXI_FUNCTION(0x4, "csi")), /* MCLK1 */
2183 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
2184 SUNXI_FUNCTION(0x0, "gpio_in"),
2185 SUNXI_FUNCTION(0x1, "gpio_out"),
2186 SUNXI_FUNCTION(0x2, "i2s0")), /* BCLK */
2187 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
2188 SUNXI_FUNCTION(0x0, "gpio_in"),
2189 SUNXI_FUNCTION(0x1, "gpio_out"),
2190 SUNXI_FUNCTION(0x2, "i2s0")), /* LRCK */
2191 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
2192 SUNXI_FUNCTION(0x0, "gpio_in"),
2193 SUNXI_FUNCTION(0x1, "gpio_out"),
2194 SUNXI_FUNCTION(0x2, "i2s0")), /* DO0 */
2195 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
2196 SUNXI_FUNCTION(0x0, "gpio_in"),
2197 SUNXI_FUNCTION(0x1, "gpio_out"),
2198 SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */
2199 SUNXI_FUNCTION(0x3, "uart3")), /* RTS */
2200 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5,
2201 SUNXI_FUNCTION(0x0, "gpio_in"),
2202 SUNXI_FUNCTION(0x1, "gpio_out"),
2203 SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */
2204 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
2205 SUNXI_FUNCTION(0x4, "i2c3")), /* SCK */
2206 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6,
2207 SUNXI_FUNCTION(0x0, "gpio_in"),
2208 SUNXI_FUNCTION(0x1, "gpio_out"),
2209 SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */
2210 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
2211 SUNXI_FUNCTION(0x4, "i2c3")), /* SDA */
2212 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7,
2213 SUNXI_FUNCTION(0x0, "gpio_in"),
2214 SUNXI_FUNCTION(0x1, "gpio_out"),
2215 SUNXI_FUNCTION(0x3, "i2s0")), /* DI */
2216 /* Hole */
2217 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
2218 SUNXI_FUNCTION(0x0, "gpio_in"),
2219 SUNXI_FUNCTION(0x1, "gpio_out"),
2220 SUNXI_FUNCTION(0x2, "nand0"), /* WE */
2221 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
2222 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
2223 SUNXI_FUNCTION(0x0, "gpio_in"),
2224 SUNXI_FUNCTION(0x1, "gpio_out"),
2225 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
2226 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
2227 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
2228 SUNXI_FUNCTION(0x0, "gpio_in"),
2229 SUNXI_FUNCTION(0x1, "gpio_out"),
2230 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
2231 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
2232 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
2233 SUNXI_FUNCTION(0x0, "gpio_in"),
2234 SUNXI_FUNCTION(0x1, "gpio_out"),
2235 SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */
2236 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
2237 SUNXI_FUNCTION(0x0, "gpio_in"),
2238 SUNXI_FUNCTION(0x1, "gpio_out"),
2239 SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
2240 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
2241 SUNXI_FUNCTION(0x0, "gpio_in"),
2242 SUNXI_FUNCTION(0x1, "gpio_out"),
2243 SUNXI_FUNCTION(0x2, "nand0")), /* RE */
2244 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
2245 SUNXI_FUNCTION(0x0, "gpio_in"),
2246 SUNXI_FUNCTION(0x1, "gpio_out"),
2247 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
2248 SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */
2249 SUNXI_FUNCTION(0x4, "mmc3")), /* CMD */
2250 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
2251 SUNXI_FUNCTION(0x0, "gpio_in"),
2252 SUNXI_FUNCTION(0x1, "gpio_out"),
2253 SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */
2254 SUNXI_FUNCTION(0x3, "mmc2"), /* CLK */
2255 SUNXI_FUNCTION(0x4, "mmc3")), /* CLK */
2256 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
2257 SUNXI_FUNCTION(0x0, "gpio_in"),
2258 SUNXI_FUNCTION(0x1, "gpio_out"),
2259 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
2260 SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */
2261 SUNXI_FUNCTION(0x4, "mmc3")), /* D0 */
2262 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
2263 SUNXI_FUNCTION(0x0, "gpio_in"),
2264 SUNXI_FUNCTION(0x1, "gpio_out"),
2265 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
2266 SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */
2267 SUNXI_FUNCTION(0x4, "mmc3")), /* D1 */
2268 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
2269 SUNXI_FUNCTION(0x0, "gpio_in"),
2270 SUNXI_FUNCTION(0x1, "gpio_out"),
2271 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
2272 SUNXI_FUNCTION(0x3, "mmc2"), /* D2 */
2273 SUNXI_FUNCTION(0x4, "mmc3")), /* D2 */
2274 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
2275 SUNXI_FUNCTION(0x0, "gpio_in"),
2276 SUNXI_FUNCTION(0x1, "gpio_out"),
2277 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
2278 SUNXI_FUNCTION(0x3, "mmc2"), /* D3 */
2279 SUNXI_FUNCTION(0x4, "mmc3")), /* D3 */
2280 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
2281 SUNXI_FUNCTION(0x0, "gpio_in"),
2282 SUNXI_FUNCTION(0x1, "gpio_out"),
2283 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
2284 SUNXI_FUNCTION(0x3, "mmc2"), /* D4 */
2285 SUNXI_FUNCTION(0x4, "mmc3")), /* D4 */
2286 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
2287 SUNXI_FUNCTION(0x0, "gpio_in"),
2288 SUNXI_FUNCTION(0x1, "gpio_out"),
2289 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
2290 SUNXI_FUNCTION(0x3, "mmc2"), /* D5 */
2291 SUNXI_FUNCTION(0x4, "mmc3")), /* D5 */
2292 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
2293 SUNXI_FUNCTION(0x0, "gpio_in"),
2294 SUNXI_FUNCTION(0x1, "gpio_out"),
2295 SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
2296 SUNXI_FUNCTION(0x3, "mmc2"), /* D6 */
2297 SUNXI_FUNCTION(0x4, "mmc3")), /* D6 */
2298 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
2299 SUNXI_FUNCTION(0x0, "gpio_in"),
2300 SUNXI_FUNCTION(0x1, "gpio_out"),
2301 SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
2302 SUNXI_FUNCTION(0x3, "mmc2"), /* D7 */
2303 SUNXI_FUNCTION(0x4, "mmc3")), /* D7 */
2304 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16,
2305 SUNXI_FUNCTION(0x0, "gpio_in"),
2306 SUNXI_FUNCTION(0x1, "gpio_out"),
2307 SUNXI_FUNCTION(0x2, "nand0"), /* DQ8 */
2308 SUNXI_FUNCTION(0x3, "nand1")), /* DQ0 */
2309 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17,
2310 SUNXI_FUNCTION(0x0, "gpio_in"),
2311 SUNXI_FUNCTION(0x1, "gpio_out"),
2312 SUNXI_FUNCTION(0x2, "nand0"), /* DQ9 */
2313 SUNXI_FUNCTION(0x3, "nand1")), /* DQ1 */
2314 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18,
2315 SUNXI_FUNCTION(0x0, "gpio_in"),
2316 SUNXI_FUNCTION(0x1, "gpio_out"),
2317 SUNXI_FUNCTION(0x2, "nand0"), /* DQ10 */
2318 SUNXI_FUNCTION(0x3, "nand1")), /* DQ2 */
2319 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
2320 SUNXI_FUNCTION(0x0, "gpio_in"),
2321 SUNXI_FUNCTION(0x1, "gpio_out"),
2322 SUNXI_FUNCTION(0x2, "nand0"), /* DQ11 */
2323 SUNXI_FUNCTION(0x3, "nand1")), /* DQ3 */
2324 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20,
2325 SUNXI_FUNCTION(0x0, "gpio_in"),
2326 SUNXI_FUNCTION(0x1, "gpio_out"),
2327 SUNXI_FUNCTION(0x2, "nand0"), /* DQ12 */
2328 SUNXI_FUNCTION(0x3, "nand1")), /* DQ4 */
2329 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21,
2330 SUNXI_FUNCTION(0x0, "gpio_in"),
2331 SUNXI_FUNCTION(0x1, "gpio_out"),
2332 SUNXI_FUNCTION(0x2, "nand0"), /* DQ13 */
2333 SUNXI_FUNCTION(0x3, "nand1")), /* DQ5 */
2334 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22,
2335 SUNXI_FUNCTION(0x0, "gpio_in"),
2336 SUNXI_FUNCTION(0x1, "gpio_out"),
2337 SUNXI_FUNCTION(0x2, "nand0"), /* DQ14 */
2338 SUNXI_FUNCTION(0x3, "nand1")), /* DQ6 */
2339 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23,
2340 SUNXI_FUNCTION(0x0, "gpio_in"),
2341 SUNXI_FUNCTION(0x1, "gpio_out"),
2342 SUNXI_FUNCTION(0x2, "nand0"), /* DQ15 */
2343 SUNXI_FUNCTION(0x3, "nand1")), /* DQ7 */
2344 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24,
2345 SUNXI_FUNCTION(0x0, "gpio_in"),
2346 SUNXI_FUNCTION(0x1, "gpio_out"),
2347 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
2348 SUNXI_FUNCTION(0x3, "mmc2"), /* RST */
2349 SUNXI_FUNCTION(0x4, "mmc3")), /* RST */
2350 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC25,
2351 SUNXI_FUNCTION(0x0, "gpio_in"),
2352 SUNXI_FUNCTION(0x1, "gpio_out"),
2353 SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */
2354 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC26,
2355 SUNXI_FUNCTION(0x0, "gpio_in"),
2356 SUNXI_FUNCTION(0x1, "gpio_out"),
2357 SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */
2358 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC27,
2359 SUNXI_FUNCTION(0x0, "gpio_in"),
2360 SUNXI_FUNCTION(0x1, "gpio_out"),
2361 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
2362 /* Hole */
2363 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0,
2364 SUNXI_FUNCTION(0x0, "gpio_in"),
2365 SUNXI_FUNCTION(0x1, "gpio_out"),
2366 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
2367 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
2368 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1,
2369 SUNXI_FUNCTION(0x0, "gpio_in"),
2370 SUNXI_FUNCTION(0x1, "gpio_out"),
2371 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
2372 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
2373 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
2374 SUNXI_FUNCTION(0x0, "gpio_in"),
2375 SUNXI_FUNCTION(0x1, "gpio_out"),
2376 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
2377 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
2378 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
2379 SUNXI_FUNCTION(0x0, "gpio_in"),
2380 SUNXI_FUNCTION(0x1, "gpio_out"),
2381 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
2382 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
2383 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
2384 SUNXI_FUNCTION(0x0, "gpio_in"),
2385 SUNXI_FUNCTION(0x1, "gpio_out"),
2386 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
2387 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
2388 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
2389 SUNXI_FUNCTION(0x0, "gpio_in"),
2390 SUNXI_FUNCTION(0x1, "gpio_out"),
2391 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
2392 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
2393 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
2394 SUNXI_FUNCTION(0x0, "gpio_in"),
2395 SUNXI_FUNCTION(0x1, "gpio_out"),
2396 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
2397 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
2398 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
2399 SUNXI_FUNCTION(0x0, "gpio_in"),
2400 SUNXI_FUNCTION(0x1, "gpio_out"),
2401 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
2402 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
2403 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8,
2404 SUNXI_FUNCTION(0x0, "gpio_in"),
2405 SUNXI_FUNCTION(0x1, "gpio_out"),
2406 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
2407 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
2408 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9,
2409 SUNXI_FUNCTION(0x0, "gpio_in"),
2410 SUNXI_FUNCTION(0x1, "gpio_out"),
2411 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
2412 SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
2413 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
2414 SUNXI_FUNCTION(0x0, "gpio_in"),
2415 SUNXI_FUNCTION(0x1, "gpio_out"),
2416 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
2417 SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */
2418 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
2419 SUNXI_FUNCTION(0x0, "gpio_in"),
2420 SUNXI_FUNCTION(0x1, "gpio_out"),
2421 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
2422 SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */
2423 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
2424 SUNXI_FUNCTION(0x0, "gpio_in"),
2425 SUNXI_FUNCTION(0x1, "gpio_out"),
2426 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
2427 SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */
2428 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
2429 SUNXI_FUNCTION(0x0, "gpio_in"),
2430 SUNXI_FUNCTION(0x1, "gpio_out"),
2431 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
2432 SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */
2433 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
2434 SUNXI_FUNCTION(0x0, "gpio_in"),
2435 SUNXI_FUNCTION(0x1, "gpio_out"),
2436 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
2437 SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */
2438 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
2439 SUNXI_FUNCTION(0x0, "gpio_in"),
2440 SUNXI_FUNCTION(0x1, "gpio_out"),
2441 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
2442 SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */
2443 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16,
2444 SUNXI_FUNCTION(0x0, "gpio_in"),
2445 SUNXI_FUNCTION(0x1, "gpio_out"),
2446 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
2447 SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */
2448 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17,
2449 SUNXI_FUNCTION(0x0, "gpio_in"),
2450 SUNXI_FUNCTION(0x1, "gpio_out"),
2451 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
2452 SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */
2453 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
2454 SUNXI_FUNCTION(0x0, "gpio_in"),
2455 SUNXI_FUNCTION(0x1, "gpio_out"),
2456 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
2457 SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */
2458 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
2459 SUNXI_FUNCTION(0x0, "gpio_in"),
2460 SUNXI_FUNCTION(0x1, "gpio_out"),
2461 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
2462 SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */
2463 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
2464 SUNXI_FUNCTION(0x0, "gpio_in"),
2465 SUNXI_FUNCTION(0x1, "gpio_out"),
2466 SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
2467 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
2468 SUNXI_FUNCTION(0x0, "gpio_in"),
2469 SUNXI_FUNCTION(0x1, "gpio_out"),
2470 SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
2471 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
2472 SUNXI_FUNCTION(0x0, "gpio_in"),
2473 SUNXI_FUNCTION(0x1, "gpio_out"),
2474 SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
2475 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
2476 SUNXI_FUNCTION(0x0, "gpio_in"),
2477 SUNXI_FUNCTION(0x1, "gpio_out"),
2478 SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
2479 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
2480 SUNXI_FUNCTION(0x0, "gpio_in"),
2481 SUNXI_FUNCTION(0x1, "gpio_out"),
2482 SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
2483 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
2484 SUNXI_FUNCTION(0x0, "gpio_in"),
2485 SUNXI_FUNCTION(0x1, "gpio_out"),
2486 SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
2487 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
2488 SUNXI_FUNCTION(0x0, "gpio_in"),
2489 SUNXI_FUNCTION(0x1, "gpio_out"),
2490 SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
2491 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
2492 SUNXI_FUNCTION(0x0, "gpio_in"),
2493 SUNXI_FUNCTION(0x1, "gpio_out"),
2494 SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
2495 /* Hole */
2496 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
2497 SUNXI_FUNCTION(0x0, "gpio_in"),
2498 SUNXI_FUNCTION(0x1, "gpio_out"),
2499 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
2500 SUNXI_FUNCTION(0x3, "ts")), /* CLK */
2501 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
2502 SUNXI_FUNCTION(0x0, "gpio_in"),
2503 SUNXI_FUNCTION(0x1, "gpio_out"),
2504 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
2505 SUNXI_FUNCTION(0x3, "ts")), /* ERR */
2506 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
2507 SUNXI_FUNCTION(0x0, "gpio_in"),
2508 SUNXI_FUNCTION(0x1, "gpio_out"),
2509 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
2510 SUNXI_FUNCTION(0x3, "ts")), /* SYNC */
2511 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
2512 SUNXI_FUNCTION(0x0, "gpio_in"),
2513 SUNXI_FUNCTION(0x1, "gpio_out"),
2514 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
2515 SUNXI_FUNCTION(0x3, "ts")), /* DVLD */
2516 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
2517 SUNXI_FUNCTION(0x0, "gpio_in"),
2518 SUNXI_FUNCTION(0x1, "gpio_out"),
2519 SUNXI_FUNCTION(0x2, "csi"), /* D0 */
2520 SUNXI_FUNCTION(0x3, "uart5")), /* TX */
2521 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
2522 SUNXI_FUNCTION(0x0, "gpio_in"),
2523 SUNXI_FUNCTION(0x1, "gpio_out"),
2524 SUNXI_FUNCTION(0x2, "csi"), /* D1 */
2525 SUNXI_FUNCTION(0x3, "uart5")), /* RX */
2526 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
2527 SUNXI_FUNCTION(0x0, "gpio_in"),
2528 SUNXI_FUNCTION(0x1, "gpio_out"),
2529 SUNXI_FUNCTION(0x2, "csi"), /* D2 */
2530 SUNXI_FUNCTION(0x3, "uart5")), /* RTS */
2531 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
2532 SUNXI_FUNCTION(0x0, "gpio_in"),
2533 SUNXI_FUNCTION(0x1, "gpio_out"),
2534 SUNXI_FUNCTION(0x2, "csi"), /* D3 */
2535 SUNXI_FUNCTION(0x3, "uart5")), /* CTS */
2536 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
2537 SUNXI_FUNCTION(0x0, "gpio_in"),
2538 SUNXI_FUNCTION(0x1, "gpio_out"),
2539 SUNXI_FUNCTION(0x2, "csi"), /* D4 */
2540 SUNXI_FUNCTION(0x3, "ts")), /* D0 */
2541 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
2542 SUNXI_FUNCTION(0x0, "gpio_in"),
2543 SUNXI_FUNCTION(0x1, "gpio_out"),
2544 SUNXI_FUNCTION(0x2, "csi"), /* D5 */
2545 SUNXI_FUNCTION(0x3, "ts")), /* D1 */
2546 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
2547 SUNXI_FUNCTION(0x0, "gpio_in"),
2548 SUNXI_FUNCTION(0x1, "gpio_out"),
2549 SUNXI_FUNCTION(0x2, "csi"), /* D6 */
2550 SUNXI_FUNCTION(0x3, "ts")), /* D2 */
2551 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
2552 SUNXI_FUNCTION(0x0, "gpio_in"),
2553 SUNXI_FUNCTION(0x1, "gpio_out"),
2554 SUNXI_FUNCTION(0x2, "csi"), /* D7 */
2555 SUNXI_FUNCTION(0x3, "ts")), /* D3 */
2556 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE12,
2557 SUNXI_FUNCTION(0x0, "gpio_in"),
2558 SUNXI_FUNCTION(0x1, "gpio_out"),
2559 SUNXI_FUNCTION(0x2, "csi"), /* D8 */
2560 SUNXI_FUNCTION(0x3, "ts")), /* D4 */
2561 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE13,
2562 SUNXI_FUNCTION(0x0, "gpio_in"),
2563 SUNXI_FUNCTION(0x1, "gpio_out"),
2564 SUNXI_FUNCTION(0x2, "csi"), /* D9 */
2565 SUNXI_FUNCTION(0x3, "ts")), /* D5 */
2566 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE14,
2567 SUNXI_FUNCTION(0x0, "gpio_in"),
2568 SUNXI_FUNCTION(0x1, "gpio_out"),
2569 SUNXI_FUNCTION(0x2, "csi"), /* D10 */
2570 SUNXI_FUNCTION(0x3, "ts")), /* D6 */
2571 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE15,
2572 SUNXI_FUNCTION(0x0, "gpio_in"),
2573 SUNXI_FUNCTION(0x1, "gpio_out"),
2574 SUNXI_FUNCTION(0x2, "csi"), /* D11 */
2575 SUNXI_FUNCTION(0x3, "ts")), /* D7 */
2576 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE16,
2577 SUNXI_FUNCTION(0x0, "gpio_in"),
2578 SUNXI_FUNCTION(0x1, "gpio_out"),
2579 SUNXI_FUNCTION(0x2, "csi")), /* MIPI CSI MCLK */
2580 /* Hole */
2581 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
2582 SUNXI_FUNCTION(0x0, "gpio_in"),
2583 SUNXI_FUNCTION(0x1, "gpio_out"),
2584 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
2585 SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */
2586 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
2587 SUNXI_FUNCTION(0x0, "gpio_in"),
2588 SUNXI_FUNCTION(0x1, "gpio_out"),
2589 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
2590 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
2591 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
2592 SUNXI_FUNCTION(0x0, "gpio_in"),
2593 SUNXI_FUNCTION(0x1, "gpio_out"),
2594 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
2595 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
2596 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
2597 SUNXI_FUNCTION(0x0, "gpio_in"),
2598 SUNXI_FUNCTION(0x1, "gpio_out"),
2599 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
2600 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
2601 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
2602 SUNXI_FUNCTION(0x0, "gpio_in"),
2603 SUNXI_FUNCTION(0x1, "gpio_out"),
2604 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
2605 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
2606 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
2607 SUNXI_FUNCTION(0x0, "gpio_in"),
2608 SUNXI_FUNCTION(0x1, "gpio_out"),
2609 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
2610 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
2611 /* Hole */
2612 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
2613 SUNXI_FUNCTION(0x0, "gpio_in"),
2614 SUNXI_FUNCTION(0x1, "gpio_out"),
2615 SUNXI_FUNCTION(0x2, "mmc1")), /* CLK */
2616 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
2617 SUNXI_FUNCTION(0x0, "gpio_in"),
2618 SUNXI_FUNCTION(0x1, "gpio_out"),
2619 SUNXI_FUNCTION(0x2, "mmc1")), /* CMD */
2620 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
2621 SUNXI_FUNCTION(0x0, "gpio_in"),
2622 SUNXI_FUNCTION(0x1, "gpio_out"),
2623 SUNXI_FUNCTION(0x2, "mmc1")), /* D0 */
2624 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
2625 SUNXI_FUNCTION(0x0, "gpio_in"),
2626 SUNXI_FUNCTION(0x1, "gpio_out"),
2627 SUNXI_FUNCTION(0x2, "mmc1")), /* D1 */
2628 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
2629 SUNXI_FUNCTION(0x0, "gpio_in"),
2630 SUNXI_FUNCTION(0x1, "gpio_out"),
2631 SUNXI_FUNCTION(0x2, "mmc1")), /* D2 */
2632 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5,
2633 SUNXI_FUNCTION(0x0, "gpio_in"),
2634 SUNXI_FUNCTION(0x1, "gpio_out"),
2635 SUNXI_FUNCTION(0x2, "mmc1")), /* D3 */
2636 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6,
2637 SUNXI_FUNCTION(0x0, "gpio_in"),
2638 SUNXI_FUNCTION(0x1, "gpio_out"),
2639 SUNXI_FUNCTION(0x2, "uart2")), /* TX */
2640 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7,
2641 SUNXI_FUNCTION(0x0, "gpio_in"),
2642 SUNXI_FUNCTION(0x1, "gpio_out"),
2643 SUNXI_FUNCTION(0x2, "uart2")), /* RX */
2644 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8,
2645 SUNXI_FUNCTION(0x0, "gpio_in"),
2646 SUNXI_FUNCTION(0x1, "gpio_out"),
2647 SUNXI_FUNCTION(0x2, "uart2")), /* RTS */
2648 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
2649 SUNXI_FUNCTION(0x0, "gpio_in"),
2650 SUNXI_FUNCTION(0x1, "gpio_out"),
2651 SUNXI_FUNCTION(0x2, "uart2")), /* CTS */
2652 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
2653 SUNXI_FUNCTION(0x0, "gpio_in"),
2654 SUNXI_FUNCTION(0x1, "gpio_out"),
2655 SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
2656 SUNXI_FUNCTION(0x3, "usb")), /* DP3 */
2657 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
2658 SUNXI_FUNCTION(0x0, "gpio_in"),
2659 SUNXI_FUNCTION(0x1, "gpio_out"),
2660 SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
2661 SUNXI_FUNCTION(0x3, "usb")), /* DM3 */
2662 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12,
2663 SUNXI_FUNCTION(0x0, "gpio_in"),
2664 SUNXI_FUNCTION(0x1, "gpio_out"),
2665 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
2666 SUNXI_FUNCTION(0x3, "i2s1")), /* MCLK */
2667 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG13,
2668 SUNXI_FUNCTION(0x0, "gpio_in"),
2669 SUNXI_FUNCTION(0x1, "gpio_out"),
2670 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
2671 SUNXI_FUNCTION(0x3, "i2s1")), /* BCLK */
2672 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG14,
2673 SUNXI_FUNCTION(0x0, "gpio_in"),
2674 SUNXI_FUNCTION(0x1, "gpio_out"),
2675 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
2676 SUNXI_FUNCTION(0x3, "i2s1")), /* LRCK */
2677 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG15,
2678 SUNXI_FUNCTION(0x0, "gpio_in"),
2679 SUNXI_FUNCTION(0x1, "gpio_out"),
2680 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
2681 SUNXI_FUNCTION(0x3, "i2s1")), /* DIN */
2682 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG16,
2683 SUNXI_FUNCTION(0x0, "gpio_in"),
2684 SUNXI_FUNCTION(0x1, "gpio_out"),
2685 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
2686 SUNXI_FUNCTION(0x3, "i2s1")), /* DOUT */
2687 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG17,
2688 SUNXI_FUNCTION(0x0, "gpio_in"),
2689 SUNXI_FUNCTION(0x1, "gpio_out"),
2690 SUNXI_FUNCTION(0x2, "uart4")), /* TX */
2691 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG18,
2692 SUNXI_FUNCTION(0x0, "gpio_in"),
2693 SUNXI_FUNCTION(0x1, "gpio_out"),
2694 SUNXI_FUNCTION(0x2, "uart4")), /* RX */
2695 /* Hole */
2696 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0,
2697 SUNXI_FUNCTION(0x0, "gpio_in"),
2698 SUNXI_FUNCTION(0x1, "gpio_out"),
2699 SUNXI_FUNCTION(0x2, "nand1")), /* WE */
2700 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1,
2701 SUNXI_FUNCTION(0x0, "gpio_in"),
2702 SUNXI_FUNCTION(0x1, "gpio_out"),
2703 SUNXI_FUNCTION(0x2, "nand1")), /* ALE */
2704 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2,
2705 SUNXI_FUNCTION(0x0, "gpio_in"),
2706 SUNXI_FUNCTION(0x1, "gpio_out"),
2707 SUNXI_FUNCTION(0x2, "nand1")), /* CLE */
2708 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3,
2709 SUNXI_FUNCTION(0x0, "gpio_in"),
2710 SUNXI_FUNCTION(0x1, "gpio_out"),
2711 SUNXI_FUNCTION(0x2, "nand1")), /* CE1 */
2712 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4,
2713 SUNXI_FUNCTION(0x0, "gpio_in"),
2714 SUNXI_FUNCTION(0x1, "gpio_out"),
2715 SUNXI_FUNCTION(0x2, "nand1")), /* CE0 */
2716 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5,
2717 SUNXI_FUNCTION(0x0, "gpio_in"),
2718 SUNXI_FUNCTION(0x1, "gpio_out"),
2719 SUNXI_FUNCTION(0x2, "nand1")), /* RE */
2720 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6,
2721 SUNXI_FUNCTION(0x0, "gpio_in"),
2722 SUNXI_FUNCTION(0x1, "gpio_out"),
2723 SUNXI_FUNCTION(0x2, "nand1")), /* RB0 */
2724 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7,
2725 SUNXI_FUNCTION(0x0, "gpio_in"),
2726 SUNXI_FUNCTION(0x1, "gpio_out"),
2727 SUNXI_FUNCTION(0x2, "nand1")), /* RB1 */
2728 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8,
2729 SUNXI_FUNCTION(0x0, "gpio_in"),
2730 SUNXI_FUNCTION(0x1, "gpio_out"),
2731 SUNXI_FUNCTION(0x2, "nand1")), /* DQS */
2732 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9,
2733 SUNXI_FUNCTION(0x0, "gpio_in"),
2734 SUNXI_FUNCTION(0x1, "gpio_out"),
2735 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
2736 SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
2737 SUNXI_FUNCTION(0x4, "pwm1")), /* Positive */
2738 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10,
2739 SUNXI_FUNCTION(0x0, "gpio_in"),
2740 SUNXI_FUNCTION(0x1, "gpio_out"),
2741 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
2742 SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
2743 SUNXI_FUNCTION(0x4, "pwm1")), /* Negative */
2744 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11,
2745 SUNXI_FUNCTION(0x0, "gpio_in"),
2746 SUNXI_FUNCTION(0x1, "gpio_out"),
2747 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
2748 SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
2749 SUNXI_FUNCTION(0x4, "pwm2")), /* Positive */
2750 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12,
2751 SUNXI_FUNCTION(0x0, "gpio_in"),
2752 SUNXI_FUNCTION(0x1, "gpio_out"),
2753 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
2754 SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
2755 SUNXI_FUNCTION(0x4, "pwm2")), /* Negative */
2756 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13,
2757 SUNXI_FUNCTION(0x0, "gpio_in"),
2758 SUNXI_FUNCTION(0x1, "gpio_out"),
2759 SUNXI_FUNCTION(0x2, "pwm0")),
2760 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14,
2761 SUNXI_FUNCTION(0x0, "gpio_in"),
2762 SUNXI_FUNCTION(0x1, "gpio_out"),
2763 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
2764 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15,
2765 SUNXI_FUNCTION(0x0, "gpio_in"),
2766 SUNXI_FUNCTION(0x1, "gpio_out"),
2767 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
2768 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16,
2769 SUNXI_FUNCTION(0x0, "gpio_in"),
2770 SUNXI_FUNCTION(0x1, "gpio_out"),
2771 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
2772 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17,
2773 SUNXI_FUNCTION(0x0, "gpio_in"),
2774 SUNXI_FUNCTION(0x1, "gpio_out"),
2775 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
2776 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18,
2777 SUNXI_FUNCTION(0x0, "gpio_in"),
2778 SUNXI_FUNCTION(0x1, "gpio_out"),
2779 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
2780 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19,
2781 SUNXI_FUNCTION(0x0, "gpio_in"),
2782 SUNXI_FUNCTION(0x1, "gpio_out"),
2783 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
2784 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20,
2785 SUNXI_FUNCTION(0x0, "gpio_in"),
2786 SUNXI_FUNCTION(0x1, "gpio_out"),
2787 SUNXI_FUNCTION(0x2, "uart0")), /* TX */
2788 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21,
2789 SUNXI_FUNCTION(0x0, "gpio_in"),
2790 SUNXI_FUNCTION(0x1, "gpio_out"),
2791 SUNXI_FUNCTION(0x2, "uart0")), /* RX */
2792 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22,
2793 SUNXI_FUNCTION(0x0, "gpio_in"),
2794 SUNXI_FUNCTION(0x1, "gpio_out")),
2795 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23,
2796 SUNXI_FUNCTION(0x0, "gpio_in"),
2797 SUNXI_FUNCTION(0x1, "gpio_out")),
2798 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24,
2799 SUNXI_FUNCTION(0x0, "gpio_in"),
2800 SUNXI_FUNCTION(0x1, "gpio_out")),
2801 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25,
2802 SUNXI_FUNCTION(0x0, "gpio_in"),
2803 SUNXI_FUNCTION(0x1, "gpio_out")),
2804 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26,
2805 SUNXI_FUNCTION(0x0, "gpio_in"),
2806 SUNXI_FUNCTION(0x1, "gpio_out")),
2807 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27,
2808 SUNXI_FUNCTION(0x0, "gpio_in"),
2809 SUNXI_FUNCTION(0x1, "gpio_out")),
2810 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH28,
2811 SUNXI_FUNCTION(0x0, "gpio_in"),
2812 SUNXI_FUNCTION(0x1, "gpio_out")),
2813 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH29,
2814 SUNXI_FUNCTION(0x0, "gpio_in"),
2815 SUNXI_FUNCTION(0x1, "gpio_out"),
2816 SUNXI_FUNCTION(0x2, "nand1")), /* CE2 */
2817 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH30,
2818 SUNXI_FUNCTION(0x0, "gpio_in"),
2819 SUNXI_FUNCTION(0x1, "gpio_out"),
2820 SUNXI_FUNCTION(0x2, "nand1")), /* CE3 */
2821};
2822
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]2823static const struct sunxi_desc_pin sun7i_a20_pins[] = {
2824 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
2825 SUNXI_FUNCTION(0x0, "gpio_in"),
2826 SUNXI_FUNCTION(0x1, "gpio_out"),
2827 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
2828 SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
2829 SUNXI_FUNCTION(0x4, "uart2"), /* RTS */
2830 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD3 */
2831 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1,
2832 SUNXI_FUNCTION(0x0, "gpio_in"),
2833 SUNXI_FUNCTION(0x1, "gpio_out"),
2834 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
2835 SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
2836 SUNXI_FUNCTION(0x4, "uart2"), /* CTS */
2837 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD2 */
2838 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2,
2839 SUNXI_FUNCTION(0x0, "gpio_in"),
2840 SUNXI_FUNCTION(0x1, "gpio_out"),
2841 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
2842 SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
2843 SUNXI_FUNCTION(0x4, "uart2"), /* TX */
2844 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD1 */
2845 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3,
2846 SUNXI_FUNCTION(0x0, "gpio_in"),
2847 SUNXI_FUNCTION(0x1, "gpio_out"),
2848 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
2849 SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
2850 SUNXI_FUNCTION(0x4, "uart2"), /* RX */
2851 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD0 */
2852 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4,
2853 SUNXI_FUNCTION(0x0, "gpio_in"),
2854 SUNXI_FUNCTION(0x1, "gpio_out"),
2855 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
2856 SUNXI_FUNCTION(0x3, "spi1"), /* CS1 */
2857 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD3 */
2858 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5,
2859 SUNXI_FUNCTION(0x0, "gpio_in"),
2860 SUNXI_FUNCTION(0x1, "gpio_out"),
2861 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
2862 SUNXI_FUNCTION(0x3, "spi3"), /* CS0 */
2863 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD2 */
2864 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6,
2865 SUNXI_FUNCTION(0x0, "gpio_in"),
2866 SUNXI_FUNCTION(0x1, "gpio_out"),
2867 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
2868 SUNXI_FUNCTION(0x3, "spi3"), /* CLK */
2869 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD1 */
2870 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7,
2871 SUNXI_FUNCTION(0x0, "gpio_in"),
2872 SUNXI_FUNCTION(0x1, "gpio_out"),
2873 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
2874 SUNXI_FUNCTION(0x3, "spi3"), /* MOSI */
2875 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD0 */
2876 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8,
2877 SUNXI_FUNCTION(0x0, "gpio_in"),
2878 SUNXI_FUNCTION(0x1, "gpio_out"),
2879 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
2880 SUNXI_FUNCTION(0x3, "spi3"), /* MISO */
2881 SUNXI_FUNCTION(0x5, "gmac")), /* GRXCK */
2882 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9,
2883 SUNXI_FUNCTION(0x0, "gpio_in"),
2884 SUNXI_FUNCTION(0x1, "gpio_out"),
2885 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
2886 SUNXI_FUNCTION(0x3, "spi3"), /* CS1 */
2887 SUNXI_FUNCTION(0x5, "gmac"), /* GNULL / ERXERR */
2888 SUNXI_FUNCTION(0x6, "i2s1")), /* MCLK */
2889 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10,
2890 SUNXI_FUNCTION(0x0, "gpio_in"),
2891 SUNXI_FUNCTION(0x1, "gpio_out"),
2892 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
2893 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
2894 SUNXI_FUNCTION(0x5, "gmac")), /* GRXCTL / ERXDV */
2895 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11,
2896 SUNXI_FUNCTION(0x0, "gpio_in"),
2897 SUNXI_FUNCTION(0x1, "gpio_out"),
2898 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
2899 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
2900 SUNXI_FUNCTION(0x5, "gmac")), /* EMDC */
2901 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12,
2902 SUNXI_FUNCTION(0x0, "gpio_in"),
2903 SUNXI_FUNCTION(0x1, "gpio_out"),
2904 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */
2905 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
2906 SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
2907 SUNXI_FUNCTION(0x5, "gmac")), /* EMDIO */
2908 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13,
2909 SUNXI_FUNCTION(0x0, "gpio_in"),
2910 SUNXI_FUNCTION(0x1, "gpio_out"),
2911 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */
2912 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
2913 SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
2914 SUNXI_FUNCTION(0x5, "gmac")), /* GTXCTL / ETXEN */
2915 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14,
2916 SUNXI_FUNCTION(0x0, "gpio_in"),
2917 SUNXI_FUNCTION(0x1, "gpio_out"),
2918 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */
2919 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
2920 SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
2921 SUNXI_FUNCTION(0x5, "gmac"), /* GNULL / ETXCK */
2922 SUNXI_FUNCTION(0x6, "i2s1")), /* BCLK */
2923 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15,
2924 SUNXI_FUNCTION(0x0, "gpio_in"),
2925 SUNXI_FUNCTION(0x1, "gpio_out"),
2926 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */
2927 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
2928 SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
2929 SUNXI_FUNCTION(0x5, "gmac"), /* GTXCK / ECRS */
2930 SUNXI_FUNCTION(0x6, "i2s1")), /* LRCK */
2931 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16,
2932 SUNXI_FUNCTION(0x0, "gpio_in"),
2933 SUNXI_FUNCTION(0x1, "gpio_out"),
2934 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */
2935 SUNXI_FUNCTION(0x3, "can"), /* TX */
2936 SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
2937 SUNXI_FUNCTION(0x5, "gmac"), /* GCLKIN / ECOL */
2938 SUNXI_FUNCTION(0x6, "i2s1")), /* DO */
2939 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17,
2940 SUNXI_FUNCTION(0x0, "gpio_in"),
2941 SUNXI_FUNCTION(0x1, "gpio_out"),
2942 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */
2943 SUNXI_FUNCTION(0x3, "can"), /* RX */
2944 SUNXI_FUNCTION(0x4, "uart1"), /* RING */
2945 SUNXI_FUNCTION(0x5, "gmac"), /* GNULL / ETXERR */
2946 SUNXI_FUNCTION(0x6, "i2s1")), /* LRCK */
2947 /* Hole */
2948 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
2949 SUNXI_FUNCTION(0x0, "gpio_in"),
2950 SUNXI_FUNCTION(0x1, "gpio_out"),
2951 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
2952 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
2953 SUNXI_FUNCTION(0x0, "gpio_in"),
2954 SUNXI_FUNCTION(0x1, "gpio_out"),
2955 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
2956 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
2957 SUNXI_FUNCTION(0x0, "gpio_in"),
2958 SUNXI_FUNCTION(0x1, "gpio_out"),
2959 SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */
2960 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
2961 SUNXI_FUNCTION(0x0, "gpio_in"),
2962 SUNXI_FUNCTION(0x1, "gpio_out"),
2963 SUNXI_FUNCTION(0x2, "ir0"), /* TX */
2964 SUNXI_FUNCTION(0x4, "spdif")), /* MCLK */
2965 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
2966 SUNXI_FUNCTION(0x0, "gpio_in"),
2967 SUNXI_FUNCTION(0x1, "gpio_out"),
2968 SUNXI_FUNCTION(0x2, "ir0")), /* RX */
2969 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5,
2970 SUNXI_FUNCTION(0x0, "gpio_in"),
2971 SUNXI_FUNCTION(0x1, "gpio_out"),
2972 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
2973 SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */
2974 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6,
2975 SUNXI_FUNCTION(0x0, "gpio_in"),
2976 SUNXI_FUNCTION(0x1, "gpio_out"),
2977 SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
2978 SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */
2979 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7,
2980 SUNXI_FUNCTION(0x0, "gpio_in"),
2981 SUNXI_FUNCTION(0x1, "gpio_out"),
2982 SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */
2983 SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */
2984 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8,
2985 SUNXI_FUNCTION(0x0, "gpio_in"),
2986 SUNXI_FUNCTION(0x1, "gpio_out"),
2987 SUNXI_FUNCTION(0x2, "i2s0"), /* DO0 */
2988 SUNXI_FUNCTION(0x3, "ac97")), /* DO */
2989 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9,
2990 SUNXI_FUNCTION(0x0, "gpio_in"),
2991 SUNXI_FUNCTION(0x1, "gpio_out"),
2992 SUNXI_FUNCTION(0x2, "i2s0")), /* DO1 */
2993 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
2994 SUNXI_FUNCTION(0x0, "gpio_in"),
2995 SUNXI_FUNCTION(0x1, "gpio_out"),
2996 SUNXI_FUNCTION(0x2, "i2s0")), /* DO2 */
2997 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11,
2998 SUNXI_FUNCTION(0x0, "gpio_in"),
2999 SUNXI_FUNCTION(0x1, "gpio_out"),
3000 SUNXI_FUNCTION(0x2, "i2s0")), /* DO3 */
3001 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12,
3002 SUNXI_FUNCTION(0x0, "gpio_in"),
3003 SUNXI_FUNCTION(0x1, "gpio_out"),
3004 SUNXI_FUNCTION(0x2, "i2s0"), /* DI */
3005 SUNXI_FUNCTION(0x3, "ac97"), /* DI */
3006 SUNXI_FUNCTION(0x4, "spdif")), /* DI */
3007 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13,
3008 SUNXI_FUNCTION(0x0, "gpio_in"),
3009 SUNXI_FUNCTION(0x1, "gpio_out"),
3010 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
3011 SUNXI_FUNCTION(0x4, "spdif")), /* DO */
3012 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14,
3013 SUNXI_FUNCTION(0x0, "gpio_in"),
3014 SUNXI_FUNCTION(0x1, "gpio_out"),
3015 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
3016 SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */
3017 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
3018 SUNXI_FUNCTION(0x0, "gpio_in"),
3019 SUNXI_FUNCTION(0x1, "gpio_out"),
3020 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
3021 SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */
3022 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
3023 SUNXI_FUNCTION(0x0, "gpio_in"),
3024 SUNXI_FUNCTION(0x1, "gpio_out"),
3025 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
3026 SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */
3027 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
3028 SUNXI_FUNCTION(0x0, "gpio_in"),
3029 SUNXI_FUNCTION(0x1, "gpio_out"),
3030 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
3031 SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */
3032 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
3033 SUNXI_FUNCTION(0x0, "gpio_in"),
3034 SUNXI_FUNCTION(0x1, "gpio_out"),
3035 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
3036 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19,
3037 SUNXI_FUNCTION(0x0, "gpio_in"),
3038 SUNXI_FUNCTION(0x1, "gpio_out"),
3039 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
3040 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20,
3041 SUNXI_FUNCTION(0x0, "gpio_in"),
3042 SUNXI_FUNCTION(0x1, "gpio_out"),
3043 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
3044 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB21,
3045 SUNXI_FUNCTION(0x0, "gpio_in"),
3046 SUNXI_FUNCTION(0x1, "gpio_out"),
3047 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
3048 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB22,
3049 SUNXI_FUNCTION(0x0, "gpio_in"),
3050 SUNXI_FUNCTION(0x1, "gpio_out"),
3051 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
3052 SUNXI_FUNCTION(0x3, "ir1")), /* TX */
3053 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB23,
3054 SUNXI_FUNCTION(0x0, "gpio_in"),
3055 SUNXI_FUNCTION(0x1, "gpio_out"),
3056 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
3057 SUNXI_FUNCTION(0x3, "ir1")), /* RX */
3058 /* Hole */
3059 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
3060 SUNXI_FUNCTION(0x0, "gpio_in"),
3061 SUNXI_FUNCTION(0x1, "gpio_out"),
3062 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
3063 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
3064 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
3065 SUNXI_FUNCTION(0x0, "gpio_in"),
3066 SUNXI_FUNCTION(0x1, "gpio_out"),
3067 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
3068 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
3069 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
3070 SUNXI_FUNCTION(0x0, "gpio_in"),
3071 SUNXI_FUNCTION(0x1, "gpio_out"),
3072 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
3073 SUNXI_FUNCTION(0x3, "spi0")), /* SCK */
3074 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
3075 SUNXI_FUNCTION(0x0, "gpio_in"),
3076 SUNXI_FUNCTION(0x1, "gpio_out"),
3077 SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */
3078 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
3079 SUNXI_FUNCTION(0x0, "gpio_in"),
3080 SUNXI_FUNCTION(0x1, "gpio_out"),
3081 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
3082 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
3083 SUNXI_FUNCTION(0x0, "gpio_in"),
3084 SUNXI_FUNCTION(0x1, "gpio_out"),
3085 SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */
3086 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
3087 SUNXI_FUNCTION(0x0, "gpio_in"),
3088 SUNXI_FUNCTION(0x1, "gpio_out"),
3089 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
3090 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
3091 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
3092 SUNXI_FUNCTION(0x0, "gpio_in"),
3093 SUNXI_FUNCTION(0x1, "gpio_out"),
3094 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
3095 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
3096 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
3097 SUNXI_FUNCTION(0x0, "gpio_in"),
3098 SUNXI_FUNCTION(0x1, "gpio_out"),
3099 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
3100 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
3101 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
3102 SUNXI_FUNCTION(0x0, "gpio_in"),
3103 SUNXI_FUNCTION(0x1, "gpio_out"),
3104 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
3105 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
3106 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
3107 SUNXI_FUNCTION(0x0, "gpio_in"),
3108 SUNXI_FUNCTION(0x1, "gpio_out"),
3109 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
3110 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
3111 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
3112 SUNXI_FUNCTION(0x0, "gpio_in"),
3113 SUNXI_FUNCTION(0x1, "gpio_out"),
3114 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
3115 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
3116 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
3117 SUNXI_FUNCTION(0x0, "gpio_in"),
3118 SUNXI_FUNCTION(0x1, "gpio_out"),
3119 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */
3120 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
3121 SUNXI_FUNCTION(0x0, "gpio_in"),
3122 SUNXI_FUNCTION(0x1, "gpio_out"),
3123 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */
3124 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
3125 SUNXI_FUNCTION(0x0, "gpio_in"),
3126 SUNXI_FUNCTION(0x1, "gpio_out"),
3127 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */
3128 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
3129 SUNXI_FUNCTION(0x0, "gpio_in"),
3130 SUNXI_FUNCTION(0x1, "gpio_out"),
3131 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */
3132 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16,
3133 SUNXI_FUNCTION(0x0, "gpio_in"),
3134 SUNXI_FUNCTION(0x1, "gpio_out"),
3135 SUNXI_FUNCTION(0x2, "nand0")), /* NWP */
3136 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17,
3137 SUNXI_FUNCTION(0x0, "gpio_in"),
3138 SUNXI_FUNCTION(0x1, "gpio_out"),
3139 SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */
3140 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18,
3141 SUNXI_FUNCTION(0x0, "gpio_in"),
3142 SUNXI_FUNCTION(0x1, "gpio_out"),
3143 SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */
3144 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
3145 SUNXI_FUNCTION(0x0, "gpio_in"),
3146 SUNXI_FUNCTION(0x1, "gpio_out"),
3147 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
3148 SUNXI_FUNCTION(0x3, "spi2"), /* CS0 */
3149 SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
3150 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20,
3151 SUNXI_FUNCTION(0x0, "gpio_in"),
3152 SUNXI_FUNCTION(0x1, "gpio_out"),
3153 SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */
3154 SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
3155 SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */
3156 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21,
3157 SUNXI_FUNCTION(0x0, "gpio_in"),
3158 SUNXI_FUNCTION(0x1, "gpio_out"),
3159 SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */
3160 SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
3161 SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
3162 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22,
3163 SUNXI_FUNCTION(0x0, "gpio_in"),
3164 SUNXI_FUNCTION(0x1, "gpio_out"),
3165 SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */
3166 SUNXI_FUNCTION(0x3, "spi2"), /* MISO */
3167 SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
3168 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23,
3169 SUNXI_FUNCTION(0x0, "gpio_in"),
3170 SUNXI_FUNCTION(0x1, "gpio_out"),
3171 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
3172 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24,
3173 SUNXI_FUNCTION(0x0, "gpio_in"),
3174 SUNXI_FUNCTION(0x1, "gpio_out"),
3175 SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */
3176 /* Hole */
3177 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0,
3178 SUNXI_FUNCTION(0x0, "gpio_in"),
3179 SUNXI_FUNCTION(0x1, "gpio_out"),
3180 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
3181 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
3182 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1,
3183 SUNXI_FUNCTION(0x0, "gpio_in"),
3184 SUNXI_FUNCTION(0x1, "gpio_out"),
3185 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
3186 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
3187 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
3188 SUNXI_FUNCTION(0x0, "gpio_in"),
3189 SUNXI_FUNCTION(0x1, "gpio_out"),
3190 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
3191 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
3192 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
3193 SUNXI_FUNCTION(0x0, "gpio_in"),
3194 SUNXI_FUNCTION(0x1, "gpio_out"),
3195 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
3196 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
3197 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
3198 SUNXI_FUNCTION(0x0, "gpio_in"),
3199 SUNXI_FUNCTION(0x1, "gpio_out"),
3200 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
3201 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
3202 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
3203 SUNXI_FUNCTION(0x0, "gpio_in"),
3204 SUNXI_FUNCTION(0x1, "gpio_out"),
3205 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
3206 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
3207 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
3208 SUNXI_FUNCTION(0x0, "gpio_in"),
3209 SUNXI_FUNCTION(0x1, "gpio_out"),
3210 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
3211 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
3212 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
3213 SUNXI_FUNCTION(0x0, "gpio_in"),
3214 SUNXI_FUNCTION(0x1, "gpio_out"),
3215 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
3216 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
3217 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8,
3218 SUNXI_FUNCTION(0x0, "gpio_in"),
3219 SUNXI_FUNCTION(0x1, "gpio_out"),
3220 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
3221 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
3222 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9,
3223 SUNXI_FUNCTION(0x0, "gpio_in"),
3224 SUNXI_FUNCTION(0x1, "gpio_out"),
3225 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
3226 SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */
3227 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
3228 SUNXI_FUNCTION(0x0, "gpio_in"),
3229 SUNXI_FUNCTION(0x1, "gpio_out"),
3230 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
3231 SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */
3232 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
3233 SUNXI_FUNCTION(0x0, "gpio_in"),
3234 SUNXI_FUNCTION(0x1, "gpio_out"),
3235 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
3236 SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */
3237 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
3238 SUNXI_FUNCTION(0x0, "gpio_in"),
3239 SUNXI_FUNCTION(0x1, "gpio_out"),
3240 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
3241 SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */
3242 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
3243 SUNXI_FUNCTION(0x0, "gpio_in"),
3244 SUNXI_FUNCTION(0x1, "gpio_out"),
3245 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
3246 SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */
3247 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
3248 SUNXI_FUNCTION(0x0, "gpio_in"),
3249 SUNXI_FUNCTION(0x1, "gpio_out"),
3250 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
3251 SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */
3252 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
3253 SUNXI_FUNCTION(0x0, "gpio_in"),
3254 SUNXI_FUNCTION(0x1, "gpio_out"),
3255 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
3256 SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */
3257 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16,
3258 SUNXI_FUNCTION(0x0, "gpio_in"),
3259 SUNXI_FUNCTION(0x1, "gpio_out"),
3260 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
3261 SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */
3262 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17,
3263 SUNXI_FUNCTION(0x0, "gpio_in"),
3264 SUNXI_FUNCTION(0x1, "gpio_out"),
3265 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
3266 SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */
3267 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
3268 SUNXI_FUNCTION(0x0, "gpio_in"),
3269 SUNXI_FUNCTION(0x1, "gpio_out"),
3270 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
3271 SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */
3272 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
3273 SUNXI_FUNCTION(0x0, "gpio_in"),
3274 SUNXI_FUNCTION(0x1, "gpio_out"),
3275 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
3276 SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */
3277 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
3278 SUNXI_FUNCTION(0x0, "gpio_in"),
3279 SUNXI_FUNCTION(0x1, "gpio_out"),
3280 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
3281 SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */
3282 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
3283 SUNXI_FUNCTION(0x0, "gpio_in"),
3284 SUNXI_FUNCTION(0x1, "gpio_out"),
3285 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
3286 SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */
3287 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
3288 SUNXI_FUNCTION(0x0, "gpio_in"),
3289 SUNXI_FUNCTION(0x1, "gpio_out"),
3290 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
3291 SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */
3292 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
3293 SUNXI_FUNCTION(0x0, "gpio_in"),
3294 SUNXI_FUNCTION(0x1, "gpio_out"),
3295 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
3296 SUNXI_FUNCTION(0x3, "sim")), /* DET */
3297 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
3298 SUNXI_FUNCTION(0x0, "gpio_in"),
3299 SUNXI_FUNCTION(0x1, "gpio_out"),
3300 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
3301 SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */
3302 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
3303 SUNXI_FUNCTION(0x0, "gpio_in"),
3304 SUNXI_FUNCTION(0x1, "gpio_out"),
3305 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
3306 SUNXI_FUNCTION(0x3, "sim")), /* RST */
3307 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
3308 SUNXI_FUNCTION(0x0, "gpio_in"),
3309 SUNXI_FUNCTION(0x1, "gpio_out"),
3310 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
3311 SUNXI_FUNCTION(0x3, "sim")), /* SCK */
3312 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
3313 SUNXI_FUNCTION(0x0, "gpio_in"),
3314 SUNXI_FUNCTION(0x1, "gpio_out"),
3315 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
3316 SUNXI_FUNCTION(0x3, "sim")), /* SDA */
3317 /* Hole */
3318 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
3319 SUNXI_FUNCTION(0x0, "gpio_in"),
3320 SUNXI_FUNCTION(0x1, "gpio_out"),
3321 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
3322 SUNXI_FUNCTION(0x3, "csi0")), /* PCK */
3323 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
3324 SUNXI_FUNCTION(0x0, "gpio_in"),
3325 SUNXI_FUNCTION(0x1, "gpio_out"),
3326 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
3327 SUNXI_FUNCTION(0x3, "csi0")), /* CK */
3328 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
3329 SUNXI_FUNCTION(0x0, "gpio_in"),
3330 SUNXI_FUNCTION(0x1, "gpio_out"),
3331 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
3332 SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */
3333 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
3334 SUNXI_FUNCTION(0x0, "gpio_in"),
3335 SUNXI_FUNCTION(0x1, "gpio_out"),
3336 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
3337 SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */
3338 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
3339 SUNXI_FUNCTION(0x0, "gpio_in"),
3340 SUNXI_FUNCTION(0x1, "gpio_out"),
3341 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
3342 SUNXI_FUNCTION(0x3, "csi0")), /* D0 */
3343 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
3344 SUNXI_FUNCTION(0x0, "gpio_in"),
3345 SUNXI_FUNCTION(0x1, "gpio_out"),
3346 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
3347 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
3348 SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */
3349 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
3350 SUNXI_FUNCTION(0x0, "gpio_in"),
3351 SUNXI_FUNCTION(0x1, "gpio_out"),
3352 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
3353 SUNXI_FUNCTION(0x3, "csi0")), /* D2 */
3354 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
3355 SUNXI_FUNCTION(0x0, "gpio_in"),
3356 SUNXI_FUNCTION(0x1, "gpio_out"),
3357 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
3358 SUNXI_FUNCTION(0x3, "csi0")), /* D3 */
3359 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
3360 SUNXI_FUNCTION(0x0, "gpio_in"),
3361 SUNXI_FUNCTION(0x1, "gpio_out"),
3362 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
3363 SUNXI_FUNCTION(0x3, "csi0")), /* D4 */
3364 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
3365 SUNXI_FUNCTION(0x0, "gpio_in"),
3366 SUNXI_FUNCTION(0x1, "gpio_out"),
3367 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
3368 SUNXI_FUNCTION(0x3, "csi0")), /* D5 */
3369 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
3370 SUNXI_FUNCTION(0x0, "gpio_in"),
3371 SUNXI_FUNCTION(0x1, "gpio_out"),
3372 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
3373 SUNXI_FUNCTION(0x3, "csi0")), /* D6 */
3374 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
3375 SUNXI_FUNCTION(0x0, "gpio_in"),
3376 SUNXI_FUNCTION(0x1, "gpio_out"),
3377 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
3378 SUNXI_FUNCTION(0x3, "csi0")), /* D7 */
3379 /* Hole */
3380 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
3381 SUNXI_FUNCTION(0x0, "gpio_in"),
3382 SUNXI_FUNCTION(0x1, "gpio_out"),
3383 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
3384 SUNXI_FUNCTION(0x4, "jtag")), /* MSI */
3385 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
3386 SUNXI_FUNCTION(0x0, "gpio_in"),
3387 SUNXI_FUNCTION(0x1, "gpio_out"),
3388 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
3389 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
3390 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
3391 SUNXI_FUNCTION(0x0, "gpio_in"),
3392 SUNXI_FUNCTION(0x1, "gpio_out"),
3393 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
3394 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
3395 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
3396 SUNXI_FUNCTION(0x0, "gpio_in"),
3397 SUNXI_FUNCTION(0x1, "gpio_out"),
3398 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
3399 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
3400 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
3401 SUNXI_FUNCTION(0x0, "gpio_in"),
3402 SUNXI_FUNCTION(0x1, "gpio_out"),
3403 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
3404 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
3405 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
3406 SUNXI_FUNCTION(0x0, "gpio_in"),
3407 SUNXI_FUNCTION(0x1, "gpio_out"),
3408 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
3409 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
3410 /* Hole */
3411 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
3412 SUNXI_FUNCTION(0x0, "gpio_in"),
3413 SUNXI_FUNCTION(0x1, "gpio_out"),
3414 SUNXI_FUNCTION(0x2, "ts1"), /* CLK */
3415 SUNXI_FUNCTION(0x3, "csi1"), /* PCK */
3416 SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */
3417 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
3418 SUNXI_FUNCTION(0x0, "gpio_in"),
3419 SUNXI_FUNCTION(0x1, "gpio_out"),
3420 SUNXI_FUNCTION(0x2, "ts1"), /* ERR */
3421 SUNXI_FUNCTION(0x3, "csi1"), /* CK */
3422 SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */
3423 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
3424 SUNXI_FUNCTION(0x0, "gpio_in"),
3425 SUNXI_FUNCTION(0x1, "gpio_out"),
3426 SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */
3427 SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */
3428 SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */
3429 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
3430 SUNXI_FUNCTION(0x0, "gpio_in"),
3431 SUNXI_FUNCTION(0x1, "gpio_out"),
3432 SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */
3433 SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */
3434 SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */
3435 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
3436 SUNXI_FUNCTION(0x0, "gpio_in"),
3437 SUNXI_FUNCTION(0x1, "gpio_out"),
3438 SUNXI_FUNCTION(0x2, "ts1"), /* D0 */
3439 SUNXI_FUNCTION(0x3, "csi1"), /* D0 */
3440 SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */
3441 SUNXI_FUNCTION(0x5, "csi0")), /* D8 */
3442 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5,
3443 SUNXI_FUNCTION(0x0, "gpio_in"),
3444 SUNXI_FUNCTION(0x1, "gpio_out"),
3445 SUNXI_FUNCTION(0x2, "ts1"), /* D1 */
3446 SUNXI_FUNCTION(0x3, "csi1"), /* D1 */
3447 SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */
3448 SUNXI_FUNCTION(0x5, "csi0")), /* D9 */
3449 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6,
3450 SUNXI_FUNCTION(0x0, "gpio_in"),
3451 SUNXI_FUNCTION(0x1, "gpio_out"),
3452 SUNXI_FUNCTION(0x2, "ts1"), /* D2 */
3453 SUNXI_FUNCTION(0x3, "csi1"), /* D2 */
3454 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
3455 SUNXI_FUNCTION(0x5, "csi0")), /* D10 */
3456 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7,
3457 SUNXI_FUNCTION(0x0, "gpio_in"),
3458 SUNXI_FUNCTION(0x1, "gpio_out"),
3459 SUNXI_FUNCTION(0x2, "ts1"), /* D3 */
3460 SUNXI_FUNCTION(0x3, "csi1"), /* D3 */
3461 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
3462 SUNXI_FUNCTION(0x5, "csi0")), /* D11 */
3463 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8,
3464 SUNXI_FUNCTION(0x0, "gpio_in"),
3465 SUNXI_FUNCTION(0x1, "gpio_out"),
3466 SUNXI_FUNCTION(0x2, "ts1"), /* D4 */
3467 SUNXI_FUNCTION(0x3, "csi1"), /* D4 */
3468 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
3469 SUNXI_FUNCTION(0x5, "csi0")), /* D12 */
3470 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
3471 SUNXI_FUNCTION(0x0, "gpio_in"),
3472 SUNXI_FUNCTION(0x1, "gpio_out"),
3473 SUNXI_FUNCTION(0x2, "ts1"), /* D5 */
3474 SUNXI_FUNCTION(0x3, "csi1"), /* D5 */
3475 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
3476 SUNXI_FUNCTION(0x5, "csi0")), /* D13 */
3477 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
3478 SUNXI_FUNCTION(0x0, "gpio_in"),
3479 SUNXI_FUNCTION(0x1, "gpio_out"),
3480 SUNXI_FUNCTION(0x2, "ts1"), /* D6 */
3481 SUNXI_FUNCTION(0x3, "csi1"), /* D6 */
3482 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
3483 SUNXI_FUNCTION(0x5, "csi0")), /* D14 */
3484 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
3485 SUNXI_FUNCTION(0x0, "gpio_in"),
3486 SUNXI_FUNCTION(0x1, "gpio_out"),
3487 SUNXI_FUNCTION(0x2, "ts1"), /* D7 */
3488 SUNXI_FUNCTION(0x3, "csi1"), /* D7 */
3489 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
3490 SUNXI_FUNCTION(0x5, "csi0")), /* D15 */
3491 /* Hole */
3492 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0,
3493 SUNXI_FUNCTION(0x0, "gpio_in"),
3494 SUNXI_FUNCTION(0x1, "gpio_out"),
3495 SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */
3496 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
3497 SUNXI_FUNCTION_IRQ(0x6, 0), /* EINT0 */
3498 SUNXI_FUNCTION(0x7, "csi1")), /* D0 */
3499 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1,
3500 SUNXI_FUNCTION(0x0, "gpio_in"),
3501 SUNXI_FUNCTION(0x1, "gpio_out"),
3502 SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */
3503 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
3504 SUNXI_FUNCTION_IRQ(0x6, 1), /* EINT1 */
3505 SUNXI_FUNCTION(0x7, "csi1")), /* D1 */
3506 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2,
3507 SUNXI_FUNCTION(0x0, "gpio_in"),
3508 SUNXI_FUNCTION(0x1, "gpio_out"),
3509 SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */
3510 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
3511 SUNXI_FUNCTION_IRQ(0x6, 2), /* EINT2 */
3512 SUNXI_FUNCTION(0x7, "csi1")), /* D2 */
3513 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3,
3514 SUNXI_FUNCTION(0x0, "gpio_in"),
3515 SUNXI_FUNCTION(0x1, "gpio_out"),
3516 SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */
3517 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
3518 SUNXI_FUNCTION_IRQ(0x6, 3), /* EINT3 */
3519 SUNXI_FUNCTION(0x7, "csi1")), /* D3 */
3520 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4,
3521 SUNXI_FUNCTION(0x0, "gpio_in"),
3522 SUNXI_FUNCTION(0x1, "gpio_out"),
3523 SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */
3524 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
3525 SUNXI_FUNCTION_IRQ(0x6, 4), /* EINT4 */
3526 SUNXI_FUNCTION(0x7, "csi1")), /* D4 */
3527 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5,
3528 SUNXI_FUNCTION(0x0, "gpio_in"),
3529 SUNXI_FUNCTION(0x1, "gpio_out"),
3530 SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */
3531 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
3532 SUNXI_FUNCTION_IRQ(0x6, 5), /* EINT5 */
3533 SUNXI_FUNCTION(0x7, "csi1")), /* D5 */
3534 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6,
3535 SUNXI_FUNCTION(0x0, "gpio_in"),
3536 SUNXI_FUNCTION(0x1, "gpio_out"),
3537 SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */
3538 SUNXI_FUNCTION(0x4, "uart5"), /* TX */
3539 SUNXI_FUNCTION(0x5, "ms"), /* BS */
3540 SUNXI_FUNCTION_IRQ(0x6, 6), /* EINT6 */
3541 SUNXI_FUNCTION(0x7, "csi1")), /* D6 */
3542 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7,
3543 SUNXI_FUNCTION(0x0, "gpio_in"),
3544 SUNXI_FUNCTION(0x1, "gpio_out"),
3545 SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */
3546 SUNXI_FUNCTION(0x4, "uart5"), /* RX */
3547 SUNXI_FUNCTION(0x5, "ms"), /* CLK */
3548 SUNXI_FUNCTION_IRQ(0x6, 7), /* EINT7 */
3549 SUNXI_FUNCTION(0x7, "csi1")), /* D7 */
3550 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8,
3551 SUNXI_FUNCTION(0x0, "gpio_in"),
3552 SUNXI_FUNCTION(0x1, "gpio_out"),
3553 SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */
3554 SUNXI_FUNCTION(0x3, "emac"), /* ERXD3 */
3555 SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */
3556 SUNXI_FUNCTION(0x5, "ms"), /* D0 */
3557 SUNXI_FUNCTION_IRQ(0x6, 8), /* EINT8 */
3558 SUNXI_FUNCTION(0x7, "csi1")), /* D8 */
3559 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9,
3560 SUNXI_FUNCTION(0x0, "gpio_in"),
3561 SUNXI_FUNCTION(0x1, "gpio_out"),
3562 SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */
3563 SUNXI_FUNCTION(0x3, "emac"), /* ERXD2 */
3564 SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */
3565 SUNXI_FUNCTION(0x5, "ms"), /* D1 */
3566 SUNXI_FUNCTION_IRQ(0x6, 9), /* EINT9 */
3567 SUNXI_FUNCTION(0x7, "csi1")), /* D9 */
3568 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10,
3569 SUNXI_FUNCTION(0x0, "gpio_in"),
3570 SUNXI_FUNCTION(0x1, "gpio_out"),
3571 SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */
3572 SUNXI_FUNCTION(0x3, "emac"), /* ERXD1 */
3573 SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */
3574 SUNXI_FUNCTION(0x5, "ms"), /* D2 */
3575 SUNXI_FUNCTION_IRQ(0x6, 10), /* EINT10 */
3576 SUNXI_FUNCTION(0x7, "csi1")), /* D10 */
3577 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11,
3578 SUNXI_FUNCTION(0x0, "gpio_in"),
3579 SUNXI_FUNCTION(0x1, "gpio_out"),
3580 SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */
3581 SUNXI_FUNCTION(0x3, "emac"), /* ERXD0 */
3582 SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */
3583 SUNXI_FUNCTION(0x5, "ms"), /* D3 */
3584 SUNXI_FUNCTION_IRQ(0x6, 11), /* EINT11 */
3585 SUNXI_FUNCTION(0x7, "csi1")), /* D11 */
3586 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12,
3587 SUNXI_FUNCTION(0x0, "gpio_in"),
3588 SUNXI_FUNCTION(0x1, "gpio_out"),
3589 SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */
3590 SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */
3591 SUNXI_FUNCTION_IRQ(0x6, 12), /* EINT12 */
3592 SUNXI_FUNCTION(0x7, "csi1")), /* D12 */
3593 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13,
3594 SUNXI_FUNCTION(0x0, "gpio_in"),
3595 SUNXI_FUNCTION(0x1, "gpio_out"),
3596 SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */
3597 SUNXI_FUNCTION(0x4, "ps2"), /* SDA1 */
3598 SUNXI_FUNCTION(0x5, "sim"), /* RST */
3599 SUNXI_FUNCTION_IRQ(0x6, 13), /* EINT13 */
3600 SUNXI_FUNCTION(0x7, "csi1")), /* D13 */
3601 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14,
3602 SUNXI_FUNCTION(0x0, "gpio_in"),
3603 SUNXI_FUNCTION(0x1, "gpio_out"),
3604 SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */
3605 SUNXI_FUNCTION(0x3, "emac"), /* ETXD3 */
3606 SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */
3607 SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */
3608 SUNXI_FUNCTION_IRQ(0x6, 14), /* EINT14 */
3609 SUNXI_FUNCTION(0x7, "csi1")), /* D14 */
3610 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15,
3611 SUNXI_FUNCTION(0x0, "gpio_in"),
3612 SUNXI_FUNCTION(0x1, "gpio_out"),
3613 SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */
3614 SUNXI_FUNCTION(0x3, "emac"), /* ETXD3 */
3615 SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */
3616 SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */
3617 SUNXI_FUNCTION_IRQ(0x6, 15), /* EINT15 */
3618 SUNXI_FUNCTION(0x7, "csi1")), /* D15 */
3619 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16,
3620 SUNXI_FUNCTION(0x0, "gpio_in"),
3621 SUNXI_FUNCTION(0x1, "gpio_out"),
3622 SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */
3623 SUNXI_FUNCTION(0x3, "emac"), /* ETXD2 */
3624 SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */
3625 SUNXI_FUNCTION_IRQ(0x6, 16), /* EINT16 */
3626 SUNXI_FUNCTION(0x7, "csi1")), /* D16 */
3627 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17,
3628 SUNXI_FUNCTION(0x0, "gpio_in"),
3629 SUNXI_FUNCTION(0x1, "gpio_out"),
3630 SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */
3631 SUNXI_FUNCTION(0x3, "emac"), /* ETXD1 */
3632 SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */
3633 SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */
3634 SUNXI_FUNCTION_IRQ(0x6, 17), /* EINT17 */
3635 SUNXI_FUNCTION(0x7, "csi1")), /* D17 */
3636 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18,
3637 SUNXI_FUNCTION(0x0, "gpio_in"),
3638 SUNXI_FUNCTION(0x1, "gpio_out"),
3639 SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */
3640 SUNXI_FUNCTION(0x3, "emac"), /* ETXD0 */
3641 SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */
3642 SUNXI_FUNCTION(0x5, "sim"), /* SCK */
3643 SUNXI_FUNCTION_IRQ(0x6, 18), /* EINT18 */
3644 SUNXI_FUNCTION(0x7, "csi1")), /* D18 */
3645 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19,
3646 SUNXI_FUNCTION(0x0, "gpio_in"),
3647 SUNXI_FUNCTION(0x1, "gpio_out"),
3648 SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */
3649 SUNXI_FUNCTION(0x3, "emac"), /* ERXERR */
3650 SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */
3651 SUNXI_FUNCTION(0x5, "sim"), /* SDA */
3652 SUNXI_FUNCTION_IRQ(0x6, 19), /* EINT19 */
3653 SUNXI_FUNCTION(0x7, "csi1")), /* D19 */
3654 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20,
3655 SUNXI_FUNCTION(0x0, "gpio_in"),
3656 SUNXI_FUNCTION(0x1, "gpio_out"),
3657 SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */
3658 SUNXI_FUNCTION(0x3, "emac"), /* ERXDV */
3659 SUNXI_FUNCTION(0x4, "can"), /* TX */
3660 SUNXI_FUNCTION_IRQ(0x6, 20), /* EINT20 */
3661 SUNXI_FUNCTION(0x7, "csi1")), /* D20 */
3662 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21,
3663 SUNXI_FUNCTION(0x0, "gpio_in"),
3664 SUNXI_FUNCTION(0x1, "gpio_out"),
3665 SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */
3666 SUNXI_FUNCTION(0x3, "emac"), /* EMDC */
3667 SUNXI_FUNCTION(0x4, "can"), /* RX */
3668 SUNXI_FUNCTION_IRQ(0x6, 21), /* EINT21 */
3669 SUNXI_FUNCTION(0x7, "csi1")), /* D21 */
3670 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22,
3671 SUNXI_FUNCTION(0x0, "gpio_in"),
3672 SUNXI_FUNCTION(0x1, "gpio_out"),
3673 SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */
3674 SUNXI_FUNCTION(0x3, "emac"), /* EMDIO */
3675 SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */
3676 SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */
3677 SUNXI_FUNCTION(0x7, "csi1")), /* D22 */
3678 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23,
3679 SUNXI_FUNCTION(0x0, "gpio_in"),
3680 SUNXI_FUNCTION(0x1, "gpio_out"),
3681 SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */
3682 SUNXI_FUNCTION(0x3, "emac"), /* ETXEN */
3683 SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */
3684 SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */
3685 SUNXI_FUNCTION(0x7, "csi1")), /* D23 */
3686 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24,
3687 SUNXI_FUNCTION(0x0, "gpio_in"),
3688 SUNXI_FUNCTION(0x1, "gpio_out"),
3689 SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */
3690 SUNXI_FUNCTION(0x3, "emac"), /* ETXCK */
3691 SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */
3692 SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */
3693 SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */
3694 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25,
3695 SUNXI_FUNCTION(0x0, "gpio_in"),
3696 SUNXI_FUNCTION(0x1, "gpio_out"),
3697 SUNXI_FUNCTION(0x2, "lcd1"), /* DE */
3698 SUNXI_FUNCTION(0x3, "emac"), /* ECRS */
3699 SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */
3700 SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */
3701 SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */
3702 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26,
3703 SUNXI_FUNCTION(0x0, "gpio_in"),
3704 SUNXI_FUNCTION(0x1, "gpio_out"),
3705 SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */
3706 SUNXI_FUNCTION(0x3, "emac"), /* ECOL */
3707 SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */
3708 SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */
3709 SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */
3710 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27,
3711 SUNXI_FUNCTION(0x0, "gpio_in"),
3712 SUNXI_FUNCTION(0x1, "gpio_out"),
3713 SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */
3714 SUNXI_FUNCTION(0x3, "emac"), /* ETXERR */
3715 SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */
3716 SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */
3717 SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */
3718 /* Hole */
3719 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI0,
3720 SUNXI_FUNCTION(0x0, "gpio_in"),
3721 SUNXI_FUNCTION(0x1, "gpio_out"),
3722 SUNXI_FUNCTION(0x3, "i2c3")), /* SCK */
3723 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI1,
3724 SUNXI_FUNCTION(0x0, "gpio_in"),
3725 SUNXI_FUNCTION(0x1, "gpio_out"),
3726 SUNXI_FUNCTION(0x3, "i2c3")), /* SDA */
3727 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI2,
3728 SUNXI_FUNCTION(0x0, "gpio_in"),
3729 SUNXI_FUNCTION(0x1, "gpio_out"),
3730 SUNXI_FUNCTION(0x3, "i2c4")), /* SCK */
3731 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI3,
3732 SUNXI_FUNCTION(0x0, "gpio_in"),
3733 SUNXI_FUNCTION(0x1, "gpio_out"),
3734 SUNXI_FUNCTION(0x2, "pwm"), /* PWM1 */
3735 SUNXI_FUNCTION(0x3, "i2c4")), /* SDA */
3736 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI4,
3737 SUNXI_FUNCTION(0x0, "gpio_in"),
3738 SUNXI_FUNCTION(0x1, "gpio_out"),
3739 SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */
3740 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI5,
3741 SUNXI_FUNCTION(0x0, "gpio_in"),
3742 SUNXI_FUNCTION(0x1, "gpio_out"),
3743 SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */
3744 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI6,
3745 SUNXI_FUNCTION(0x0, "gpio_in"),
3746 SUNXI_FUNCTION(0x1, "gpio_out"),
3747 SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */
3748 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI7,
3749 SUNXI_FUNCTION(0x0, "gpio_in"),
3750 SUNXI_FUNCTION(0x1, "gpio_out"),
3751 SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */
3752 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI8,
3753 SUNXI_FUNCTION(0x0, "gpio_in"),
3754 SUNXI_FUNCTION(0x1, "gpio_out"),
3755 SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */
3756 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI9,
3757 SUNXI_FUNCTION(0x0, "gpio_in"),
3758 SUNXI_FUNCTION(0x1, "gpio_out"),
3759 SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */
3760 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI10,
3761 SUNXI_FUNCTION(0x0, "gpio_in"),
3762 SUNXI_FUNCTION(0x1, "gpio_out"),
3763 SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
3764 SUNXI_FUNCTION(0x3, "uart5"), /* TX */
3765 SUNXI_FUNCTION_IRQ(0x5, 22)), /* EINT22 */
3766 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI11,
3767 SUNXI_FUNCTION(0x0, "gpio_in"),
3768 SUNXI_FUNCTION(0x1, "gpio_out"),
3769 SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
3770 SUNXI_FUNCTION(0x3, "uart5"), /* RX */
3771 SUNXI_FUNCTION_IRQ(0x5, 23)), /* EINT23 */
3772 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI12,
3773 SUNXI_FUNCTION(0x0, "gpio_in"),
3774 SUNXI_FUNCTION(0x1, "gpio_out"),
3775 SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
3776 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
Chen-Yu Tsaib6a32a22013-12-30 11:25:48 +0800[diff] [blame^]3777 SUNXI_FUNCTION(0x4, "clk_out_a"), /* CLK_OUT_A */
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]3778 SUNXI_FUNCTION_IRQ(0x5, 24)), /* EINT24 */
3779 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13,
3780 SUNXI_FUNCTION(0x0, "gpio_in"),
3781 SUNXI_FUNCTION(0x1, "gpio_out"),
3782 SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
3783 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
Chen-Yu Tsaib6a32a22013-12-30 11:25:48 +0800[diff] [blame^]3784 SUNXI_FUNCTION(0x4, "clk_out_b"), /* CLK_OUT_B */
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]3785 SUNXI_FUNCTION_IRQ(0x5, 25)), /* EINT25 */
3786 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14,
3787 SUNXI_FUNCTION(0x0, "gpio_in"),
3788 SUNXI_FUNCTION(0x1, "gpio_out"),
3789 SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */
3790 SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */
3791 SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */
3792 SUNXI_FUNCTION_IRQ(0x5, 26)), /* EINT26 */
3793 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI15,
3794 SUNXI_FUNCTION(0x0, "gpio_in"),
3795 SUNXI_FUNCTION(0x1, "gpio_out"),
3796 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
3797 SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */
3798 SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */
3799 SUNXI_FUNCTION_IRQ(0x5, 27)), /* EINT27 */
3800 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI16,
3801 SUNXI_FUNCTION(0x0, "gpio_in"),
3802 SUNXI_FUNCTION(0x1, "gpio_out"),
3803 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
3804 SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
3805 SUNXI_FUNCTION_IRQ(0x5, 28)), /* EINT28 */
3806 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI17,
3807 SUNXI_FUNCTION(0x0, "gpio_in"),
3808 SUNXI_FUNCTION(0x1, "gpio_out"),
3809 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
3810 SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
3811 SUNXI_FUNCTION_IRQ(0x5, 29)), /* EINT29 */
3812 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI18,
3813 SUNXI_FUNCTION(0x0, "gpio_in"),
3814 SUNXI_FUNCTION(0x1, "gpio_out"),
3815 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
3816 SUNXI_FUNCTION(0x3, "uart2"), /* TX */
3817 SUNXI_FUNCTION_IRQ(0x5, 30)), /* EINT30 */
3818 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI19,
3819 SUNXI_FUNCTION(0x0, "gpio_in"),
3820 SUNXI_FUNCTION(0x1, "gpio_out"),
3821 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
3822 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
3823 SUNXI_FUNCTION_IRQ(0x5, 31)), /* EINT31 */
3824 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI20,
3825 SUNXI_FUNCTION(0x0, "gpio_in"),
3826 SUNXI_FUNCTION(0x1, "gpio_out"),
3827 SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */
3828 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
3829 SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */
3830 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI21,
3831 SUNXI_FUNCTION(0x0, "gpio_in"),
3832 SUNXI_FUNCTION(0x1, "gpio_out"),
3833 SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */
3834 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
3835 SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */
3836};
3837
Maxime Ripard44abb932013-06-09 18:36:03 +0200[diff] [blame]3838static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = {
3839 .pins = sun4i_a10_pins,
3840 .npins = ARRAY_SIZE(sun4i_a10_pins),
3841};
3842
Maxime Ripardac689362013-06-09 18:36:04 +0200[diff] [blame]3843static const struct sunxi_pinctrl_desc sun5i_a10s_pinctrl_data = {
3844 .pins = sun5i_a10s_pins,
3845 .npins = ARRAY_SIZE(sun5i_a10s_pins),
3846};
3847
Maxime Ripard44abb932013-06-09 18:36:03 +0200[diff] [blame]3848static const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_data = {
3849 .pins = sun5i_a13_pins,
3850 .npins = ARRAY_SIZE(sun5i_a13_pins),
3851};
3852
Maxime Ripardde0c9022013-08-04 11:47:34 +0200[diff] [blame]3853static const struct sunxi_pinctrl_desc sun6i_a31_pinctrl_data = {
3854 .pins = sun6i_a31_pins,
3855 .npins = ARRAY_SIZE(sun6i_a31_pins),
3856};
3857
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]3858static const struct sunxi_pinctrl_desc sun7i_a20_pinctrl_data = {
3859 .pins = sun7i_a20_pins,
3860 .npins = ARRAY_SIZE(sun7i_a20_pins),
3861};
3862
Maxime Ripard44abb932013-06-09 18:36:03 +0200[diff] [blame]3863#endif /* __PINCTRL_SUNXI_PINS_H */