blob: 1121b3934cb90a2fa04b9bb19351e210732ccc96 [file] [log] [blame]
Vinod Koula13ae5a2020-11-26 12:58:39 +05301# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx55.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Global Clock & Reset Controller Binding for SDX55
8
9maintainers:
10 - Vinod Koul <vkoul@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
12
13description: |
14 Qualcomm global clock control module which supports the clocks, resets and
15 power domains on SDX55
16
17 See also:
18 - dt-bindings/clock/qcom,gcc-sdx55.h
19
20properties:
21 compatible:
22 const: qcom,gcc-sdx55
23
24 clocks:
25 items:
26 - description: Board XO source
27 - description: Sleep clock source
28 - description: PLL test clock source (Optional clock)
29 minItems: 2
30 maxItems: 3
31
32 clock-names:
33 items:
34 - const: bi_tcxo
35 - const: sleep_clk
36 - const: core_bi_pll_test_se # Optional clock
37 minItems: 2
38 maxItems: 3
39
40 '#clock-cells':
41 const: 1
42
43 '#reset-cells':
44 const: 1
45
46 '#power-domain-cells':
47 const: 1
48
49 reg:
50 maxItems: 1
51
52required:
53 - compatible
54 - clocks
55 - clock-names
56 - reg
57 - '#clock-cells'
58 - '#reset-cells'
59 - '#power-domain-cells'
60
61additionalProperties: false
62
63examples:
64 - |
65 #include <dt-bindings/clock/qcom,rpmh.h>
66 clock-controller@100000 {
67 compatible = "qcom,gcc-sdx55";
68 reg = <0x00100000 0x1f0000>;
69 clocks = <&rpmhcc RPMH_CXO_CLK>,
70 <&sleep_clk>, <&pll_test_clk>;
71 clock-names = "bi_tcxo", "sleep_clk", "core_bi_pll_test_se";
72 #clock-cells = <1>;
73 #reset-cells = <1>;
74 #power-domain-cells = <1>;
75 };
76
77...