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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / b3253241fd37a45fae2b25a2892145bed323d224 / . / arch / arm / boot / dts / imx6qdl-gw53xx.dtsi
blob: c91b5a6c769bfd5f154ff41c0a6389ccb4184374 [file] [log] [blame]
Tim Harveye3946fe2014-02-07 15:24:56 +0800[diff] [blame]1/*
2 * Copyright 2013 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/ {
13 /* these are used by bootloader for disabling nodes */
14 aliases {
15 can0 = &can1;
16 ethernet0 = &fec;
17 ethernet1 = &eth1;
18 led0 = &led0;
19 led1 = &led1;
20 led2 = &led2;
21 nand = &gpmi;
22 sky2 = &eth1;
23 ssi0 = &ssi1;
24 usb0 = &usbh1;
25 usb1 = &usbotg;
26 usdhc2 = &usdhc3;
27 };
28
29 chosen {
30 bootargs = "console=ttymxc1,115200";
31 };
32
Tim Harveyb3253242014-04-30 23:32:30 -0700[diff] [blame^]33 backlight {
34 compatible = "pwm-backlight";
35 pwms = <&pwm4 0 5000000>;
36 brightness-levels = <0 4 8 16 32 64 128 255>;
37 default-brightness-level = <7>;
38 };
39
Tim Harveye3946fe2014-02-07 15:24:56 +0800[diff] [blame]40 leds {
41 compatible = "gpio-leds";
42
43 led0: user1 {
44 label = "user1";
45 gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */
46 default-state = "on";
47 linux,default-trigger = "heartbeat";
48 };
49
50 led1: user2 {
51 label = "user2";
52 gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */
53 default-state = "off";
54 };
55
56 led2: user3 {
57 label = "user3";
58 gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */
59 default-state = "off";
60 };
61 };
62
63 memory {
64 reg = <0x10000000 0x40000000>;
65 };
66
67 pps {
68 compatible = "pps-gpio";
69 gpios = <&gpio1 26 0>;
70 status = "okay";
71 };
72
73 regulators {
74 compatible = "simple-bus";
75 #address-cells = <1>;
76 #size-cells = <0>;
77
78 reg_1p0v: regulator@0 {
79 compatible = "regulator-fixed";
80 reg = <0>;
81 regulator-name = "1P0V";
82 regulator-min-microvolt = <1000000>;
83 regulator-max-microvolt = <1000000>;
84 regulator-always-on;
85 };
86
87 /* remove when pmic 1p8 regulator available */
88 reg_1p8v: regulator@1 {
89 compatible = "regulator-fixed";
90 reg = <1>;
91 regulator-name = "1P8V";
92 regulator-min-microvolt = <1800000>;
93 regulator-max-microvolt = <1800000>;
94 regulator-always-on;
95 };
96
97 reg_3p3v: regulator@2 {
98 compatible = "regulator-fixed";
99 reg = <2>;
100 regulator-name = "3P3V";
101 regulator-min-microvolt = <3300000>;
102 regulator-max-microvolt = <3300000>;
103 regulator-always-on;
104 };
105
106 reg_usb_h1_vbus: regulator@3 {
107 compatible = "regulator-fixed";
108 reg = <3>;
109 regulator-name = "usb_h1_vbus";
110 regulator-min-microvolt = <5000000>;
111 regulator-max-microvolt = <5000000>;
112 regulator-always-on;
113 };
114
115 reg_usb_otg_vbus: regulator@4 {
116 compatible = "regulator-fixed";
117 reg = <4>;
118 regulator-name = "usb_otg_vbus";
119 regulator-min-microvolt = <5000000>;
120 regulator-max-microvolt = <5000000>;
121 gpio = <&gpio3 22 0>;
122 enable-active-high;
123 };
124 };
125
126 sound {
127 compatible = "fsl,imx6q-sabrelite-sgtl5000",
128 "fsl,imx-audio-sgtl5000";
129 model = "imx6q-sabrelite-sgtl5000";
130 ssi-controller = <&ssi1>;
131 audio-codec = <&codec>;
132 audio-routing =
133 "MIC_IN", "Mic Jack",
134 "Mic Jack", "Mic Bias",
135 "Headphone Jack", "HP_OUT";
136 mux-int-port = <1>;
137 mux-ext-port = <4>;
138 };
139};
140
141&audmux {
142 pinctrl-names = "default";
143 pinctrl-0 = <&pinctrl_audmux>;
144 status = "okay";
145};
146
147&can1 {
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_flexcan1>;
150 status = "okay";
151};
152
153&fec {
154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_enet>;
156 phy-mode = "rgmii";
157 phy-reset-gpios = <&gpio1 30 0>;
158 status = "okay";
159};
160
161&gpmi {
162 pinctrl-names = "default";
163 pinctrl-0 = <&pinctrl_gpmi_nand>;
164 status = "okay";
165};
166
Tim Harveyaef15db2014-04-23 00:47:51 -0700[diff] [blame]167&hdmi {
168 ddc-i2c-bus = <&i2c3>;
169 status = "okay";
170};
171
Tim Harveye3946fe2014-02-07 15:24:56 +0800[diff] [blame]172&i2c1 {
173 clock-frequency = <100000>;
174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_i2c1>;
176 status = "okay";
177
178 eeprom1: eeprom@50 {
179 compatible = "atmel,24c02";
180 reg = <0x50>;
181 pagesize = <16>;
182 };
183
184 eeprom2: eeprom@51 {
185 compatible = "atmel,24c02";
186 reg = <0x51>;
187 pagesize = <16>;
188 };
189
190 eeprom3: eeprom@52 {
191 compatible = "atmel,24c02";
192 reg = <0x52>;
193 pagesize = <16>;
194 };
195
196 eeprom4: eeprom@53 {
197 compatible = "atmel,24c02";
198 reg = <0x53>;
199 pagesize = <16>;
200 };
201
202 gpio: pca9555@23 {
203 compatible = "nxp,pca9555";
204 reg = <0x23>;
205 gpio-controller;
206 #gpio-cells = <2>;
207 };
208
209 hwmon: gsc@29 {
210 compatible = "gw,gsp";
211 reg = <0x29>;
212 };
213
214 rtc: ds1672@68 {
215 compatible = "dallas,ds1672";
216 reg = <0x68>;
217 };
218};
219
220&i2c2 {
221 clock-frequency = <100000>;
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_i2c2>;
224 status = "okay";
225
226 pciclkgen: si53156@6b {
227 compatible = "sil,si53156";
228 reg = <0x6b>;
229 };
230
231 pciswitch: pex8606@3f {
232 compatible = "plx,pex8606";
233 reg = <0x3f>;
234 };
235
236 pmic: ltc3676@3c {
237 compatible = "ltc,ltc3676";
238 reg = <0x3c>;
239
240 regulators {
241 /* VDD_SOC */
242 sw1_reg: ltc3676__sw1 {
243 regulator-min-microvolt = <1175000>;
244 regulator-max-microvolt = <1175000>;
245 regulator-boot-on;
246 regulator-always-on;
247 };
248
249 /* VDD_1P8 */
250 sw2_reg: ltc3676__sw2 {
251 regulator-min-microvolt = <1800000>;
252 regulator-max-microvolt = <1800000>;
253 regulator-boot-on;
254 regulator-always-on;
255 };
256
257 /* VDD_ARM */
258 sw3_reg: ltc3676__sw3 {
259 regulator-min-microvolt = <1175000>;
260 regulator-max-microvolt = <1175000>;
261 regulator-boot-on;
262 regulator-always-on;
263 };
264
265 /* VDD_DDR */
266 sw4_reg: ltc3676__sw4 {
267 regulator-min-microvolt = <1500000>;
268 regulator-max-microvolt = <1500000>;
269 regulator-boot-on;
270 regulator-always-on;
271 };
272
273 /* VDD_2P5 */
274 ldo2_reg: ltc3676__ldo2 {
275 regulator-min-microvolt = <2500000>;
276 regulator-max-microvolt = <2500000>;
277 regulator-boot-on;
278 regulator-always-on;
279 };
280
281 /* VDD_1P8 */
282 ldo3_reg: ltc3676__ldo3 {
283 regulator-min-microvolt = <1800000>;
284 regulator-max-microvolt = <1800000>;
285 regulator-boot-on;
286 regulator-always-on;
287 };
288
289 /* VDD_HIGH */
290 ldo4_reg: ltc3676__ldo4 {
291 regulator-min-microvolt = <3000000>;
292 regulator-max-microvolt = <3000000>;
293 };
294 };
295 };
296};
297
298&i2c3 {
299 clock-frequency = <100000>;
300 pinctrl-names = "default";
301 pinctrl-0 = <&pinctrl_i2c3>;
302 status = "okay";
303
304 accelerometer: fxos8700@1e {
305 compatible = "fsl,fxos8700";
306 reg = <0x1e>;
307 };
308
309 codec: sgtl5000@0a {
310 compatible = "fsl,sgtl5000";
311 reg = <0x0a>;
312 clocks = <&clks 201>;
313 VDDA-supply = <&reg_1p8v>;
314 VDDIO-supply = <&reg_3p3v>;
315 };
316
317 hdmiin: adv7611@4c {
318 compatible = "adi,adv7611";
319 reg = <0x4c>;
320 };
321
322 touchscreen: egalax_ts@04 {
323 compatible = "eeti,egalax_ts";
324 reg = <0x04>;
325 interrupt-parent = <&gpio1>;
326 interrupts = <11 2>; /* gpio1_11 active low */
327 wakeup-gpios = <&gpio1 11 0>;
328 };
329
330 videoout: adv7393@2a {
331 compatible = "adi,adv7393";
332 reg = <0x2a>;
333 };
334
335 videoin: adv7180@20 {
336 compatible = "adi,adv7180";
337 reg = <0x20>;
338 };
339};
340
341&iomuxc {
342 pinctrl-names = "default";
343 pinctrl-0 = <&pinctrl_hog>;
344
345 imx6qdl-gw53xx {
346 pinctrl_hog: hoggrp {
347 fsl,pins = <
348 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* PCIE6EXP_DIO0 */
349 MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* PCIE6EXP_DIO1 */
350 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */
351 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 /* GPS_SHDN */
352 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */
353 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */
354 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */
355 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */
356 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAN_STBY */
357 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x80000000 /* PMIC_IRQ# */
358 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000 /* HUB_RST# */
359 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* PCIE_WDIS# */
360 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000 /* ACCEL_IRQ# */
361 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */
362 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x80000000 /* USBOTG_OC# */
363 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */
364 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */
365 MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x80000000 /* TOUCH_IRQ# */
366 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* SD3_DET# */
367 >;
368 };
369
370 pinctrl_audmux: audmuxgrp {
371 fsl,pins = <
372 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
373 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
374 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
375 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
376 >;
377 };
378
379 pinctrl_enet: enetgrp {
380 fsl,pins = <
381 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
382 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
383 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
384 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
385 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
386 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
387 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
388 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
389 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
390 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
391 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
392 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
393 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
394 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
395 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
396 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
397 >;
398 };
399
400 pinctrl_flexcan1: flexcan1grp {
401 fsl,pins = <
402 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
403 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
404 >;
405 };
406
407 pinctrl_gpmi_nand: gpminandgrp {
408 fsl,pins = <
409 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
410 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
411 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
412 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
413 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
414 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
415 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
416 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
417 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
418 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
419 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
420 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
421 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
422 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
423 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
424 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
425 >;
426 };
427
428 pinctrl_i2c1: i2c1grp {
429 fsl,pins = <
430 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
431 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
432 >;
433 };
434
435 pinctrl_i2c2: i2c2grp {
436 fsl,pins = <
437 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
438 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
439 >;
440 };
441
442 pinctrl_i2c3: i2c3grp {
443 fsl,pins = <
444 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
445 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
446 >;
447 };
448
Tim Harveyb3253242014-04-30 23:32:30 -0700[diff] [blame^]449 pinctrl_pwm4: pwm4grp {
450 fsl,pins = <
451 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
452 >;
453 };
454
Tim Harveye3946fe2014-02-07 15:24:56 +0800[diff] [blame]455 pinctrl_uart1: uart1grp {
456 fsl,pins = <
457 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
458 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
459 >;
460 };
461
462 pinctrl_uart2: uart2grp {
463 fsl,pins = <
464 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
465 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
466 >;
467 };
468
469 pinctrl_uart5: uart5grp {
470 fsl,pins = <
471 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
472 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
473 >;
474 };
475
476 pinctrl_usbotg: usbotggrp {
477 fsl,pins = <
478 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
479 >;
480 };
481
482 pinctrl_usdhc3: usdhc3grp {
483 fsl,pins = <
484 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
485 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
486 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
487 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
488 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
489 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
490 >;
491 };
492 };
493};
494
495&ldb {
496 status = "okay";
497
498 lvds-channel@1 {
499 fsl,data-mapping = "spwg";
500 fsl,data-width = <18>;
501 status = "okay";
502
503 display-timings {
504 native-mode = <&timing0>;
505 timing0: hsd100pxn1 {
506 clock-frequency = <65000000>;
507 hactive = <1024>;
508 vactive = <768>;
509 hback-porch = <220>;
510 hfront-porch = <40>;
511 vback-porch = <21>;
512 vfront-porch = <7>;
513 hsync-len = <60>;
514 vsync-len = <10>;
515 };
516 };
517 };
518};
519
520&pcie {
521 reset-gpio = <&gpio1 29 0>;
522 status = "okay";
523
524 eth1: sky2@8 { /* MAC/PHY on bus 8 */
525 compatible = "marvell,sky2";
526 };
527};
528
Tim Harveyb3253242014-04-30 23:32:30 -0700[diff] [blame^]529&pwm4 {
530 pinctrl-names = "default";
531 pinctrl-0 = <&pinctrl_pwm4>;
532 status = "okay";
533};
534
Tim Harveye3946fe2014-02-07 15:24:56 +0800[diff] [blame]535&ssi1 {
536 fsl,mode = "i2s-slave";
537 status = "okay";
538};
539
540&uart1 {
541 pinctrl-names = "default";
542 pinctrl-0 = <&pinctrl_uart1>;
543 status = "okay";
544};
545
546&uart2 {
547 pinctrl-names = "default";
548 pinctrl-0 = <&pinctrl_uart2>;
549 status = "okay";
550};
551
552&uart5 {
553 pinctrl-names = "default";
554 pinctrl-0 = <&pinctrl_uart5>;
555 status = "okay";
556};
557
558&usbotg {
559 vbus-supply = <&reg_usb_otg_vbus>;
560 pinctrl-names = "default";
561 pinctrl-0 = <&pinctrl_usbotg>;
562 disable-over-current;
563 status = "okay";
564};
565
566&usbh1 {
567 vbus-supply = <&reg_usb_h1_vbus>;
568 status = "okay";
569};
570
571&usdhc3 {
572 pinctrl-names = "default";
573 pinctrl-0 = <&pinctrl_usdhc3>;
574 cd-gpios = <&gpio7 0 0>;
575 vmmc-supply = <&reg_3p3v>;
576 status = "okay";
577};