Thomas Gleixner | f50a7f3 | 2019-05-28 09:57:18 -0700 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Boris BREZILLON | d7d1d45 | 2013-08-07 10:49:01 +0200 | [diff] [blame] | 2 | /* |
Nicolas Ferre | 8dafaa1 | 2015-03-04 17:56:03 +0100 | [diff] [blame] | 3 | * sama5d3_uart.dtsi - Device Tree Include file for SAMA5D3 SoC with |
Boris BREZILLON | d7d1d45 | 2013-08-07 10:49:01 +0200 | [diff] [blame] | 4 | * UART support |
| 5 | * |
| 6 | * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> |
Boris BREZILLON | d7d1d45 | 2013-08-07 10:49:01 +0200 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #include <dt-bindings/pinctrl/at91.h> |
| 10 | #include <dt-bindings/interrupt-controller/irq.h> |
Tushar Behera | 35d35aa | 2014-03-06 11:34:43 +0530 | [diff] [blame] | 11 | #include <dt-bindings/clock/at91.h> |
Boris BREZILLON | d7d1d45 | 2013-08-07 10:49:01 +0200 | [diff] [blame] | 12 | |
| 13 | / { |
Nicolas Ferre | ac0585c | 2013-12-02 17:10:04 +0100 | [diff] [blame] | 14 | aliases { |
| 15 | serial5 = &uart0; |
| 16 | serial6 = &uart1; |
| 17 | }; |
| 18 | |
Boris BREZILLON | d7d1d45 | 2013-08-07 10:49:01 +0200 | [diff] [blame] | 19 | ahb { |
| 20 | apb { |
| 21 | pinctrl@fffff200 { |
| 22 | uart0 { |
| 23 | pinctrl_uart0: uart0-0 { |
| 24 | atmel,pins = |
Peter Rosin | 5e04822 | 2018-03-21 16:35:50 +0100 | [diff] [blame] | 25 | <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* conflicts with PWMFI2, ISI_D8 */ |
| 26 | AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with ISI_PCK */ |
Boris BREZILLON | d7d1d45 | 2013-08-07 10:49:01 +0200 | [diff] [blame] | 27 | }; |
| 28 | }; |
| 29 | |
| 30 | uart1 { |
| 31 | pinctrl_uart1: uart1-0 { |
| 32 | atmel,pins = |
Peter Rosin | 5e04822 | 2018-03-21 16:35:50 +0100 | [diff] [blame] | 33 | <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* conflicts with TWD0, ISI_VSYNC */ |
| 34 | AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with TWCK0, ISI_HSYNC */ |
Boris BREZILLON | d7d1d45 | 2013-08-07 10:49:01 +0200 | [diff] [blame] | 35 | }; |
| 36 | }; |
| 37 | }; |
| 38 | |
| 39 | uart0: serial@f0024000 { |
| 40 | compatible = "atmel,at91sam9260-usart"; |
Peter Rosin | 1c1d369 | 2016-11-10 08:46:40 +0100 | [diff] [blame] | 41 | reg = <0xf0024000 0x100>; |
Boris BREZILLON | d7d1d45 | 2013-08-07 10:49:01 +0200 | [diff] [blame] | 42 | interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; |
| 43 | pinctrl-names = "default"; |
| 44 | pinctrl-0 = <&pinctrl_uart0>; |
Alexandre Belloni | 7ed609b | 2020-01-10 23:27:44 +0100 | [diff] [blame] | 45 | clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 46 | clock-names = "usart"; |
Boris BREZILLON | d7d1d45 | 2013-08-07 10:49:01 +0200 | [diff] [blame] | 47 | status = "disabled"; |
| 48 | }; |
| 49 | |
| 50 | uart1: serial@f8028000 { |
| 51 | compatible = "atmel,at91sam9260-usart"; |
Peter Rosin | 1c1d369 | 2016-11-10 08:46:40 +0100 | [diff] [blame] | 52 | reg = <0xf8028000 0x100>; |
Boris BREZILLON | d7d1d45 | 2013-08-07 10:49:01 +0200 | [diff] [blame] | 53 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; |
| 54 | pinctrl-names = "default"; |
| 55 | pinctrl-0 = <&pinctrl_uart1>; |
Alexandre Belloni | 7ed609b | 2020-01-10 23:27:44 +0100 | [diff] [blame] | 56 | clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 57 | clock-names = "usart"; |
Boris BREZILLON | d7d1d45 | 2013-08-07 10:49:01 +0200 | [diff] [blame] | 58 | status = "disabled"; |
| 59 | }; |
| 60 | }; |
| 61 | }; |
| 62 | }; |