Gitiles
Code Review Sign In
review.shift-gmbh.com / SHIFTPHONES / mainline / linux / b2ffa16a1c837e50a29d43fe93091492693648fe / . / arch / arm / boot / dts / imx51.dtsi
blob: 01cfcbe5928e83a1c7514d8cbd94c461ef85e761 [file] [log] [blame]
Fabio Estevam241f76b2018-05-07 15:23:40 -0300[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2011 Freescale Semiconductor, Inc.
4// Copyright 2011 Linaro Ltd.
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]5
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]6#include "imx51-pinfunc.h"
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]7#include <dt-bindings/clock/imx5-clock.h>
Alexander Shiyanbdb3eec2013-11-19 15:47:27 +0400[diff] [blame]8#include <dt-bindings/gpio/gpio.h>
Alexander Shiyan72d86d22014-01-11 10:54:19 +0400[diff] [blame]9#include <dt-bindings/input/input.h>
10#include <dt-bindings/interrupt-controller/irq.h>
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]11
12/ {
Fabio Estevam7f107882016-11-12 13:30:35 -0200[diff] [blame]13 #address-cells = <1>;
14 #size-cells = <1>;
Fabio Estevama971c552017-01-23 14:54:10 -0200[diff] [blame]15 /*
16 * The decompressor and also some bootloaders rely on a
17 * pre-existing /chosen node to be available to insert the
18 * command line and merge other ATAGS info.
Fabio Estevama971c552017-01-23 14:54:10 -0200[diff] [blame]19 */
20 chosen {};
Fabio Estevam7f107882016-11-12 13:30:35 -0200[diff] [blame]21
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]22 aliases {
Marek Vasut22970072014-02-28 12:58:41 +0100[diff] [blame]23 ethernet0 = &fec;
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]24 gpio0 = &gpio1;
25 gpio1 = &gpio2;
26 gpio2 = &gpio3;
27 gpio3 = &gpio4;
Sascha Hauere3b73c62013-06-25 15:51:55 +0200[diff] [blame]28 i2c0 = &i2c1;
29 i2c1 = &i2c2;
Sascha Hauerf742c222014-01-16 13:44:21 +0100[diff] [blame]30 mmc0 = &esdhc1;
31 mmc1 = &esdhc2;
32 mmc2 = &esdhc3;
33 mmc3 = &esdhc4;
Sascha Hauere3b73c62013-06-25 15:51:55 +0200[diff] [blame]34 serial0 = &uart1;
35 serial1 = &uart2;
36 serial2 = &uart3;
37 spi0 = &ecspi1;
38 spi1 = &ecspi2;
39 spi2 = &cspi;
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]40 };
41
42 tzic: tz-interrupt-controller@e0000000 {
43 compatible = "fsl,imx51-tzic", "fsl,tzic";
44 interrupt-controller;
45 #interrupt-cells = <1>;
46 reg = <0xe0000000 0x4000>;
47 };
48
49 clocks {
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]50 ckil {
51 compatible = "fsl,imx-ckil", "fixed-clock";
Shawn Guo4b2b4042014-04-11 09:56:46 +0800[diff] [blame]52 #clock-cells = <0>;
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]53 clock-frequency = <32768>;
54 };
55
56 ckih1 {
57 compatible = "fsl,imx-ckih1", "fixed-clock";
Shawn Guo4b2b4042014-04-11 09:56:46 +0800[diff] [blame]58 #clock-cells = <0>;
Alexander Shiyan677e28b2013-07-27 11:19:45 +0400[diff] [blame]59 clock-frequency = <0>;
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]60 };
61
62 ckih2 {
63 compatible = "fsl,imx-ckih2", "fixed-clock";
Shawn Guo4b2b4042014-04-11 09:56:46 +0800[diff] [blame]64 #clock-cells = <0>;
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]65 clock-frequency = <0>;
66 };
67
68 osc {
69 compatible = "fsl,imx-osc", "fixed-clock";
Shawn Guo4b2b4042014-04-11 09:56:46 +0800[diff] [blame]70 #clock-cells = <0>;
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]71 clock-frequency = <24000000>;
72 };
73 };
74
Markus Pargmann6f9d62d2013-04-07 21:56:45 +0200[diff] [blame]75 cpus {
76 #address-cells = <1>;
77 #size-cells = <0>;
Alexander Shiyan6acde882013-11-07 12:45:05 +0400[diff] [blame]78 cpu: cpu@0 {
Markus Pargmann6f9d62d2013-04-07 21:56:45 +0200[diff] [blame]79 device_type = "cpu";
80 compatible = "arm,cortex-a8";
81 reg = <0>;
Alexander Shiyan6acde882013-11-07 12:45:05 +0400[diff] [blame]82 clock-latency = <62500>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]83 clocks = <&clks IMX5_CLK_CPU_PODF>;
Markus Pargmann6f9d62d2013-04-07 21:56:45 +0200[diff] [blame]84 clock-names = "cpu";
85 operating-points = <
Alexander Shiyan6acde882013-11-07 12:45:05 +0400[diff] [blame]86 166000 1000000
87 600000 1050000
88 800000 1100000
Markus Pargmann6f9d62d2013-04-07 21:56:45 +0200[diff] [blame]89 >;
Alexander Shiyan6acde882013-11-07 12:45:05 +0400[diff] [blame]90 voltage-tolerance = <5>;
Markus Pargmann6f9d62d2013-04-07 21:56:45 +0200[diff] [blame]91 };
92 };
93
Fabio Estevam4b301222018-07-10 13:31:44 -0300[diff] [blame]94 pmu: pmu {
95 compatible = "arm,cortex-a8-pmu";
96 interrupt-parent = <&tzic>;
97 interrupts = <77>;
98 };
99
Fabio Estevam82210bf2018-07-03 10:05:54 -0300[diff] [blame]100 usbphy0: usbphy0 {
101 compatible = "usb-nop-xceiv";
102 clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
103 clock-names = "main_clk";
104 #phy-cells = <0>;
Sascha Hauerb5af6b12012-11-12 12:56:00 +0100[diff] [blame]105 };
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]106
Philipp Zabel288b9e62020-03-13 11:57:39 +0100[diff] [blame]107 capture-subsystem {
108 compatible = "fsl,imx-capture-subsystem";
109 ports = <&ipu_csi0>, <&ipu_csi1>;
110 };
111
Philipp Zabelde10e042014-03-05 10:20:59 +0100[diff] [blame]112 display-subsystem {
113 compatible = "fsl,imx-display-subsystem";
114 ports = <&ipu_di0>, <&ipu_di1>;
115 };
116
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]117 soc {
118 #address-cells = <1>;
119 #size-cells = <1>;
120 compatible = "simple-bus";
121 interrupt-parent = <&tzic>;
122 ranges;
123
Krzysztof Kozlowski7e28fc42019-10-02 18:43:12 +0200[diff] [blame]124 iram: sram@1ffe0000 {
Alexander Shiyanda38ea32013-08-21 11:28:24 +0400[diff] [blame]125 compatible = "mmio-sram";
126 reg = <0x1ffe0000 0x20000>;
127 };
128
Jonathan Marek006303d2018-12-04 10:17:00 -0500[diff] [blame]129 gpu: gpu@30000000 {
130 compatible = "amd,imageon-200.1", "amd,imageon";
131 reg = <0x30000000 0x20000>;
132 reg-names = "kgsl_3d0_reg_memory";
133 interrupts = <12>;
134 interrupt-names = "kgsl_3d0_irq";
135 clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>;
136 clock-names = "core_clk", "mem_iface_clk";
137 };
138
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]139 ipu: ipu@40000000 {
Philipp Zabelde10e042014-03-05 10:20:59 +0100[diff] [blame]140 #address-cells = <1>;
141 #size-cells = <0>;
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]142 compatible = "fsl,imx51-ipu";
143 reg = <0x40000000 0x20000000>;
144 interrupts = <11 10>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]145 clocks = <&clks IMX5_CLK_IPU_GATE>,
Jagan Teki46311702016-10-26 15:31:01 +0530[diff] [blame]146 <&clks IMX5_CLK_IPU_DI0_GATE>,
147 <&clks IMX5_CLK_IPU_DI1_GATE>;
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]148 clock-names = "bus", "di0", "di1";
149 resets = <&src 2>;
Philipp Zabelde10e042014-03-05 10:20:59 +0100[diff] [blame]150
Philipp Zabel288b9e62020-03-13 11:57:39 +0100[diff] [blame]151 ipu_csi0: port@0 {
152 reg = <0>;
153 };
154
155 ipu_csi1: port@1 {
156 reg = <1>;
157 };
158
Philipp Zabelde10e042014-03-05 10:20:59 +0100[diff] [blame]159 ipu_di0: port@2 {
160 reg = <2>;
161
Marco Franchif7059422017-10-05 11:31:41 -0300[diff] [blame]162 ipu_di0_disp1: endpoint {
Philipp Zabelde10e042014-03-05 10:20:59 +0100[diff] [blame]163 };
164 };
165
166 ipu_di1: port@3 {
167 reg = <3>;
168
Marco Franchif7059422017-10-05 11:31:41 -0300[diff] [blame]169 ipu_di1_disp2: endpoint {
Philipp Zabelde10e042014-03-05 10:20:59 +0100[diff] [blame]170 };
171 };
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]172 };
173
Peng Fanc0157bd2020-02-13 11:17:58 +0800[diff] [blame]174 bus@70000000 { /* AIPS1 */
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]175 compatible = "fsl,aips-bus", "simple-bus";
176 #address-cells = <1>;
177 #size-cells = <1>;
178 reg = <0x70000000 0x10000000>;
179 ranges;
180
181 spba@70000000 {
182 compatible = "fsl,spba-bus", "simple-bus";
183 #address-cells = <1>;
184 #size-cells = <1>;
185 reg = <0x70000000 0x40000>;
186 ranges;
187
Anson Huang7e4cd9d2020-06-02 14:24:51 +0800[diff] [blame]188 esdhc1: mmc@70004000 {
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]189 compatible = "fsl,imx51-esdhc";
190 reg = <0x70004000 0x4000>;
191 interrupts = <1>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]192 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
Jagan Teki46311702016-10-26 15:31:01 +0530[diff] [blame]193 <&clks IMX5_CLK_DUMMY>,
194 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]195 clock-names = "ipg", "ahb", "per";
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]196 status = "disabled";
197 };
198
Anson Huang7e4cd9d2020-06-02 14:24:51 +0800[diff] [blame]199 esdhc2: mmc@70008000 {
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]200 compatible = "fsl,imx51-esdhc";
201 reg = <0x70008000 0x4000>;
202 interrupts = <2>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]203 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
Jagan Teki46311702016-10-26 15:31:01 +0530[diff] [blame]204 <&clks IMX5_CLK_DUMMY>,
205 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]206 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]207 bus-width = <4>;
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]208 status = "disabled";
209 };
210
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]211 uart3: serial@7000c000 {
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]212 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
213 reg = <0x7000c000 0x4000>;
214 interrupts = <33>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]215 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
Jagan Teki46311702016-10-26 15:31:01 +0530[diff] [blame]216 <&clks IMX5_CLK_UART3_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]217 clock-names = "ipg", "per";
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]218 status = "disabled";
219 };
220
Rob Herring5a2ecf02018-09-13 13:12:29 -0500[diff] [blame]221 ecspi1: spi@70010000 {
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]222 #address-cells = <1>;
223 #size-cells = <0>;
224 compatible = "fsl,imx51-ecspi";
225 reg = <0x70010000 0x4000>;
226 interrupts = <36>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]227 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
Jagan Teki46311702016-10-26 15:31:01 +0530[diff] [blame]228 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]229 clock-names = "ipg", "per";
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]230 status = "disabled";
231 };
232
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]233 ssi2: ssi@70014000 {
Alexander Shiyan6ff7f512014-08-19 20:00:09 +0400[diff] [blame]234 #sound-dai-cells = <0>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]235 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
236 reg = <0x70014000 0x4000>;
237 interrupts = <30>;
Fabio Estevam53ec8742014-09-18 20:23:49 -0300[diff] [blame]238 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
239 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
240 clock-names = "ipg", "baud";
Shawn Guo5da826a2013-07-17 13:50:54 +0800[diff] [blame]241 dmas = <&sdma 24 1 0>,
242 <&sdma 25 1 0>;
243 dma-names = "rx", "tx";
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]244 fsl,fifo-depth = <15>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]245 status = "disabled";
246 };
247
Anson Huang7e4cd9d2020-06-02 14:24:51 +0800[diff] [blame]248 esdhc3: mmc@70020000 {
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]249 compatible = "fsl,imx51-esdhc";
250 reg = <0x70020000 0x4000>;
251 interrupts = <3>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]252 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
Jagan Teki46311702016-10-26 15:31:01 +0530[diff] [blame]253 <&clks IMX5_CLK_DUMMY>,
254 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]255 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]256 bus-width = <4>;
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]257 status = "disabled";
258 };
259
Anson Huang7e4cd9d2020-06-02 14:24:51 +0800[diff] [blame]260 esdhc4: mmc@70024000 {
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]261 compatible = "fsl,imx51-esdhc";
262 reg = <0x70024000 0x4000>;
263 interrupts = <4>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]264 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
Jagan Teki46311702016-10-26 15:31:01 +0530[diff] [blame]265 <&clks IMX5_CLK_DUMMY>,
266 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]267 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]268 bus-width = <4>;
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]269 status = "disabled";
270 };
271 };
272
Fabio Estevamba72b5a2018-06-20 15:06:19 -0300[diff] [blame]273 aipstz1: bridge@73f00000 {
274 compatible = "fsl,imx51-aipstz";
275 reg = <0x73f00000 0x60>;
276 };
277
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]278 usbotg: usb@73f80000 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]279 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
280 reg = <0x73f80000 0x0200>;
281 interrupts = <18>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]282 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]283 fsl,usbmisc = <&usbmisc 0>;
Michael Grzeschika79025c2013-04-11 12:13:16 +0200[diff] [blame]284 fsl,usbphy = <&usbphy0>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]285 status = "disabled";
286 };
287
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]288 usbh1: usb@73f80200 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]289 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
290 reg = <0x73f80200 0x0200>;
291 interrupts = <14>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]292 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]293 fsl,usbmisc = <&usbmisc 1>;
Matt Porter3ec481e2015-02-27 09:06:00 -0500[diff] [blame]294 dr_mode = "host";
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]295 status = "disabled";
296 };
297
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]298 usbh2: usb@73f80400 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]299 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
300 reg = <0x73f80400 0x0200>;
301 interrupts = <16>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]302 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]303 fsl,usbmisc = <&usbmisc 2>;
Matt Porter3ec481e2015-02-27 09:06:00 -0500[diff] [blame]304 dr_mode = "host";
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]305 status = "disabled";
306 };
307
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]308 usbh3: usb@73f80600 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]309 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
310 reg = <0x73f80600 0x0200>;
311 interrupts = <17>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]312 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]313 fsl,usbmisc = <&usbmisc 3>;
Matt Porter3ec481e2015-02-27 09:06:00 -0500[diff] [blame]314 dr_mode = "host";
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]315 status = "disabled";
316 };
317
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]318 usbmisc: usbmisc@73f80800 {
319 #index-cells = <1>;
320 compatible = "fsl,imx51-usbmisc";
321 reg = <0x73f80800 0x200>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]322 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]323 };
324
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]325 gpio1: gpio@73f84000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]326 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]327 reg = <0x73f84000 0x4000>;
328 interrupts = <50 51>;
329 gpio-controller;
330 #gpio-cells = <2>;
331 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]332 #interrupt-cells = <2>;
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]333 };
334
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]335 gpio2: gpio@73f88000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]336 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]337 reg = <0x73f88000 0x4000>;
338 interrupts = <52 53>;
339 gpio-controller;
340 #gpio-cells = <2>;
341 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]342 #interrupt-cells = <2>;
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]343 };
344
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]345 gpio3: gpio@73f8c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]346 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]347 reg = <0x73f8c000 0x4000>;
348 interrupts = <54 55>;
349 gpio-controller;
350 #gpio-cells = <2>;
351 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]352 #interrupt-cells = <2>;
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]353 };
354
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]355 gpio4: gpio@73f90000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]356 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]357 reg = <0x73f90000 0x4000>;
358 interrupts = <56 57>;
359 gpio-controller;
360 #gpio-cells = <2>;
361 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]362 #interrupt-cells = <2>;
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]363 };
364
Liu Ying6012555c2013-01-03 20:37:33 +0800[diff] [blame]365 kpp: kpp@73f94000 {
366 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
367 reg = <0x73f94000 0x4000>;
368 interrupts = <60>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]369 clocks = <&clks IMX5_CLK_DUMMY>;
Liu Ying6012555c2013-01-03 20:37:33 +0800[diff] [blame]370 status = "disabled";
371 };
372
Krzysztof Kozlowskicec12cd2020-09-26 18:23:01 +0200[diff] [blame]373 wdog1: watchdog@73f98000 {
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]374 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
375 reg = <0x73f98000 0x4000>;
376 interrupts = <58>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]377 clocks = <&clks IMX5_CLK_DUMMY>;
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]378 };
379
Krzysztof Kozlowskicec12cd2020-09-26 18:23:01 +0200[diff] [blame]380 wdog2: watchdog@73f9c000 {
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]381 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
382 reg = <0x73f9c000 0x4000>;
383 interrupts = <59>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]384 clocks = <&clks IMX5_CLK_DUMMY>;
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]385 status = "disabled";
386 };
387
Sascha Hauered73c632013-03-14 13:08:59 +0100[diff] [blame]388 gpt: timer@73fa0000 {
389 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
390 reg = <0x73fa0000 0x4000>;
391 interrupts = <39>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]392 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
Jagan Teki46311702016-10-26 15:31:01 +0530[diff] [blame]393 <&clks IMX5_CLK_GPT_HF_GATE>;
Sascha Hauered73c632013-03-14 13:08:59 +0100[diff] [blame]394 clock-names = "ipg", "per";
395 };
396
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]397 iomuxc: iomuxc@73fa8000 {
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]398 compatible = "fsl,imx51-iomuxc";
399 reg = <0x73fa8000 0x4000>;
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]400 };
401
Sascha Hauer82a618d2012-11-19 00:57:08 +0100[diff] [blame]402 pwm1: pwm@73fb4000 {
Uwe Kleine-Königfa28d822020-07-10 07:19:37 +0200[diff] [blame]403 #pwm-cells = <3>;
Sascha Hauer82a618d2012-11-19 00:57:08 +0100[diff] [blame]404 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
405 reg = <0x73fb4000 0x4000>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]406 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
Jagan Teki46311702016-10-26 15:31:01 +0530[diff] [blame]407 <&clks IMX5_CLK_PWM1_HF_GATE>;
Sascha Hauer82a618d2012-11-19 00:57:08 +0100[diff] [blame]408 clock-names = "ipg", "per";
409 interrupts = <61>;
410 };
411
412 pwm2: pwm@73fb8000 {
Uwe Kleine-Königfa28d822020-07-10 07:19:37 +0200[diff] [blame]413 #pwm-cells = <3>;
Sascha Hauer82a618d2012-11-19 00:57:08 +0100[diff] [blame]414 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
415 reg = <0x73fb8000 0x4000>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]416 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
Jagan Teki46311702016-10-26 15:31:01 +0530[diff] [blame]417 <&clks IMX5_CLK_PWM2_HF_GATE>;
Sascha Hauer82a618d2012-11-19 00:57:08 +0100[diff] [blame]418 clock-names = "ipg", "per";
419 interrupts = <94>;
420 };
421
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]422 uart1: serial@73fbc000 {
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]423 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
424 reg = <0x73fbc000 0x4000>;
425 interrupts = <31>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]426 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
Jagan Teki46311702016-10-26 15:31:01 +0530[diff] [blame]427 <&clks IMX5_CLK_UART1_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]428 clock-names = "ipg", "per";
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]429 status = "disabled";
430 };
431
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]432 uart2: serial@73fc0000 {
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]433 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
434 reg = <0x73fc0000 0x4000>;
435 interrupts = <32>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]436 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
Jagan Teki46311702016-10-26 15:31:01 +0530[diff] [blame]437 <&clks IMX5_CLK_UART2_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]438 clock-names = "ipg", "per";
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]439 status = "disabled";
440 };
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]441
Anson Huang6a3153e2020-05-18 20:54:20 +0800[diff] [blame]442 src: reset-controller@73fd0000 {
Philipp Zabel8d84c372013-03-28 17:35:23 +0100[diff] [blame]443 compatible = "fsl,imx51-src";
444 reg = <0x73fd0000 0x4000>;
Anson Huang905d3d22020-05-12 10:25:06 +0800[diff] [blame]445 interrupts = <75>;
Philipp Zabel8d84c372013-03-28 17:35:23 +0100[diff] [blame]446 #reset-cells = <1>;
447 };
448
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]449 clks: ccm@73fd4000{
450 compatible = "fsl,imx51-ccm";
451 reg = <0x73fd4000 0x4000>;
452 interrupts = <0 71 0x04 0 72 0x04>;
453 #clock-cells = <1>;
454 };
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]455 };
456
Peng Fanc0157bd2020-02-13 11:17:58 +0800[diff] [blame]457 bus@80000000 { /* AIPS2 */
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]458 compatible = "fsl,aips-bus", "simple-bus";
459 #address-cells = <1>;
460 #size-cells = <1>;
461 reg = <0x80000000 0x10000000>;
462 ranges;
463
Fabio Estevamba72b5a2018-06-20 15:06:19 -0300[diff] [blame]464 aipstz2: bridge@83f00000 {
465 compatible = "fsl,imx51-aipstz";
466 reg = <0x83f00000 0x60>;
467 };
468
Anson Huang78b05002020-05-28 11:12:50 +0800[diff] [blame]469 iim: efuse@83f98000 {
Sebastian Reichel36034ae2021-01-27 18:40:23 +0100[diff] [blame]470 compatible = "fsl,imx51-iim", "fsl,imx27-iim", "syscon";
Sascha Hauer6510ea252013-06-25 15:51:51 +0200[diff] [blame]471 reg = <0x83f98000 0x4000>;
472 interrupts = <69>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]473 clocks = <&clks IMX5_CLK_IIM_GATE>;
Sascha Hauer6510ea252013-06-25 15:51:51 +0200[diff] [blame]474 };
475
Fabio Estevamf2254a32018-07-10 13:31:45 -0300[diff] [blame]476 tigerp: tigerp@83fa0000 {
477 compatible = "fsl,imx51-tigerp";
478 reg = <0x83fa0000 0x28>;
479 };
480
Alexander Shiyanad15f082013-08-21 11:28:25 +0400[diff] [blame]481 owire: owire@83fa4000 {
482 compatible = "fsl,imx51-owire", "fsl,imx21-owire";
483 reg = <0x83fa4000 0x4000>;
484 interrupts = <88>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]485 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
Alexander Shiyanad15f082013-08-21 11:28:25 +0400[diff] [blame]486 status = "disabled";
487 };
488
Rob Herring5a2ecf02018-09-13 13:12:29 -0500[diff] [blame]489 ecspi2: spi@83fac000 {
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]490 #address-cells = <1>;
491 #size-cells = <0>;
492 compatible = "fsl,imx51-ecspi";
493 reg = <0x83fac000 0x4000>;
494 interrupts = <37>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]495 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
Jagan Teki46311702016-10-26 15:31:01 +0530[diff] [blame]496 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]497 clock-names = "ipg", "per";
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]498 status = "disabled";
499 };
500
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]501 sdma: sdma@83fb0000 {
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]502 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
503 reg = <0x83fb0000 0x4000>;
504 interrupts = <6>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]505 clocks = <&clks IMX5_CLK_SDMA_GATE>,
Andrey Smirnov918bbde2019-03-28 23:49:23 -0700[diff] [blame]506 <&clks IMX5_CLK_AHB>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]507 clock-names = "ipg", "ahb";
Huang Shijiefb72bb22013-07-02 10:15:29 +0800[diff] [blame]508 #dma-cells = <3>;
Fabio Estevam7e4f0362012-08-08 11:28:07 -0300[diff] [blame]509 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]510 };
511
Rob Herring5a2ecf02018-09-13 13:12:29 -0500[diff] [blame]512 cspi: spi@83fc0000 {
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]513 #address-cells = <1>;
514 #size-cells = <0>;
515 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
516 reg = <0x83fc0000 0x4000>;
517 interrupts = <38>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]518 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
Jagan Teki46311702016-10-26 15:31:01 +0530[diff] [blame]519 <&clks IMX5_CLK_CSPI_IPG_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]520 clock-names = "ipg", "per";
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]521 status = "disabled";
522 };
523
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]524 i2c2: i2c@83fc4000 {
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]525 #address-cells = <1>;
526 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]527 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]528 reg = <0x83fc4000 0x4000>;
529 interrupts = <63>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]530 clocks = <&clks IMX5_CLK_I2C2_GATE>;
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]531 status = "disabled";
532 };
533
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]534 i2c1: i2c@83fc8000 {
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]535 #address-cells = <1>;
536 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]537 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]538 reg = <0x83fc8000 0x4000>;
539 interrupts = <62>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]540 clocks = <&clks IMX5_CLK_I2C1_GATE>;
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]541 status = "disabled";
542 };
543
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]544 ssi1: ssi@83fcc000 {
Alexander Shiyan6ff7f512014-08-19 20:00:09 +0400[diff] [blame]545 #sound-dai-cells = <0>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]546 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
547 reg = <0x83fcc000 0x4000>;
548 interrupts = <29>;
Fabio Estevam53ec8742014-09-18 20:23:49 -0300[diff] [blame]549 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
550 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
551 clock-names = "ipg", "baud";
Shawn Guo5da826a2013-07-17 13:50:54 +0800[diff] [blame]552 dmas = <&sdma 28 0 0>,
553 <&sdma 29 0 0>;
554 dma-names = "rx", "tx";
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]555 fsl,fifo-depth = <15>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]556 status = "disabled";
557 };
558
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]559 audmux: audmux@83fd0000 {
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]560 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
561 reg = <0x83fd0000 0x4000>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]562 clocks = <&clks IMX5_CLK_DUMMY>;
Alexander Shiyane030df92013-11-07 12:45:06 +0400[diff] [blame]563 clock-names = "audmux";
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]564 status = "disabled";
565 };
566
Fabio Estevamb6b93a32018-07-09 15:19:14 -0300[diff] [blame]567 m4if: m4if@83fd8000 {
568 compatible = "fsl,imx51-m4if";
569 reg = <0x83fd8000 0x1000>;
570 };
571
Alexander Shiyanedd05282013-07-13 08:30:57 +0400[diff] [blame]572 weim: weim@83fda000 {
573 #address-cells = <2>;
574 #size-cells = <1>;
575 compatible = "fsl,imx51-weim";
576 reg = <0x83fda000 0x1000>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]577 clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
Alexander Shiyanedd05282013-07-13 08:30:57 +0400[diff] [blame]578 ranges = <
579 0 0 0xb0000000 0x08000000
580 1 0 0xb8000000 0x08000000
581 2 0 0xc0000000 0x08000000
582 3 0 0xc8000000 0x04000000
583 4 0 0xcc000000 0x02000000
584 5 0 0xce000000 0x02000000
585 >;
586 status = "disabled";
587 };
588
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]589 nfc: nand@83fdb000 {
Alexander Shiyanf0e3f892014-04-16 11:24:50 +0400[diff] [blame]590 #address-cells = <1>;
591 #size-cells = <1>;
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]592 compatible = "fsl,imx51-nand";
593 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
594 interrupts = <8>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]595 clocks = <&clks IMX5_CLK_NFC_GATE>;
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]596 status = "disabled";
597 };
598
Sascha Hauer718a35002013-04-04 11:25:09 +0200[diff] [blame]599 pata: pata@83fe0000 {
600 compatible = "fsl,imx51-pata", "fsl,imx27-pata";
601 reg = <0x83fe0000 0x4000>;
602 interrupts = <70>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]603 clocks = <&clks IMX5_CLK_PATA_GATE>;
Sascha Hauer718a35002013-04-04 11:25:09 +0200[diff] [blame]604 status = "disabled";
605 };
606
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]607 ssi3: ssi@83fe8000 {
Alexander Shiyan6ff7f512014-08-19 20:00:09 +0400[diff] [blame]608 #sound-dai-cells = <0>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]609 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
610 reg = <0x83fe8000 0x4000>;
611 interrupts = <96>;
Fabio Estevam53ec8742014-09-18 20:23:49 -0300[diff] [blame]612 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
613 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
614 clock-names = "ipg", "baud";
Shawn Guo5da826a2013-07-17 13:50:54 +0800[diff] [blame]615 dmas = <&sdma 46 0 0>,
616 <&sdma 47 0 0>;
617 dma-names = "rx", "tx";
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]618 fsl,fifo-depth = <15>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]619 status = "disabled";
620 };
621
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]622 fec: ethernet@83fec000 {
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]623 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
624 reg = <0x83fec000 0x4000>;
625 interrupts = <87>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]626 clocks = <&clks IMX5_CLK_FEC_GATE>,
Jagan Teki46311702016-10-26 15:31:01 +0530[diff] [blame]627 <&clks IMX5_CLK_FEC_GATE>,
628 <&clks IMX5_CLK_FEC_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]629 clock-names = "ipg", "ahb", "ptp";
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]630 status = "disabled";
631 };
Philipp Zabel328bd822017-12-13 15:24:06 +0100[diff] [blame]632
Fabio Estevam41d9feb2018-09-11 17:10:42 -0300[diff] [blame]633 vpu: vpu@83ff4000 {
Philipp Zabel328bd822017-12-13 15:24:06 +0100[diff] [blame]634 compatible = "fsl,imx51-vpu", "cnm,codahx4";
635 reg = <0x83ff4000 0x1000>;
636 interrupts = <9>;
637 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
638 <&clks IMX5_CLK_VPU_GATE>;
639 clock-names = "per", "ahb";
640 resets = <&src 1>;
641 iram = <&iram>;
642 };
Fabio Estevam91527432018-06-26 20:18:52 -0300[diff] [blame]643
644 sahara: crypto@83ff8000 {
645 compatible = "fsl,imx53-sahara", "fsl,imx51-sahara";
646 reg = <0x83ff8000 0x4000>;
647 interrupts = <19 20>;
648 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
649 <&clks IMX5_CLK_SAHARA_IPG_GATE>;
650 clock-names = "ipg", "ahb";
651 };
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]652 };
653 };
654};