Jianwei Wang | 109eee2 | 2015-08-19 22:19:49 -0400 | [diff] [blame] | 1 | Device Tree bindings for Freescale DCU DRM Driver |
| 2 | |
| 3 | Required properties: |
| 4 | - compatible: Should be one of |
| 5 | * "fsl,ls1021a-dcu". |
| 6 | * "fsl,vf610-dcu". |
| 7 | |
| 8 | - reg: Address and length of the register set for dcu. |
Stefan Agner | f93500f | 2016-03-22 15:45:29 -0700 | [diff] [blame] | 9 | - clocks: Handle to "dcu" and "pix" clock (in the order below) |
| 10 | This can be the same clock (e.g. LS1021a) |
| 11 | See ../clocks/clock-bindings.txt for details. |
| 12 | - clock-names: Should be "dcu" and "pix" |
| 13 | See ../clocks/clock-bindings.txt for details. |
Jianwei Wang | 109eee2 | 2015-08-19 22:19:49 -0400 | [diff] [blame] | 14 | - big-endian Boolean property, LS1021A DCU registers are big-endian. |
Meng Yi | 924591b | 2016-07-15 14:53:37 +0800 | [diff] [blame] | 15 | - port Video port for the panel output |
Jianwei Wang | 109eee2 | 2015-08-19 22:19:49 -0400 | [diff] [blame] | 16 | |
Stefan Agner | fb127b7 | 2015-12-02 14:39:40 -0800 | [diff] [blame] | 17 | Optional properties: |
| 18 | - fsl,tcon: The phandle to the timing controller node. |
| 19 | |
Jianwei Wang | 109eee2 | 2015-08-19 22:19:49 -0400 | [diff] [blame] | 20 | Examples: |
| 21 | dcu: dcu@2ce0000 { |
| 22 | compatible = "fsl,ls1021a-dcu"; |
| 23 | reg = <0x0 0x2ce0000 0x0 0x10000>; |
Stefan Agner | f93500f | 2016-03-22 15:45:29 -0700 | [diff] [blame] | 24 | clocks = <&platform_clk 0>, <&platform_clk 0>; |
| 25 | clock-names = "dcu", "pix"; |
Jianwei Wang | 109eee2 | 2015-08-19 22:19:49 -0400 | [diff] [blame] | 26 | big-endian; |
Stefan Agner | fb127b7 | 2015-12-02 14:39:40 -0800 | [diff] [blame] | 27 | fsl,tcon = <&tcon>; |
Meng Yi | 924591b | 2016-07-15 14:53:37 +0800 | [diff] [blame] | 28 | |
| 29 | port { |
| 30 | dcu_out: endpoint { |
| 31 | remote-endpoint = <&panel_out>; |
| 32 | }; |
| 33 | }; |
Jianwei Wang | 109eee2 | 2015-08-19 22:19:49 -0400 | [diff] [blame] | 34 | }; |