Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | // |
| 3 | // Copyright (c) 2013-2014 Freescale Semiconductor, Inc |
| 4 | // Copyright (c) 2017 Sysam, Angelo Dureghello <angelo@sysam.it> |
| 5 | |
| 6 | #include <linux/dmapool.h> |
| 7 | #include <linux/module.h> |
| 8 | #include <linux/slab.h> |
Laurentiu Tudor | 0fa89f9 | 2019-01-18 12:06:23 +0200 | [diff] [blame] | 9 | #include <linux/dma-mapping.h> |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 10 | |
| 11 | #include "fsl-edma-common.h" |
| 12 | |
| 13 | #define EDMA_CR 0x00 |
| 14 | #define EDMA_ES 0x04 |
| 15 | #define EDMA_ERQ 0x0C |
| 16 | #define EDMA_EEI 0x14 |
| 17 | #define EDMA_SERQ 0x1B |
| 18 | #define EDMA_CERQ 0x1A |
| 19 | #define EDMA_SEEI 0x19 |
| 20 | #define EDMA_CEEI 0x18 |
| 21 | #define EDMA_CINT 0x1F |
| 22 | #define EDMA_CERR 0x1E |
| 23 | #define EDMA_SSRT 0x1D |
| 24 | #define EDMA_CDNE 0x1C |
| 25 | #define EDMA_INTR 0x24 |
| 26 | #define EDMA_ERR 0x2C |
| 27 | |
| 28 | #define EDMA64_ERQH 0x08 |
| 29 | #define EDMA64_EEIH 0x10 |
| 30 | #define EDMA64_SERQ 0x18 |
| 31 | #define EDMA64_CERQ 0x19 |
| 32 | #define EDMA64_SEEI 0x1a |
| 33 | #define EDMA64_CEEI 0x1b |
| 34 | #define EDMA64_CINT 0x1c |
| 35 | #define EDMA64_CERR 0x1d |
| 36 | #define EDMA64_SSRT 0x1e |
| 37 | #define EDMA64_CDNE 0x1f |
| 38 | #define EDMA64_INTH 0x20 |
| 39 | #define EDMA64_INTL 0x24 |
| 40 | #define EDMA64_ERRH 0x28 |
| 41 | #define EDMA64_ERRL 0x2c |
| 42 | |
| 43 | #define EDMA_TCD 0x1000 |
| 44 | |
| 45 | static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan) |
| 46 | { |
Angelo Dureghello | 377eaf3 | 2018-08-19 19:27:14 +0200 | [diff] [blame] | 47 | struct edma_regs *regs = &fsl_chan->edma->regs; |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 48 | u32 ch = fsl_chan->vchan.chan.chan_id; |
| 49 | |
Robin Gong | af80272 | 2019-06-25 17:43:19 +0800 | [diff] [blame^] | 50 | if (fsl_chan->edma->drvdata->version == v1) { |
Angelo Dureghello | e7a3ff9 | 2018-08-19 19:27:16 +0200 | [diff] [blame] | 51 | edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei); |
| 52 | edma_writeb(fsl_chan->edma, ch, regs->serq); |
| 53 | } else { |
| 54 | /* ColdFire is big endian, and accesses natively |
| 55 | * big endian I/O peripherals |
| 56 | */ |
| 57 | iowrite8(EDMA_SEEI_SEEI(ch), regs->seei); |
| 58 | iowrite8(ch, regs->serq); |
| 59 | } |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 60 | } |
| 61 | |
| 62 | void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan) |
| 63 | { |
Angelo Dureghello | 377eaf3 | 2018-08-19 19:27:14 +0200 | [diff] [blame] | 64 | struct edma_regs *regs = &fsl_chan->edma->regs; |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 65 | u32 ch = fsl_chan->vchan.chan.chan_id; |
| 66 | |
Robin Gong | af80272 | 2019-06-25 17:43:19 +0800 | [diff] [blame^] | 67 | if (fsl_chan->edma->drvdata->version == v1) { |
Angelo Dureghello | e7a3ff9 | 2018-08-19 19:27:16 +0200 | [diff] [blame] | 68 | edma_writeb(fsl_chan->edma, ch, regs->cerq); |
| 69 | edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei); |
| 70 | } else { |
| 71 | /* ColdFire is big endian, and accesses natively |
| 72 | * big endian I/O peripherals |
| 73 | */ |
| 74 | iowrite8(ch, regs->cerq); |
| 75 | iowrite8(EDMA_CEEI_CEEI(ch), regs->ceei); |
| 76 | } |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 77 | } |
| 78 | EXPORT_SYMBOL_GPL(fsl_edma_disable_request); |
| 79 | |
| 80 | void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan, |
| 81 | unsigned int slot, bool enable) |
| 82 | { |
| 83 | u32 ch = fsl_chan->vchan.chan.chan_id; |
| 84 | void __iomem *muxaddr; |
| 85 | unsigned int chans_per_mux, ch_off; |
Robin Gong | af80272 | 2019-06-25 17:43:19 +0800 | [diff] [blame^] | 86 | u32 dmamux_nr = fsl_chan->edma->drvdata->dmamuxs; |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 87 | |
Robin Gong | af80272 | 2019-06-25 17:43:19 +0800 | [diff] [blame^] | 88 | chans_per_mux = fsl_chan->edma->n_chans / dmamux_nr; |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 89 | ch_off = fsl_chan->vchan.chan.chan_id % chans_per_mux; |
| 90 | muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux]; |
| 91 | slot = EDMAMUX_CHCFG_SOURCE(slot); |
| 92 | |
| 93 | if (enable) |
| 94 | iowrite8(EDMAMUX_CHCFG_ENBL | slot, muxaddr + ch_off); |
| 95 | else |
| 96 | iowrite8(EDMAMUX_CHCFG_DIS, muxaddr + ch_off); |
| 97 | } |
| 98 | EXPORT_SYMBOL_GPL(fsl_edma_chan_mux); |
| 99 | |
| 100 | static unsigned int fsl_edma_get_tcd_attr(enum dma_slave_buswidth addr_width) |
| 101 | { |
| 102 | switch (addr_width) { |
| 103 | case 1: |
| 104 | return EDMA_TCD_ATTR_SSIZE_8BIT | EDMA_TCD_ATTR_DSIZE_8BIT; |
| 105 | case 2: |
| 106 | return EDMA_TCD_ATTR_SSIZE_16BIT | EDMA_TCD_ATTR_DSIZE_16BIT; |
| 107 | case 4: |
| 108 | return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT; |
| 109 | case 8: |
| 110 | return EDMA_TCD_ATTR_SSIZE_64BIT | EDMA_TCD_ATTR_DSIZE_64BIT; |
| 111 | default: |
| 112 | return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT; |
| 113 | } |
| 114 | } |
| 115 | |
| 116 | void fsl_edma_free_desc(struct virt_dma_desc *vdesc) |
| 117 | { |
| 118 | struct fsl_edma_desc *fsl_desc; |
| 119 | int i; |
| 120 | |
| 121 | fsl_desc = to_fsl_edma_desc(vdesc); |
| 122 | for (i = 0; i < fsl_desc->n_tcds; i++) |
| 123 | dma_pool_free(fsl_desc->echan->tcd_pool, fsl_desc->tcd[i].vtcd, |
| 124 | fsl_desc->tcd[i].ptcd); |
| 125 | kfree(fsl_desc); |
| 126 | } |
| 127 | EXPORT_SYMBOL_GPL(fsl_edma_free_desc); |
| 128 | |
| 129 | int fsl_edma_terminate_all(struct dma_chan *chan) |
| 130 | { |
| 131 | struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); |
| 132 | unsigned long flags; |
| 133 | LIST_HEAD(head); |
| 134 | |
| 135 | spin_lock_irqsave(&fsl_chan->vchan.lock, flags); |
| 136 | fsl_edma_disable_request(fsl_chan); |
| 137 | fsl_chan->edesc = NULL; |
| 138 | fsl_chan->idle = true; |
| 139 | vchan_get_all_descriptors(&fsl_chan->vchan, &head); |
| 140 | spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); |
| 141 | vchan_dma_desc_free_list(&fsl_chan->vchan, &head); |
| 142 | return 0; |
| 143 | } |
| 144 | EXPORT_SYMBOL_GPL(fsl_edma_terminate_all); |
| 145 | |
| 146 | int fsl_edma_pause(struct dma_chan *chan) |
| 147 | { |
| 148 | struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); |
| 149 | unsigned long flags; |
| 150 | |
| 151 | spin_lock_irqsave(&fsl_chan->vchan.lock, flags); |
| 152 | if (fsl_chan->edesc) { |
| 153 | fsl_edma_disable_request(fsl_chan); |
| 154 | fsl_chan->status = DMA_PAUSED; |
| 155 | fsl_chan->idle = true; |
| 156 | } |
| 157 | spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); |
| 158 | return 0; |
| 159 | } |
| 160 | EXPORT_SYMBOL_GPL(fsl_edma_pause); |
| 161 | |
| 162 | int fsl_edma_resume(struct dma_chan *chan) |
| 163 | { |
| 164 | struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); |
| 165 | unsigned long flags; |
| 166 | |
| 167 | spin_lock_irqsave(&fsl_chan->vchan.lock, flags); |
| 168 | if (fsl_chan->edesc) { |
| 169 | fsl_edma_enable_request(fsl_chan); |
| 170 | fsl_chan->status = DMA_IN_PROGRESS; |
| 171 | fsl_chan->idle = false; |
| 172 | } |
| 173 | spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); |
| 174 | return 0; |
| 175 | } |
| 176 | EXPORT_SYMBOL_GPL(fsl_edma_resume); |
| 177 | |
Laurentiu Tudor | 0fa89f9 | 2019-01-18 12:06:23 +0200 | [diff] [blame] | 178 | static void fsl_edma_unprep_slave_dma(struct fsl_edma_chan *fsl_chan) |
| 179 | { |
| 180 | if (fsl_chan->dma_dir != DMA_NONE) |
| 181 | dma_unmap_resource(fsl_chan->vchan.chan.device->dev, |
| 182 | fsl_chan->dma_dev_addr, |
| 183 | fsl_chan->dma_dev_size, |
| 184 | fsl_chan->dma_dir, 0); |
| 185 | fsl_chan->dma_dir = DMA_NONE; |
| 186 | } |
| 187 | |
| 188 | static bool fsl_edma_prep_slave_dma(struct fsl_edma_chan *fsl_chan, |
| 189 | enum dma_transfer_direction dir) |
| 190 | { |
| 191 | struct device *dev = fsl_chan->vchan.chan.device->dev; |
| 192 | enum dma_data_direction dma_dir; |
| 193 | phys_addr_t addr = 0; |
| 194 | u32 size = 0; |
| 195 | |
| 196 | switch (dir) { |
| 197 | case DMA_MEM_TO_DEV: |
| 198 | dma_dir = DMA_FROM_DEVICE; |
| 199 | addr = fsl_chan->cfg.dst_addr; |
| 200 | size = fsl_chan->cfg.dst_maxburst; |
| 201 | break; |
| 202 | case DMA_DEV_TO_MEM: |
| 203 | dma_dir = DMA_TO_DEVICE; |
| 204 | addr = fsl_chan->cfg.src_addr; |
| 205 | size = fsl_chan->cfg.src_maxburst; |
| 206 | break; |
| 207 | default: |
| 208 | dma_dir = DMA_NONE; |
| 209 | break; |
| 210 | } |
| 211 | |
| 212 | /* Already mapped for this config? */ |
| 213 | if (fsl_chan->dma_dir == dma_dir) |
| 214 | return true; |
| 215 | |
| 216 | fsl_edma_unprep_slave_dma(fsl_chan); |
| 217 | |
| 218 | fsl_chan->dma_dev_addr = dma_map_resource(dev, addr, size, dma_dir, 0); |
| 219 | if (dma_mapping_error(dev, fsl_chan->dma_dev_addr)) |
| 220 | return false; |
| 221 | fsl_chan->dma_dev_size = size; |
| 222 | fsl_chan->dma_dir = dma_dir; |
| 223 | |
| 224 | return true; |
| 225 | } |
| 226 | |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 227 | int fsl_edma_slave_config(struct dma_chan *chan, |
| 228 | struct dma_slave_config *cfg) |
| 229 | { |
| 230 | struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); |
| 231 | |
Vinod Koul | 0e819e35 | 2018-10-07 19:42:56 +0530 | [diff] [blame] | 232 | memcpy(&fsl_chan->cfg, cfg, sizeof(*cfg)); |
Laurentiu Tudor | 0fa89f9 | 2019-01-18 12:06:23 +0200 | [diff] [blame] | 233 | fsl_edma_unprep_slave_dma(fsl_chan); |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 234 | |
| 235 | return 0; |
| 236 | } |
| 237 | EXPORT_SYMBOL_GPL(fsl_edma_slave_config); |
| 238 | |
| 239 | static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan, |
| 240 | struct virt_dma_desc *vdesc, bool in_progress) |
| 241 | { |
| 242 | struct fsl_edma_desc *edesc = fsl_chan->edesc; |
Angelo Dureghello | 377eaf3 | 2018-08-19 19:27:14 +0200 | [diff] [blame] | 243 | struct edma_regs *regs = &fsl_chan->edma->regs; |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 244 | u32 ch = fsl_chan->vchan.chan.chan_id; |
Vinod Koul | 0e819e35 | 2018-10-07 19:42:56 +0530 | [diff] [blame] | 245 | enum dma_transfer_direction dir = edesc->dirn; |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 246 | dma_addr_t cur_addr, dma_addr; |
| 247 | size_t len, size; |
| 248 | int i; |
| 249 | |
| 250 | /* calculate the total size in this desc */ |
| 251 | for (len = i = 0; i < fsl_chan->edesc->n_tcds; i++) |
| 252 | len += le32_to_cpu(edesc->tcd[i].vtcd->nbytes) |
| 253 | * le16_to_cpu(edesc->tcd[i].vtcd->biter); |
| 254 | |
| 255 | if (!in_progress) |
| 256 | return len; |
| 257 | |
| 258 | if (dir == DMA_MEM_TO_DEV) |
Angelo Dureghello | 377eaf3 | 2018-08-19 19:27:14 +0200 | [diff] [blame] | 259 | cur_addr = edma_readl(fsl_chan->edma, ®s->tcd[ch].saddr); |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 260 | else |
Angelo Dureghello | 377eaf3 | 2018-08-19 19:27:14 +0200 | [diff] [blame] | 261 | cur_addr = edma_readl(fsl_chan->edma, ®s->tcd[ch].daddr); |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 262 | |
| 263 | /* figure out the finished and calculate the residue */ |
| 264 | for (i = 0; i < fsl_chan->edesc->n_tcds; i++) { |
| 265 | size = le32_to_cpu(edesc->tcd[i].vtcd->nbytes) |
| 266 | * le16_to_cpu(edesc->tcd[i].vtcd->biter); |
| 267 | if (dir == DMA_MEM_TO_DEV) |
| 268 | dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->saddr); |
| 269 | else |
| 270 | dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->daddr); |
| 271 | |
| 272 | len -= size; |
| 273 | if (cur_addr >= dma_addr && cur_addr < dma_addr + size) { |
| 274 | len += dma_addr + size - cur_addr; |
| 275 | break; |
| 276 | } |
| 277 | } |
| 278 | |
| 279 | return len; |
| 280 | } |
| 281 | |
| 282 | enum dma_status fsl_edma_tx_status(struct dma_chan *chan, |
| 283 | dma_cookie_t cookie, struct dma_tx_state *txstate) |
| 284 | { |
| 285 | struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); |
| 286 | struct virt_dma_desc *vdesc; |
| 287 | enum dma_status status; |
| 288 | unsigned long flags; |
| 289 | |
| 290 | status = dma_cookie_status(chan, cookie, txstate); |
| 291 | if (status == DMA_COMPLETE) |
| 292 | return status; |
| 293 | |
| 294 | if (!txstate) |
| 295 | return fsl_chan->status; |
| 296 | |
| 297 | spin_lock_irqsave(&fsl_chan->vchan.lock, flags); |
| 298 | vdesc = vchan_find_desc(&fsl_chan->vchan, cookie); |
| 299 | if (fsl_chan->edesc && cookie == fsl_chan->edesc->vdesc.tx.cookie) |
| 300 | txstate->residue = |
| 301 | fsl_edma_desc_residue(fsl_chan, vdesc, true); |
| 302 | else if (vdesc) |
| 303 | txstate->residue = |
| 304 | fsl_edma_desc_residue(fsl_chan, vdesc, false); |
| 305 | else |
| 306 | txstate->residue = 0; |
| 307 | |
| 308 | spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); |
| 309 | |
| 310 | return fsl_chan->status; |
| 311 | } |
| 312 | EXPORT_SYMBOL_GPL(fsl_edma_tx_status); |
| 313 | |
| 314 | static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan, |
| 315 | struct fsl_edma_hw_tcd *tcd) |
| 316 | { |
| 317 | struct fsl_edma_engine *edma = fsl_chan->edma; |
Angelo Dureghello | 377eaf3 | 2018-08-19 19:27:14 +0200 | [diff] [blame] | 318 | struct edma_regs *regs = &fsl_chan->edma->regs; |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 319 | u32 ch = fsl_chan->vchan.chan.chan_id; |
| 320 | |
| 321 | /* |
| 322 | * TCD parameters are stored in struct fsl_edma_hw_tcd in little |
| 323 | * endian format. However, we need to load the TCD registers in |
| 324 | * big- or little-endian obeying the eDMA engine model endian. |
| 325 | */ |
Angelo Dureghello | 377eaf3 | 2018-08-19 19:27:14 +0200 | [diff] [blame] | 326 | edma_writew(edma, 0, ®s->tcd[ch].csr); |
| 327 | edma_writel(edma, le32_to_cpu(tcd->saddr), ®s->tcd[ch].saddr); |
| 328 | edma_writel(edma, le32_to_cpu(tcd->daddr), ®s->tcd[ch].daddr); |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 329 | |
Angelo Dureghello | 377eaf3 | 2018-08-19 19:27:14 +0200 | [diff] [blame] | 330 | edma_writew(edma, le16_to_cpu(tcd->attr), ®s->tcd[ch].attr); |
| 331 | edma_writew(edma, le16_to_cpu(tcd->soff), ®s->tcd[ch].soff); |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 332 | |
Angelo Dureghello | 377eaf3 | 2018-08-19 19:27:14 +0200 | [diff] [blame] | 333 | edma_writel(edma, le32_to_cpu(tcd->nbytes), ®s->tcd[ch].nbytes); |
| 334 | edma_writel(edma, le32_to_cpu(tcd->slast), ®s->tcd[ch].slast); |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 335 | |
Angelo Dureghello | 377eaf3 | 2018-08-19 19:27:14 +0200 | [diff] [blame] | 336 | edma_writew(edma, le16_to_cpu(tcd->citer), ®s->tcd[ch].citer); |
| 337 | edma_writew(edma, le16_to_cpu(tcd->biter), ®s->tcd[ch].biter); |
| 338 | edma_writew(edma, le16_to_cpu(tcd->doff), ®s->tcd[ch].doff); |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 339 | |
Angelo Dureghello | 377eaf3 | 2018-08-19 19:27:14 +0200 | [diff] [blame] | 340 | edma_writel(edma, le32_to_cpu(tcd->dlast_sga), |
| 341 | ®s->tcd[ch].dlast_sga); |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 342 | |
Angelo Dureghello | 377eaf3 | 2018-08-19 19:27:14 +0200 | [diff] [blame] | 343 | edma_writew(edma, le16_to_cpu(tcd->csr), ®s->tcd[ch].csr); |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 344 | } |
| 345 | |
| 346 | static inline |
| 347 | void fsl_edma_fill_tcd(struct fsl_edma_hw_tcd *tcd, u32 src, u32 dst, |
| 348 | u16 attr, u16 soff, u32 nbytes, u32 slast, u16 citer, |
| 349 | u16 biter, u16 doff, u32 dlast_sga, bool major_int, |
| 350 | bool disable_req, bool enable_sg) |
| 351 | { |
| 352 | u16 csr = 0; |
| 353 | |
| 354 | /* |
| 355 | * eDMA hardware SGs require the TCDs to be stored in little |
| 356 | * endian format irrespective of the register endian model. |
| 357 | * So we put the value in little endian in memory, waiting |
| 358 | * for fsl_edma_set_tcd_regs doing the swap. |
| 359 | */ |
| 360 | tcd->saddr = cpu_to_le32(src); |
| 361 | tcd->daddr = cpu_to_le32(dst); |
| 362 | |
| 363 | tcd->attr = cpu_to_le16(attr); |
| 364 | |
Angelo Dureghello | 377eaf3 | 2018-08-19 19:27:14 +0200 | [diff] [blame] | 365 | tcd->soff = cpu_to_le16(soff); |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 366 | |
Angelo Dureghello | 377eaf3 | 2018-08-19 19:27:14 +0200 | [diff] [blame] | 367 | tcd->nbytes = cpu_to_le32(nbytes); |
| 368 | tcd->slast = cpu_to_le32(slast); |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 369 | |
| 370 | tcd->citer = cpu_to_le16(EDMA_TCD_CITER_CITER(citer)); |
Angelo Dureghello | 377eaf3 | 2018-08-19 19:27:14 +0200 | [diff] [blame] | 371 | tcd->doff = cpu_to_le16(doff); |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 372 | |
Angelo Dureghello | 377eaf3 | 2018-08-19 19:27:14 +0200 | [diff] [blame] | 373 | tcd->dlast_sga = cpu_to_le32(dlast_sga); |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 374 | |
| 375 | tcd->biter = cpu_to_le16(EDMA_TCD_BITER_BITER(biter)); |
| 376 | if (major_int) |
| 377 | csr |= EDMA_TCD_CSR_INT_MAJOR; |
| 378 | |
| 379 | if (disable_req) |
| 380 | csr |= EDMA_TCD_CSR_D_REQ; |
| 381 | |
| 382 | if (enable_sg) |
| 383 | csr |= EDMA_TCD_CSR_E_SG; |
| 384 | |
| 385 | tcd->csr = cpu_to_le16(csr); |
| 386 | } |
| 387 | |
| 388 | static struct fsl_edma_desc *fsl_edma_alloc_desc(struct fsl_edma_chan *fsl_chan, |
| 389 | int sg_len) |
| 390 | { |
| 391 | struct fsl_edma_desc *fsl_desc; |
| 392 | int i; |
| 393 | |
Gustavo A. R. Silva | de1fa4f | 2019-01-04 15:25:45 -0600 | [diff] [blame] | 394 | fsl_desc = kzalloc(struct_size(fsl_desc, tcd, sg_len), GFP_NOWAIT); |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 395 | if (!fsl_desc) |
| 396 | return NULL; |
| 397 | |
| 398 | fsl_desc->echan = fsl_chan; |
| 399 | fsl_desc->n_tcds = sg_len; |
| 400 | for (i = 0; i < sg_len; i++) { |
| 401 | fsl_desc->tcd[i].vtcd = dma_pool_alloc(fsl_chan->tcd_pool, |
| 402 | GFP_NOWAIT, &fsl_desc->tcd[i].ptcd); |
| 403 | if (!fsl_desc->tcd[i].vtcd) |
| 404 | goto err; |
| 405 | } |
| 406 | return fsl_desc; |
| 407 | |
| 408 | err: |
| 409 | while (--i >= 0) |
| 410 | dma_pool_free(fsl_chan->tcd_pool, fsl_desc->tcd[i].vtcd, |
| 411 | fsl_desc->tcd[i].ptcd); |
| 412 | kfree(fsl_desc); |
| 413 | return NULL; |
| 414 | } |
| 415 | |
| 416 | struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic( |
| 417 | struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, |
| 418 | size_t period_len, enum dma_transfer_direction direction, |
| 419 | unsigned long flags) |
| 420 | { |
| 421 | struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); |
| 422 | struct fsl_edma_desc *fsl_desc; |
| 423 | dma_addr_t dma_buf_next; |
| 424 | int sg_len, i; |
| 425 | u32 src_addr, dst_addr, last_sg, nbytes; |
| 426 | u16 soff, doff, iter; |
| 427 | |
Vinod Koul | 0e819e35 | 2018-10-07 19:42:56 +0530 | [diff] [blame] | 428 | if (!is_slave_direction(direction)) |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 429 | return NULL; |
| 430 | |
Laurentiu Tudor | 0fa89f9 | 2019-01-18 12:06:23 +0200 | [diff] [blame] | 431 | if (!fsl_edma_prep_slave_dma(fsl_chan, direction)) |
| 432 | return NULL; |
| 433 | |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 434 | sg_len = buf_len / period_len; |
| 435 | fsl_desc = fsl_edma_alloc_desc(fsl_chan, sg_len); |
| 436 | if (!fsl_desc) |
| 437 | return NULL; |
| 438 | fsl_desc->iscyclic = true; |
Vinod Koul | 0e819e35 | 2018-10-07 19:42:56 +0530 | [diff] [blame] | 439 | fsl_desc->dirn = direction; |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 440 | |
| 441 | dma_buf_next = dma_addr; |
Vinod Koul | 0e819e35 | 2018-10-07 19:42:56 +0530 | [diff] [blame] | 442 | if (direction == DMA_MEM_TO_DEV) { |
| 443 | fsl_chan->attr = |
| 444 | fsl_edma_get_tcd_attr(fsl_chan->cfg.dst_addr_width); |
| 445 | nbytes = fsl_chan->cfg.dst_addr_width * |
| 446 | fsl_chan->cfg.dst_maxburst; |
| 447 | } else { |
| 448 | fsl_chan->attr = |
| 449 | fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width); |
| 450 | nbytes = fsl_chan->cfg.src_addr_width * |
| 451 | fsl_chan->cfg.src_maxburst; |
| 452 | } |
| 453 | |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 454 | iter = period_len / nbytes; |
| 455 | |
| 456 | for (i = 0; i < sg_len; i++) { |
| 457 | if (dma_buf_next >= dma_addr + buf_len) |
| 458 | dma_buf_next = dma_addr; |
| 459 | |
| 460 | /* get next sg's physical address */ |
| 461 | last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd; |
| 462 | |
Vinod Koul | 0e819e35 | 2018-10-07 19:42:56 +0530 | [diff] [blame] | 463 | if (direction == DMA_MEM_TO_DEV) { |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 464 | src_addr = dma_buf_next; |
Laurentiu Tudor | 0fa89f9 | 2019-01-18 12:06:23 +0200 | [diff] [blame] | 465 | dst_addr = fsl_chan->dma_dev_addr; |
Vinod Koul | 0e819e35 | 2018-10-07 19:42:56 +0530 | [diff] [blame] | 466 | soff = fsl_chan->cfg.dst_addr_width; |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 467 | doff = 0; |
| 468 | } else { |
Laurentiu Tudor | 0fa89f9 | 2019-01-18 12:06:23 +0200 | [diff] [blame] | 469 | src_addr = fsl_chan->dma_dev_addr; |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 470 | dst_addr = dma_buf_next; |
| 471 | soff = 0; |
Vinod Koul | 0e819e35 | 2018-10-07 19:42:56 +0530 | [diff] [blame] | 472 | doff = fsl_chan->cfg.src_addr_width; |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 473 | } |
| 474 | |
| 475 | fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr, dst_addr, |
Vinod Koul | 0e819e35 | 2018-10-07 19:42:56 +0530 | [diff] [blame] | 476 | fsl_chan->attr, soff, nbytes, 0, iter, |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 477 | iter, doff, last_sg, true, false, true); |
| 478 | dma_buf_next += period_len; |
| 479 | } |
| 480 | |
| 481 | return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); |
| 482 | } |
| 483 | EXPORT_SYMBOL_GPL(fsl_edma_prep_dma_cyclic); |
| 484 | |
| 485 | struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg( |
| 486 | struct dma_chan *chan, struct scatterlist *sgl, |
| 487 | unsigned int sg_len, enum dma_transfer_direction direction, |
| 488 | unsigned long flags, void *context) |
| 489 | { |
| 490 | struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); |
| 491 | struct fsl_edma_desc *fsl_desc; |
| 492 | struct scatterlist *sg; |
| 493 | u32 src_addr, dst_addr, last_sg, nbytes; |
| 494 | u16 soff, doff, iter; |
| 495 | int i; |
| 496 | |
Vinod Koul | 0e819e35 | 2018-10-07 19:42:56 +0530 | [diff] [blame] | 497 | if (!is_slave_direction(direction)) |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 498 | return NULL; |
| 499 | |
Laurentiu Tudor | 0fa89f9 | 2019-01-18 12:06:23 +0200 | [diff] [blame] | 500 | if (!fsl_edma_prep_slave_dma(fsl_chan, direction)) |
| 501 | return NULL; |
| 502 | |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 503 | fsl_desc = fsl_edma_alloc_desc(fsl_chan, sg_len); |
| 504 | if (!fsl_desc) |
| 505 | return NULL; |
| 506 | fsl_desc->iscyclic = false; |
Vinod Koul | 0e819e35 | 2018-10-07 19:42:56 +0530 | [diff] [blame] | 507 | fsl_desc->dirn = direction; |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 508 | |
Vinod Koul | 0e819e35 | 2018-10-07 19:42:56 +0530 | [diff] [blame] | 509 | if (direction == DMA_MEM_TO_DEV) { |
| 510 | fsl_chan->attr = |
| 511 | fsl_edma_get_tcd_attr(fsl_chan->cfg.dst_addr_width); |
| 512 | nbytes = fsl_chan->cfg.dst_addr_width * |
| 513 | fsl_chan->cfg.dst_maxburst; |
| 514 | } else { |
| 515 | fsl_chan->attr = |
| 516 | fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width); |
| 517 | nbytes = fsl_chan->cfg.src_addr_width * |
| 518 | fsl_chan->cfg.src_maxburst; |
| 519 | } |
| 520 | |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 521 | for_each_sg(sgl, sg, sg_len, i) { |
| 522 | /* get next sg's physical address */ |
| 523 | last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd; |
| 524 | |
Vinod Koul | 0e819e35 | 2018-10-07 19:42:56 +0530 | [diff] [blame] | 525 | if (direction == DMA_MEM_TO_DEV) { |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 526 | src_addr = sg_dma_address(sg); |
Laurentiu Tudor | 0fa89f9 | 2019-01-18 12:06:23 +0200 | [diff] [blame] | 527 | dst_addr = fsl_chan->dma_dev_addr; |
Vinod Koul | 0e819e35 | 2018-10-07 19:42:56 +0530 | [diff] [blame] | 528 | soff = fsl_chan->cfg.dst_addr_width; |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 529 | doff = 0; |
| 530 | } else { |
Laurentiu Tudor | 0fa89f9 | 2019-01-18 12:06:23 +0200 | [diff] [blame] | 531 | src_addr = fsl_chan->dma_dev_addr; |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 532 | dst_addr = sg_dma_address(sg); |
| 533 | soff = 0; |
Vinod Koul | 0e819e35 | 2018-10-07 19:42:56 +0530 | [diff] [blame] | 534 | doff = fsl_chan->cfg.src_addr_width; |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 535 | } |
| 536 | |
| 537 | iter = sg_dma_len(sg) / nbytes; |
| 538 | if (i < sg_len - 1) { |
| 539 | last_sg = fsl_desc->tcd[(i + 1)].ptcd; |
| 540 | fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr, |
Vinod Koul | 0e819e35 | 2018-10-07 19:42:56 +0530 | [diff] [blame] | 541 | dst_addr, fsl_chan->attr, soff, |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 542 | nbytes, 0, iter, iter, doff, last_sg, |
| 543 | false, false, true); |
| 544 | } else { |
| 545 | last_sg = 0; |
| 546 | fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr, |
Vinod Koul | 0e819e35 | 2018-10-07 19:42:56 +0530 | [diff] [blame] | 547 | dst_addr, fsl_chan->attr, soff, |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 548 | nbytes, 0, iter, iter, doff, last_sg, |
| 549 | true, true, false); |
| 550 | } |
| 551 | } |
| 552 | |
| 553 | return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); |
| 554 | } |
| 555 | EXPORT_SYMBOL_GPL(fsl_edma_prep_slave_sg); |
| 556 | |
| 557 | void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan) |
| 558 | { |
| 559 | struct virt_dma_desc *vdesc; |
| 560 | |
| 561 | vdesc = vchan_next_desc(&fsl_chan->vchan); |
| 562 | if (!vdesc) |
| 563 | return; |
| 564 | fsl_chan->edesc = to_fsl_edma_desc(vdesc); |
| 565 | fsl_edma_set_tcd_regs(fsl_chan, fsl_chan->edesc->tcd[0].vtcd); |
| 566 | fsl_edma_enable_request(fsl_chan); |
| 567 | fsl_chan->status = DMA_IN_PROGRESS; |
| 568 | fsl_chan->idle = false; |
| 569 | } |
| 570 | EXPORT_SYMBOL_GPL(fsl_edma_xfer_desc); |
| 571 | |
| 572 | void fsl_edma_issue_pending(struct dma_chan *chan) |
| 573 | { |
| 574 | struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); |
| 575 | unsigned long flags; |
| 576 | |
| 577 | spin_lock_irqsave(&fsl_chan->vchan.lock, flags); |
| 578 | |
| 579 | if (unlikely(fsl_chan->pm_state != RUNNING)) { |
| 580 | spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); |
| 581 | /* cannot submit due to suspend */ |
| 582 | return; |
| 583 | } |
| 584 | |
| 585 | if (vchan_issue_pending(&fsl_chan->vchan) && !fsl_chan->edesc) |
| 586 | fsl_edma_xfer_desc(fsl_chan); |
| 587 | |
| 588 | spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); |
| 589 | } |
| 590 | EXPORT_SYMBOL_GPL(fsl_edma_issue_pending); |
| 591 | |
| 592 | int fsl_edma_alloc_chan_resources(struct dma_chan *chan) |
| 593 | { |
| 594 | struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); |
| 595 | |
| 596 | fsl_chan->tcd_pool = dma_pool_create("tcd_pool", chan->device->dev, |
| 597 | sizeof(struct fsl_edma_hw_tcd), |
| 598 | 32, 0); |
| 599 | return 0; |
| 600 | } |
| 601 | EXPORT_SYMBOL_GPL(fsl_edma_alloc_chan_resources); |
| 602 | |
| 603 | void fsl_edma_free_chan_resources(struct dma_chan *chan) |
| 604 | { |
| 605 | struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); |
| 606 | unsigned long flags; |
| 607 | LIST_HEAD(head); |
| 608 | |
| 609 | spin_lock_irqsave(&fsl_chan->vchan.lock, flags); |
| 610 | fsl_edma_disable_request(fsl_chan); |
| 611 | fsl_edma_chan_mux(fsl_chan, 0, false); |
| 612 | fsl_chan->edesc = NULL; |
| 613 | vchan_get_all_descriptors(&fsl_chan->vchan, &head); |
Laurentiu Tudor | 0fa89f9 | 2019-01-18 12:06:23 +0200 | [diff] [blame] | 614 | fsl_edma_unprep_slave_dma(fsl_chan); |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 615 | spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); |
| 616 | |
| 617 | vchan_dma_desc_free_list(&fsl_chan->vchan, &head); |
| 618 | dma_pool_destroy(fsl_chan->tcd_pool); |
| 619 | fsl_chan->tcd_pool = NULL; |
| 620 | } |
| 621 | EXPORT_SYMBOL_GPL(fsl_edma_free_chan_resources); |
| 622 | |
| 623 | void fsl_edma_cleanup_vchan(struct dma_device *dmadev) |
| 624 | { |
| 625 | struct fsl_edma_chan *chan, *_chan; |
| 626 | |
| 627 | list_for_each_entry_safe(chan, _chan, |
| 628 | &dmadev->channels, vchan.chan.device_node) { |
| 629 | list_del(&chan->vchan.chan.device_node); |
| 630 | tasklet_kill(&chan->vchan.task); |
| 631 | } |
| 632 | } |
| 633 | EXPORT_SYMBOL_GPL(fsl_edma_cleanup_vchan); |
| 634 | |
Angelo Dureghello | 377eaf3 | 2018-08-19 19:27:14 +0200 | [diff] [blame] | 635 | /* |
| 636 | * On the 32 channels Vybrid/mpc577x edma version (here called "v1"), |
| 637 | * register offsets are different compared to ColdFire mcf5441x 64 channels |
| 638 | * edma (here called "v2"). |
| 639 | * |
| 640 | * This function sets up register offsets as per proper declared version |
| 641 | * so must be called in xxx_edma_probe() just after setting the |
| 642 | * edma "version" and "membase" appropriately. |
| 643 | */ |
| 644 | void fsl_edma_setup_regs(struct fsl_edma_engine *edma) |
| 645 | { |
| 646 | edma->regs.cr = edma->membase + EDMA_CR; |
| 647 | edma->regs.es = edma->membase + EDMA_ES; |
| 648 | edma->regs.erql = edma->membase + EDMA_ERQ; |
| 649 | edma->regs.eeil = edma->membase + EDMA_EEI; |
| 650 | |
Robin Gong | af80272 | 2019-06-25 17:43:19 +0800 | [diff] [blame^] | 651 | edma->regs.serq = edma->membase + ((edma->drvdata->version == v1) ? |
Angelo Dureghello | 377eaf3 | 2018-08-19 19:27:14 +0200 | [diff] [blame] | 652 | EDMA_SERQ : EDMA64_SERQ); |
Robin Gong | af80272 | 2019-06-25 17:43:19 +0800 | [diff] [blame^] | 653 | edma->regs.cerq = edma->membase + ((edma->drvdata->version == v1) ? |
Angelo Dureghello | 377eaf3 | 2018-08-19 19:27:14 +0200 | [diff] [blame] | 654 | EDMA_CERQ : EDMA64_CERQ); |
Robin Gong | af80272 | 2019-06-25 17:43:19 +0800 | [diff] [blame^] | 655 | edma->regs.seei = edma->membase + ((edma->drvdata->version == v1) ? |
Angelo Dureghello | 377eaf3 | 2018-08-19 19:27:14 +0200 | [diff] [blame] | 656 | EDMA_SEEI : EDMA64_SEEI); |
Robin Gong | af80272 | 2019-06-25 17:43:19 +0800 | [diff] [blame^] | 657 | edma->regs.ceei = edma->membase + ((edma->drvdata->version == v1) ? |
Angelo Dureghello | 377eaf3 | 2018-08-19 19:27:14 +0200 | [diff] [blame] | 658 | EDMA_CEEI : EDMA64_CEEI); |
Robin Gong | af80272 | 2019-06-25 17:43:19 +0800 | [diff] [blame^] | 659 | edma->regs.cint = edma->membase + ((edma->drvdata->version == v1) ? |
Angelo Dureghello | 377eaf3 | 2018-08-19 19:27:14 +0200 | [diff] [blame] | 660 | EDMA_CINT : EDMA64_CINT); |
Robin Gong | af80272 | 2019-06-25 17:43:19 +0800 | [diff] [blame^] | 661 | edma->regs.cerr = edma->membase + ((edma->drvdata->version == v1) ? |
Angelo Dureghello | 377eaf3 | 2018-08-19 19:27:14 +0200 | [diff] [blame] | 662 | EDMA_CERR : EDMA64_CERR); |
Robin Gong | af80272 | 2019-06-25 17:43:19 +0800 | [diff] [blame^] | 663 | edma->regs.ssrt = edma->membase + ((edma->drvdata->version == v1) ? |
Angelo Dureghello | 377eaf3 | 2018-08-19 19:27:14 +0200 | [diff] [blame] | 664 | EDMA_SSRT : EDMA64_SSRT); |
Robin Gong | af80272 | 2019-06-25 17:43:19 +0800 | [diff] [blame^] | 665 | edma->regs.cdne = edma->membase + ((edma->drvdata->version == v1) ? |
Angelo Dureghello | 377eaf3 | 2018-08-19 19:27:14 +0200 | [diff] [blame] | 666 | EDMA_CDNE : EDMA64_CDNE); |
Robin Gong | af80272 | 2019-06-25 17:43:19 +0800 | [diff] [blame^] | 667 | edma->regs.intl = edma->membase + ((edma->drvdata->version == v1) ? |
Angelo Dureghello | 377eaf3 | 2018-08-19 19:27:14 +0200 | [diff] [blame] | 668 | EDMA_INTR : EDMA64_INTL); |
Robin Gong | af80272 | 2019-06-25 17:43:19 +0800 | [diff] [blame^] | 669 | edma->regs.errl = edma->membase + ((edma->drvdata->version == v1) ? |
Angelo Dureghello | 377eaf3 | 2018-08-19 19:27:14 +0200 | [diff] [blame] | 670 | EDMA_ERR : EDMA64_ERRL); |
| 671 | |
Robin Gong | af80272 | 2019-06-25 17:43:19 +0800 | [diff] [blame^] | 672 | if (edma->drvdata->version == v2) { |
Angelo Dureghello | 377eaf3 | 2018-08-19 19:27:14 +0200 | [diff] [blame] | 673 | edma->regs.erqh = edma->membase + EDMA64_ERQH; |
| 674 | edma->regs.eeih = edma->membase + EDMA64_EEIH; |
| 675 | edma->regs.errh = edma->membase + EDMA64_ERRH; |
| 676 | edma->regs.inth = edma->membase + EDMA64_INTH; |
| 677 | } |
| 678 | |
| 679 | edma->regs.tcd = edma->membase + EDMA_TCD; |
| 680 | } |
| 681 | EXPORT_SYMBOL_GPL(fsl_edma_setup_regs); |
| 682 | |
Angelo Dureghello | 9d83152 | 2018-08-19 19:27:13 +0200 | [diff] [blame] | 683 | MODULE_LICENSE("GPL v2"); |