| Boris BREZILLON | d7d1d45 | 2013-08-07 10:49:01 +0200 | [diff] [blame] | 1 | /* |
| 2 | * at91sama5d3_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with |
| 3 | * LCD support |
| 4 | * |
| 5 | * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> |
| 6 | * |
| 7 | * Licensed under GPLv2. |
| 8 | */ |
| 9 | |
| 10 | #include <dt-bindings/pinctrl/at91.h> |
| 11 | #include <dt-bindings/interrupt-controller/irq.h> |
| 12 | |
| 13 | / { |
| 14 | ahb { |
| 15 | apb { |
| 16 | pinctrl@fffff200 { |
| 17 | lcd { |
| 18 | pinctrl_lcd: lcd-0 { |
| 19 | atmel,pins = |
| 20 | <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA24 periph A LCDPWM */ |
| 21 | AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA26 periph A LCDVSYNC */ |
| 22 | AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA27 periph A LCDHSYNC */ |
| 23 | AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA25 periph A LCDDISP */ |
| 24 | AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA29 periph A LCDDEN */ |
| 25 | AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA28 periph A LCDPCK */ |
| 26 | AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A LCDD0 pin */ |
| 27 | AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A LCDD1 pin */ |
| 28 | AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA2 periph A LCDD2 pin */ |
| 29 | AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA3 periph A LCDD3 pin */ |
| 30 | AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA4 periph A LCDD4 pin */ |
| 31 | AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA5 periph A LCDD5 pin */ |
| 32 | AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA6 periph A LCDD6 pin */ |
| 33 | AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A LCDD7 pin */ |
| 34 | AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A LCDD8 pin */ |
| 35 | AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A LCDD9 pin */ |
| 36 | AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A LCDD10 pin */ |
| 37 | AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A LCDD11 pin */ |
| 38 | AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A LCDD12 pin */ |
| 39 | AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A LCDD13 pin */ |
| 40 | AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A LCDD14 pin */ |
| 41 | AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A LCDD15 pin */ |
| 42 | AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC14 periph C LCDD16 pin */ |
| 43 | AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC13 periph C LCDD17 pin */ |
| 44 | AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC12 periph C LCDD18 pin */ |
| 45 | AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC11 periph C LCDD19 pin */ |
| 46 | AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC10 periph C LCDD20 pin */ |
| 47 | AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC15 periph C LCDD21 pin */ |
| 48 | AT91_PIOE 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PE27 periph C LCDD22 pin */ |
| 49 | AT91_PIOE 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PE28 periph C LCDD23 pin */ |
| 50 | }; |
| 51 | }; |
| 52 | }; |
| Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 53 | |
| 54 | pmc: pmc@fffffc00 { |
| 55 | periphck { |
| 56 | lcdc_clk: lcdc_clk { |
| 57 | #clock-cells = <0>; |
| 58 | reg = <36>; |
| 59 | }; |
| 60 | }; |
| 61 | |
| 62 | systemck { |
| 63 | lcdck: lcdck { |
| 64 | #clock-cells = <0>; |
| 65 | reg = <3>; |
| 66 | clocks = <&mck>; |
| 67 | }; |
| 68 | }; |
| 69 | }; |
| Boris BREZILLON | d7d1d45 | 2013-08-07 10:49:01 +0200 | [diff] [blame] | 70 | }; |
| 71 | }; |
| 72 | }; |