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Dinh Nguyen53126a22013-09-16 15:57:48 -05001* Synopsys Designware PCIe interface
Jingoo Han340cba62013-06-21 16:24:54 +09002
3Required properties:
Lucas Stach1db823e2014-06-03 08:44:25 -06004- compatible: should contain "snps,dw-pcie" to identify the core.
Jingoo Han340cba62013-06-21 16:24:54 +09005- #address-cells: set to <3>
6- #size-cells: set to <2>
7- device_type: set to "pci"
8- ranges: ranges for the PCI memory and I/O regions
9- #interrupt-cells: set to <1>
10- interrupt-map-mask and interrupt-map: standard PCI properties
11 to define the mapping of the PCIe interface to interrupt
12 numbers.
Jingoo Han4b1ced82013-07-31 17:14:10 +090013- num-lanes: number of lanes to use
Lucas Stach1db823e2014-06-03 08:44:25 -060014- clocks: Must contain an entry for each entry in clock-names.
15 See ../clocks/clock-bindings.txt for details.
16- clock-names: Must include the following entries:
17 - "pcie"
18 - "pcie_bus"
Marek Vasutc28f8a12013-12-12 22:49:58 +010019
20Optional properties:
Jingoo Han340cba62013-06-21 16:24:54 +090021- reset-gpio: gpio pin number of power good signal