Dinh Nguyen | 53126a2 | 2013-09-16 15:57:48 -0500 | [diff] [blame] | 1 | * Synopsys Designware PCIe interface |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 2 | |
| 3 | Required properties: |
Lucas Stach | 1db823e | 2014-06-03 08:44:25 -0600 | [diff] [blame] | 4 | - compatible: should contain "snps,dw-pcie" to identify the core. |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 5 | - #address-cells: set to <3> |
| 6 | - #size-cells: set to <2> |
| 7 | - device_type: set to "pci" |
| 8 | - ranges: ranges for the PCI memory and I/O regions |
| 9 | - #interrupt-cells: set to <1> |
| 10 | - interrupt-map-mask and interrupt-map: standard PCI properties |
| 11 | to define the mapping of the PCIe interface to interrupt |
| 12 | numbers. |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 13 | - num-lanes: number of lanes to use |
Lucas Stach | 1db823e | 2014-06-03 08:44:25 -0600 | [diff] [blame] | 14 | - clocks: Must contain an entry for each entry in clock-names. |
| 15 | See ../clocks/clock-bindings.txt for details. |
| 16 | - clock-names: Must include the following entries: |
| 17 | - "pcie" |
| 18 | - "pcie_bus" |
Marek Vasut | c28f8a1 | 2013-12-12 22:49:58 +0100 | [diff] [blame] | 19 | |
| 20 | Optional properties: |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 21 | - reset-gpio: gpio pin number of power good signal |