blob: 354b8cd5537f8702b513c9106fbeec91d9ca9ac5 [file] [log] [blame]
Thomas Gleixnerfd534e92019-05-23 11:14:39 +02001// SPDX-License-Identifier: GPL-2.0-or-later
Dan Williams0a82a622009-07-14 12:20:37 -07002/*
3 * Asynchronous RAID-6 recovery calculations ASYNC_TX API.
4 * Copyright(c) 2009 Intel Corporation
5 *
6 * based on raid6recov.c:
7 * Copyright 2002 H. Peter Anvin
Dan Williams0a82a622009-07-14 12:20:37 -07008 */
9#include <linux/kernel.h>
10#include <linux/interrupt.h>
Paul Gortmaker4bb33cc2011-05-27 14:41:48 -040011#include <linux/module.h>
Dan Williams0a82a622009-07-14 12:20:37 -070012#include <linux/dma-mapping.h>
13#include <linux/raid/pq.h>
14#include <linux/async_tx.h>
Dan Williams3bbdd492013-10-18 19:35:28 +020015#include <linux/dmaengine.h>
Dan Williams0a82a622009-07-14 12:20:37 -070016
17static struct dma_async_tx_descriptor *
Yufen Yu4f86ff52020-08-20 09:22:11 -040018async_sum_product(struct page *dest, unsigned int d_off,
19 struct page **srcs, unsigned int *src_offs, unsigned char *coef,
20 size_t len, struct async_submit_ctl *submit)
Dan Williams0a82a622009-07-14 12:20:37 -070021{
22 struct dma_chan *chan = async_tx_find_channel(submit, DMA_PQ,
23 &dest, 1, srcs, 2, len);
24 struct dma_device *dma = chan ? chan->device : NULL;
Dan Williams3bbdd492013-10-18 19:35:28 +020025 struct dmaengine_unmap_data *unmap = NULL;
Dan Williams0a82a622009-07-14 12:20:37 -070026 const u8 *amul, *bmul;
27 u8 ax, bx;
28 u8 *a, *b, *c;
29
Dan Williams3bbdd492013-10-18 19:35:28 +020030 if (dma)
NeilBrownb02bab62016-01-07 11:02:34 +110031 unmap = dmaengine_get_unmap_data(dma->dev, 3, GFP_NOWAIT);
Dan Williams3bbdd492013-10-18 19:35:28 +020032
33 if (unmap) {
Dan Williams0a82a622009-07-14 12:20:37 -070034 struct device *dev = dma->dev;
Dan Williams3bbdd492013-10-18 19:35:28 +020035 dma_addr_t pq[2];
Dan Williams0a82a622009-07-14 12:20:37 -070036 struct dma_async_tx_descriptor *tx;
Bartlomiej Zolnierkiewicz0776ae72013-10-18 19:35:33 +020037 enum dma_ctrl_flags dma_flags = DMA_PREP_PQ_DISABLE_P;
Dan Williams0a82a622009-07-14 12:20:37 -070038
Dan Williams0403e382009-09-08 17:42:50 -070039 if (submit->flags & ASYNC_TX_FENCE)
40 dma_flags |= DMA_PREP_FENCE;
Yufen Yu4f86ff52020-08-20 09:22:11 -040041 unmap->addr[0] = dma_map_page(dev, srcs[0], src_offs[0],
42 len, DMA_TO_DEVICE);
43 unmap->addr[1] = dma_map_page(dev, srcs[1], src_offs[1],
44 len, DMA_TO_DEVICE);
Dan Williams3bbdd492013-10-18 19:35:28 +020045 unmap->to_cnt = 2;
46
Yufen Yu4f86ff52020-08-20 09:22:11 -040047 unmap->addr[2] = dma_map_page(dev, dest, d_off,
48 len, DMA_BIDIRECTIONAL);
Dan Williams3bbdd492013-10-18 19:35:28 +020049 unmap->bidi_cnt = 1;
50 /* engine only looks at Q, but expects it to follow P */
51 pq[1] = unmap->addr[2];
52
53 unmap->len = len;
54 tx = dma->device_prep_dma_pq(chan, pq, unmap->addr, 2, coef,
Dan Williams0a82a622009-07-14 12:20:37 -070055 len, dma_flags);
56 if (tx) {
Dan Williams3bbdd492013-10-18 19:35:28 +020057 dma_set_unmap(tx, unmap);
Dan Williams0a82a622009-07-14 12:20:37 -070058 async_tx_submit(chan, tx, submit);
Dan Williams3bbdd492013-10-18 19:35:28 +020059 dmaengine_unmap_put(unmap);
Dan Williams0a82a622009-07-14 12:20:37 -070060 return tx;
61 }
Dan Williams1f6672d2009-09-21 10:47:40 -070062
63 /* could not get a descriptor, unmap and fall through to
64 * the synchronous path
65 */
Dan Williams3bbdd492013-10-18 19:35:28 +020066 dmaengine_unmap_put(unmap);
Dan Williams0a82a622009-07-14 12:20:37 -070067 }
68
69 /* run the operation synchronously */
70 async_tx_quiesce(&submit->depend_tx);
71 amul = raid6_gfmul[coef[0]];
72 bmul = raid6_gfmul[coef[1]];
Yufen Yu4f86ff52020-08-20 09:22:11 -040073 a = page_address(srcs[0]) + src_offs[0];
74 b = page_address(srcs[1]) + src_offs[1];
75 c = page_address(dest) + d_off;
Dan Williams0a82a622009-07-14 12:20:37 -070076
77 while (len--) {
78 ax = amul[*a++];
79 bx = bmul[*b++];
80 *c++ = ax ^ bx;
81 }
82
83 return NULL;
84}
85
86static struct dma_async_tx_descriptor *
Yufen Yu4f86ff52020-08-20 09:22:11 -040087async_mult(struct page *dest, unsigned int d_off, struct page *src,
88 unsigned int s_off, u8 coef, size_t len,
89 struct async_submit_ctl *submit)
Dan Williams0a82a622009-07-14 12:20:37 -070090{
91 struct dma_chan *chan = async_tx_find_channel(submit, DMA_PQ,
92 &dest, 1, &src, 1, len);
93 struct dma_device *dma = chan ? chan->device : NULL;
Dan Williams3bbdd492013-10-18 19:35:28 +020094 struct dmaengine_unmap_data *unmap = NULL;
Dan Williams0a82a622009-07-14 12:20:37 -070095 const u8 *qmul; /* Q multiplier table */
96 u8 *d, *s;
97
Dan Williams3bbdd492013-10-18 19:35:28 +020098 if (dma)
NeilBrownb02bab62016-01-07 11:02:34 +110099 unmap = dmaengine_get_unmap_data(dma->dev, 3, GFP_NOWAIT);
Dan Williams3bbdd492013-10-18 19:35:28 +0200100
101 if (unmap) {
Dan Williams0a82a622009-07-14 12:20:37 -0700102 dma_addr_t dma_dest[2];
Dan Williams0a82a622009-07-14 12:20:37 -0700103 struct device *dev = dma->dev;
104 struct dma_async_tx_descriptor *tx;
Bartlomiej Zolnierkiewicz0776ae72013-10-18 19:35:33 +0200105 enum dma_ctrl_flags dma_flags = DMA_PREP_PQ_DISABLE_P;
Dan Williams0a82a622009-07-14 12:20:37 -0700106
Dan Williams0403e382009-09-08 17:42:50 -0700107 if (submit->flags & ASYNC_TX_FENCE)
108 dma_flags |= DMA_PREP_FENCE;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400109 unmap->addr[0] = dma_map_page(dev, src, s_off,
110 len, DMA_TO_DEVICE);
Dan Williams3bbdd492013-10-18 19:35:28 +0200111 unmap->to_cnt++;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400112 unmap->addr[1] = dma_map_page(dev, dest, d_off,
113 len, DMA_BIDIRECTIONAL);
Dan Williams3bbdd492013-10-18 19:35:28 +0200114 dma_dest[1] = unmap->addr[1];
115 unmap->bidi_cnt++;
116 unmap->len = len;
117
118 /* this looks funny, but the engine looks for Q at
119 * dma_dest[1] and ignores dma_dest[0] as a dest
120 * due to DMA_PREP_PQ_DISABLE_P
121 */
122 tx = dma->device_prep_dma_pq(chan, dma_dest, unmap->addr,
123 1, &coef, len, dma_flags);
124
Dan Williams0a82a622009-07-14 12:20:37 -0700125 if (tx) {
Dan Williams3bbdd492013-10-18 19:35:28 +0200126 dma_set_unmap(tx, unmap);
127 dmaengine_unmap_put(unmap);
Dan Williams0a82a622009-07-14 12:20:37 -0700128 async_tx_submit(chan, tx, submit);
129 return tx;
130 }
Dan Williams1f6672d2009-09-21 10:47:40 -0700131
132 /* could not get a descriptor, unmap and fall through to
133 * the synchronous path
134 */
Dan Williams3bbdd492013-10-18 19:35:28 +0200135 dmaengine_unmap_put(unmap);
Dan Williams0a82a622009-07-14 12:20:37 -0700136 }
137
138 /* no channel available, or failed to allocate a descriptor, so
139 * perform the operation synchronously
140 */
141 async_tx_quiesce(&submit->depend_tx);
142 qmul = raid6_gfmul[coef];
Yufen Yu4f86ff52020-08-20 09:22:11 -0400143 d = page_address(dest) + d_off;
144 s = page_address(src) + s_off;
Dan Williams0a82a622009-07-14 12:20:37 -0700145
146 while (len--)
147 *d++ = qmul[*s++];
148
149 return NULL;
150}
151
152static struct dma_async_tx_descriptor *
Dan Williamsda17bf42009-10-19 14:05:12 -0700153__2data_recov_4(int disks, size_t bytes, int faila, int failb,
Yufen Yu4f86ff52020-08-20 09:22:11 -0400154 struct page **blocks, unsigned int *offs,
155 struct async_submit_ctl *submit)
Dan Williams0a82a622009-07-14 12:20:37 -0700156{
157 struct dma_async_tx_descriptor *tx = NULL;
158 struct page *p, *q, *a, *b;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400159 unsigned int p_off, q_off, a_off, b_off;
Dan Williams0a82a622009-07-14 12:20:37 -0700160 struct page *srcs[2];
Yufen Yu4f86ff52020-08-20 09:22:11 -0400161 unsigned int src_offs[2];
Dan Williams0a82a622009-07-14 12:20:37 -0700162 unsigned char coef[2];
163 enum async_tx_flags flags = submit->flags;
164 dma_async_tx_callback cb_fn = submit->cb_fn;
165 void *cb_param = submit->cb_param;
166 void *scribble = submit->scribble;
167
Dan Williamsda17bf42009-10-19 14:05:12 -0700168 p = blocks[disks-2];
Yufen Yu4f86ff52020-08-20 09:22:11 -0400169 p_off = offs[disks-2];
Dan Williamsda17bf42009-10-19 14:05:12 -0700170 q = blocks[disks-1];
Yufen Yu4f86ff52020-08-20 09:22:11 -0400171 q_off = offs[disks-1];
Dan Williams0a82a622009-07-14 12:20:37 -0700172
173 a = blocks[faila];
Yufen Yu4f86ff52020-08-20 09:22:11 -0400174 a_off = offs[faila];
Dan Williams0a82a622009-07-14 12:20:37 -0700175 b = blocks[failb];
Yufen Yu4f86ff52020-08-20 09:22:11 -0400176 b_off = offs[failb];
Dan Williams0a82a622009-07-14 12:20:37 -0700177
178 /* in the 4 disk case P + Pxy == P and Q + Qxy == Q */
179 /* Dx = A*(P+Pxy) + B*(Q+Qxy) */
180 srcs[0] = p;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400181 src_offs[0] = p_off;
Dan Williams0a82a622009-07-14 12:20:37 -0700182 srcs[1] = q;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400183 src_offs[1] = q_off;
Dan Williams0a82a622009-07-14 12:20:37 -0700184 coef[0] = raid6_gfexi[failb-faila];
185 coef[1] = raid6_gfinv[raid6_gfexp[faila]^raid6_gfexp[failb]];
Dan Williams0403e382009-09-08 17:42:50 -0700186 init_async_submit(submit, ASYNC_TX_FENCE, tx, NULL, NULL, scribble);
Yufen Yu4f86ff52020-08-20 09:22:11 -0400187 tx = async_sum_product(b, b_off, srcs, src_offs, coef, bytes, submit);
Dan Williams0a82a622009-07-14 12:20:37 -0700188
189 /* Dy = P+Pxy+Dx */
190 srcs[0] = p;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400191 src_offs[0] = p_off;
Dan Williams0a82a622009-07-14 12:20:37 -0700192 srcs[1] = b;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400193 src_offs[1] = b_off;
Dan Williams0a82a622009-07-14 12:20:37 -0700194 init_async_submit(submit, flags | ASYNC_TX_XOR_ZERO_DST, tx, cb_fn,
195 cb_param, scribble);
Yufen Yu4f86ff52020-08-20 09:22:11 -0400196 tx = async_xor_offs(a, a_off, srcs, src_offs, 2, bytes, submit);
Dan Williams0a82a622009-07-14 12:20:37 -0700197
198 return tx;
199
200}
201
202static struct dma_async_tx_descriptor *
Dan Williamsda17bf42009-10-19 14:05:12 -0700203__2data_recov_5(int disks, size_t bytes, int faila, int failb,
Yufen Yu4f86ff52020-08-20 09:22:11 -0400204 struct page **blocks, unsigned int *offs,
205 struct async_submit_ctl *submit)
Dan Williams0a82a622009-07-14 12:20:37 -0700206{
207 struct dma_async_tx_descriptor *tx = NULL;
208 struct page *p, *q, *g, *dp, *dq;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400209 unsigned int p_off, q_off, g_off, dp_off, dq_off;
Dan Williams0a82a622009-07-14 12:20:37 -0700210 struct page *srcs[2];
Yufen Yu4f86ff52020-08-20 09:22:11 -0400211 unsigned int src_offs[2];
Dan Williams0a82a622009-07-14 12:20:37 -0700212 unsigned char coef[2];
213 enum async_tx_flags flags = submit->flags;
214 dma_async_tx_callback cb_fn = submit->cb_fn;
215 void *cb_param = submit->cb_param;
216 void *scribble = submit->scribble;
Dan Williamsda17bf42009-10-19 14:05:12 -0700217 int good_srcs, good, i;
Dan Williams0a82a622009-07-14 12:20:37 -0700218
Dan Williamsda17bf42009-10-19 14:05:12 -0700219 good_srcs = 0;
220 good = -1;
221 for (i = 0; i < disks-2; i++) {
222 if (blocks[i] == NULL)
223 continue;
Dan Williams0a82a622009-07-14 12:20:37 -0700224 if (i == faila || i == failb)
225 continue;
Dan Williamsda17bf42009-10-19 14:05:12 -0700226 good = i;
227 good_srcs++;
Dan Williams0a82a622009-07-14 12:20:37 -0700228 }
Dan Williamsda17bf42009-10-19 14:05:12 -0700229 BUG_ON(good_srcs > 1);
Dan Williams0a82a622009-07-14 12:20:37 -0700230
Dan Williamsda17bf42009-10-19 14:05:12 -0700231 p = blocks[disks-2];
Yufen Yu4f86ff52020-08-20 09:22:11 -0400232 p_off = offs[disks-2];
Dan Williamsda17bf42009-10-19 14:05:12 -0700233 q = blocks[disks-1];
Yufen Yu4f86ff52020-08-20 09:22:11 -0400234 q_off = offs[disks-1];
Dan Williams0a82a622009-07-14 12:20:37 -0700235 g = blocks[good];
Yufen Yu4f86ff52020-08-20 09:22:11 -0400236 g_off = offs[good];
Dan Williams0a82a622009-07-14 12:20:37 -0700237
238 /* Compute syndrome with zero for the missing data pages
239 * Use the dead data pages as temporary storage for delta p and
240 * delta q
241 */
242 dp = blocks[faila];
Yufen Yu4f86ff52020-08-20 09:22:11 -0400243 dp_off = offs[faila];
Dan Williams0a82a622009-07-14 12:20:37 -0700244 dq = blocks[failb];
Yufen Yu4f86ff52020-08-20 09:22:11 -0400245 dq_off = offs[failb];
Dan Williams0a82a622009-07-14 12:20:37 -0700246
Dan Williams0403e382009-09-08 17:42:50 -0700247 init_async_submit(submit, ASYNC_TX_FENCE, tx, NULL, NULL, scribble);
Yufen Yu4f86ff52020-08-20 09:22:11 -0400248 tx = async_memcpy(dp, g, dp_off, g_off, bytes, submit);
Dan Williams0403e382009-09-08 17:42:50 -0700249 init_async_submit(submit, ASYNC_TX_FENCE, tx, NULL, NULL, scribble);
Yufen Yu4f86ff52020-08-20 09:22:11 -0400250 tx = async_mult(dq, dq_off, g, g_off,
251 raid6_gfexp[good], bytes, submit);
Dan Williams0a82a622009-07-14 12:20:37 -0700252
253 /* compute P + Pxy */
254 srcs[0] = dp;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400255 src_offs[0] = dp_off;
Dan Williams0a82a622009-07-14 12:20:37 -0700256 srcs[1] = p;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400257 src_offs[1] = p_off;
Dan Williams0403e382009-09-08 17:42:50 -0700258 init_async_submit(submit, ASYNC_TX_FENCE|ASYNC_TX_XOR_DROP_DST, tx,
259 NULL, NULL, scribble);
Yufen Yu4f86ff52020-08-20 09:22:11 -0400260 tx = async_xor_offs(dp, dp_off, srcs, src_offs, 2, bytes, submit);
Dan Williams0a82a622009-07-14 12:20:37 -0700261
262 /* compute Q + Qxy */
263 srcs[0] = dq;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400264 src_offs[0] = dq_off;
Dan Williams0a82a622009-07-14 12:20:37 -0700265 srcs[1] = q;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400266 src_offs[1] = q_off;
Dan Williams0403e382009-09-08 17:42:50 -0700267 init_async_submit(submit, ASYNC_TX_FENCE|ASYNC_TX_XOR_DROP_DST, tx,
268 NULL, NULL, scribble);
Yufen Yu4f86ff52020-08-20 09:22:11 -0400269 tx = async_xor_offs(dq, dq_off, srcs, src_offs, 2, bytes, submit);
Dan Williams0a82a622009-07-14 12:20:37 -0700270
271 /* Dx = A*(P+Pxy) + B*(Q+Qxy) */
272 srcs[0] = dp;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400273 src_offs[0] = dp_off;
Dan Williams0a82a622009-07-14 12:20:37 -0700274 srcs[1] = dq;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400275 src_offs[1] = dq_off;
Dan Williams0a82a622009-07-14 12:20:37 -0700276 coef[0] = raid6_gfexi[failb-faila];
277 coef[1] = raid6_gfinv[raid6_gfexp[faila]^raid6_gfexp[failb]];
Dan Williams0403e382009-09-08 17:42:50 -0700278 init_async_submit(submit, ASYNC_TX_FENCE, tx, NULL, NULL, scribble);
Yufen Yu4f86ff52020-08-20 09:22:11 -0400279 tx = async_sum_product(dq, dq_off, srcs, src_offs, coef, bytes, submit);
Dan Williams0a82a622009-07-14 12:20:37 -0700280
281 /* Dy = P+Pxy+Dx */
282 srcs[0] = dp;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400283 src_offs[0] = dp_off;
Dan Williams0a82a622009-07-14 12:20:37 -0700284 srcs[1] = dq;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400285 src_offs[1] = dq_off;
Dan Williams0a82a622009-07-14 12:20:37 -0700286 init_async_submit(submit, flags | ASYNC_TX_XOR_DROP_DST, tx, cb_fn,
287 cb_param, scribble);
Yufen Yu4f86ff52020-08-20 09:22:11 -0400288 tx = async_xor_offs(dp, dp_off, srcs, src_offs, 2, bytes, submit);
Dan Williams0a82a622009-07-14 12:20:37 -0700289
290 return tx;
291}
292
293static struct dma_async_tx_descriptor *
294__2data_recov_n(int disks, size_t bytes, int faila, int failb,
Yufen Yu4f86ff52020-08-20 09:22:11 -0400295 struct page **blocks, unsigned int *offs,
296 struct async_submit_ctl *submit)
Dan Williams0a82a622009-07-14 12:20:37 -0700297{
298 struct dma_async_tx_descriptor *tx = NULL;
299 struct page *p, *q, *dp, *dq;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400300 unsigned int p_off, q_off, dp_off, dq_off;
Dan Williams0a82a622009-07-14 12:20:37 -0700301 struct page *srcs[2];
Yufen Yu4f86ff52020-08-20 09:22:11 -0400302 unsigned int src_offs[2];
Dan Williams0a82a622009-07-14 12:20:37 -0700303 unsigned char coef[2];
304 enum async_tx_flags flags = submit->flags;
305 dma_async_tx_callback cb_fn = submit->cb_fn;
306 void *cb_param = submit->cb_param;
307 void *scribble = submit->scribble;
308
309 p = blocks[disks-2];
Yufen Yu4f86ff52020-08-20 09:22:11 -0400310 p_off = offs[disks-2];
Dan Williams0a82a622009-07-14 12:20:37 -0700311 q = blocks[disks-1];
Yufen Yu4f86ff52020-08-20 09:22:11 -0400312 q_off = offs[disks-1];
Dan Williams0a82a622009-07-14 12:20:37 -0700313
314 /* Compute syndrome with zero for the missing data pages
315 * Use the dead data pages as temporary storage for
316 * delta p and delta q
317 */
318 dp = blocks[faila];
Yufen Yu4f86ff52020-08-20 09:22:11 -0400319 dp_off = offs[faila];
NeilBrown5dd33c92009-10-16 16:40:25 +1100320 blocks[faila] = NULL;
Dan Williams0a82a622009-07-14 12:20:37 -0700321 blocks[disks-2] = dp;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400322 offs[disks-2] = dp_off;
Dan Williams0a82a622009-07-14 12:20:37 -0700323 dq = blocks[failb];
Yufen Yu4f86ff52020-08-20 09:22:11 -0400324 dq_off = offs[failb];
NeilBrown5dd33c92009-10-16 16:40:25 +1100325 blocks[failb] = NULL;
Dan Williams0a82a622009-07-14 12:20:37 -0700326 blocks[disks-1] = dq;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400327 offs[disks-1] = dq_off;
Dan Williams0a82a622009-07-14 12:20:37 -0700328
Dan Williams0403e382009-09-08 17:42:50 -0700329 init_async_submit(submit, ASYNC_TX_FENCE, tx, NULL, NULL, scribble);
Yufen Yu4f86ff52020-08-20 09:22:11 -0400330 tx = async_gen_syndrome(blocks, offs, disks, bytes, submit);
Dan Williams0a82a622009-07-14 12:20:37 -0700331
332 /* Restore pointer table */
333 blocks[faila] = dp;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400334 offs[faila] = dp_off;
Dan Williams0a82a622009-07-14 12:20:37 -0700335 blocks[failb] = dq;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400336 offs[failb] = dq_off;
Dan Williams0a82a622009-07-14 12:20:37 -0700337 blocks[disks-2] = p;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400338 offs[disks-2] = p_off;
Dan Williams0a82a622009-07-14 12:20:37 -0700339 blocks[disks-1] = q;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400340 offs[disks-1] = q_off;
Dan Williams0a82a622009-07-14 12:20:37 -0700341
342 /* compute P + Pxy */
343 srcs[0] = dp;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400344 src_offs[0] = dp_off;
Dan Williams0a82a622009-07-14 12:20:37 -0700345 srcs[1] = p;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400346 src_offs[1] = p_off;
Dan Williams0403e382009-09-08 17:42:50 -0700347 init_async_submit(submit, ASYNC_TX_FENCE|ASYNC_TX_XOR_DROP_DST, tx,
348 NULL, NULL, scribble);
Yufen Yu4f86ff52020-08-20 09:22:11 -0400349 tx = async_xor_offs(dp, dp_off, srcs, src_offs, 2, bytes, submit);
Dan Williams0a82a622009-07-14 12:20:37 -0700350
351 /* compute Q + Qxy */
352 srcs[0] = dq;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400353 src_offs[0] = dq_off;
Dan Williams0a82a622009-07-14 12:20:37 -0700354 srcs[1] = q;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400355 src_offs[1] = q_off;
Dan Williams0403e382009-09-08 17:42:50 -0700356 init_async_submit(submit, ASYNC_TX_FENCE|ASYNC_TX_XOR_DROP_DST, tx,
357 NULL, NULL, scribble);
Yufen Yu4f86ff52020-08-20 09:22:11 -0400358 tx = async_xor_offs(dq, dq_off, srcs, src_offs, 2, bytes, submit);
Dan Williams0a82a622009-07-14 12:20:37 -0700359
360 /* Dx = A*(P+Pxy) + B*(Q+Qxy) */
361 srcs[0] = dp;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400362 src_offs[0] = dp_off;
Dan Williams0a82a622009-07-14 12:20:37 -0700363 srcs[1] = dq;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400364 src_offs[1] = dq_off;
Dan Williams0a82a622009-07-14 12:20:37 -0700365 coef[0] = raid6_gfexi[failb-faila];
366 coef[1] = raid6_gfinv[raid6_gfexp[faila]^raid6_gfexp[failb]];
Dan Williams0403e382009-09-08 17:42:50 -0700367 init_async_submit(submit, ASYNC_TX_FENCE, tx, NULL, NULL, scribble);
Yufen Yu4f86ff52020-08-20 09:22:11 -0400368 tx = async_sum_product(dq, dq_off, srcs, src_offs, coef, bytes, submit);
Dan Williams0a82a622009-07-14 12:20:37 -0700369
370 /* Dy = P+Pxy+Dx */
371 srcs[0] = dp;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400372 src_offs[0] = dp_off;
Dan Williams0a82a622009-07-14 12:20:37 -0700373 srcs[1] = dq;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400374 src_offs[1] = dq_off;
Dan Williams0a82a622009-07-14 12:20:37 -0700375 init_async_submit(submit, flags | ASYNC_TX_XOR_DROP_DST, tx, cb_fn,
376 cb_param, scribble);
Yufen Yu4f86ff52020-08-20 09:22:11 -0400377 tx = async_xor_offs(dp, dp_off, srcs, src_offs, 2, bytes, submit);
Dan Williams0a82a622009-07-14 12:20:37 -0700378
379 return tx;
380}
381
382/**
383 * async_raid6_2data_recov - asynchronously calculate two missing data blocks
384 * @disks: number of disks in the RAID-6 array
385 * @bytes: block size
386 * @faila: first failed drive index
387 * @failb: second failed drive index
388 * @blocks: array of source pointers where the last two entries are p and q
Yufen Yu4f86ff52020-08-20 09:22:11 -0400389 * @offs: array of offset for pages in blocks
Dan Williams0a82a622009-07-14 12:20:37 -0700390 * @submit: submission/completion modifiers
391 */
392struct dma_async_tx_descriptor *
393async_raid6_2data_recov(int disks, size_t bytes, int faila, int failb,
Yufen Yu4f86ff52020-08-20 09:22:11 -0400394 struct page **blocks, unsigned int *offs,
395 struct async_submit_ctl *submit)
Dan Williams0a82a622009-07-14 12:20:37 -0700396{
Dan Williams5157b4a2010-05-04 20:41:56 -0700397 void *scribble = submit->scribble;
Dan Williamsda17bf42009-10-19 14:05:12 -0700398 int non_zero_srcs, i;
399
Dan Williams0a82a622009-07-14 12:20:37 -0700400 BUG_ON(faila == failb);
401 if (failb < faila)
402 swap(faila, failb);
403
404 pr_debug("%s: disks: %d len: %zu\n", __func__, disks, bytes);
405
Dan Williams5157b4a2010-05-04 20:41:56 -0700406 /* if a dma resource is not available or a scribble buffer is not
407 * available punt to the synchronous path. In the 'dma not
408 * available' case be sure to use the scribble buffer to
409 * preserve the content of 'blocks' as the caller intended.
Dan Williams0a82a622009-07-14 12:20:37 -0700410 */
Dan Williams5157b4a2010-05-04 20:41:56 -0700411 if (!async_dma_find_channel(DMA_PQ) || !scribble) {
412 void **ptrs = scribble ? scribble : (void **) blocks;
Dan Williams0a82a622009-07-14 12:20:37 -0700413
414 async_tx_quiesce(&submit->depend_tx);
415 for (i = 0; i < disks; i++)
NeilBrown5dd33c92009-10-16 16:40:25 +1100416 if (blocks[i] == NULL)
Dan Williamsda17bf42009-10-19 14:05:12 -0700417 ptrs[i] = (void *) raid6_empty_zero_page;
NeilBrown5dd33c92009-10-16 16:40:25 +1100418 else
Yufen Yu4f86ff52020-08-20 09:22:11 -0400419 ptrs[i] = page_address(blocks[i]) + offs[i];
Dan Williams0a82a622009-07-14 12:20:37 -0700420
421 raid6_2data_recov(disks, bytes, faila, failb, ptrs);
422
423 async_tx_sync_epilog(submit);
424
425 return NULL;
426 }
427
Dan Williamsda17bf42009-10-19 14:05:12 -0700428 non_zero_srcs = 0;
429 for (i = 0; i < disks-2 && non_zero_srcs < 4; i++)
430 if (blocks[i])
431 non_zero_srcs++;
432 switch (non_zero_srcs) {
433 case 0:
434 case 1:
435 /* There must be at least 2 sources - the failed devices. */
436 BUG();
437
438 case 2:
Dan Williams0a82a622009-07-14 12:20:37 -0700439 /* dma devices do not uniformly understand a zero source pq
440 * operation (in contrast to the synchronous case), so
Dan Williamsda17bf42009-10-19 14:05:12 -0700441 * explicitly handle the special case of a 4 disk array with
442 * both data disks missing.
Dan Williams0a82a622009-07-14 12:20:37 -0700443 */
Yufen Yu4f86ff52020-08-20 09:22:11 -0400444 return __2data_recov_4(disks, bytes, faila, failb,
445 blocks, offs, submit);
Dan Williamsda17bf42009-10-19 14:05:12 -0700446 case 3:
Dan Williams0a82a622009-07-14 12:20:37 -0700447 /* dma devices do not uniformly understand a single
448 * source pq operation (in contrast to the synchronous
Dan Williamsda17bf42009-10-19 14:05:12 -0700449 * case), so explicitly handle the special case of a 5 disk
450 * array with 2 of 3 data disks missing.
Dan Williams0a82a622009-07-14 12:20:37 -0700451 */
Yufen Yu4f86ff52020-08-20 09:22:11 -0400452 return __2data_recov_5(disks, bytes, faila, failb,
453 blocks, offs, submit);
Dan Williams0a82a622009-07-14 12:20:37 -0700454 default:
Yufen Yu4f86ff52020-08-20 09:22:11 -0400455 return __2data_recov_n(disks, bytes, faila, failb,
456 blocks, offs, submit);
Dan Williams0a82a622009-07-14 12:20:37 -0700457 }
458}
459EXPORT_SYMBOL_GPL(async_raid6_2data_recov);
460
461/**
462 * async_raid6_datap_recov - asynchronously calculate a data and the 'p' block
463 * @disks: number of disks in the RAID-6 array
464 * @bytes: block size
465 * @faila: failed drive index
466 * @blocks: array of source pointers where the last two entries are p and q
Yufen Yu4f86ff52020-08-20 09:22:11 -0400467 * @offs: array of offset for pages in blocks
Dan Williams0a82a622009-07-14 12:20:37 -0700468 * @submit: submission/completion modifiers
469 */
470struct dma_async_tx_descriptor *
471async_raid6_datap_recov(int disks, size_t bytes, int faila,
Yufen Yu4f86ff52020-08-20 09:22:11 -0400472 struct page **blocks, unsigned int *offs,
473 struct async_submit_ctl *submit)
Dan Williams0a82a622009-07-14 12:20:37 -0700474{
475 struct dma_async_tx_descriptor *tx = NULL;
476 struct page *p, *q, *dq;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400477 unsigned int p_off, q_off, dq_off;
Dan Williams0a82a622009-07-14 12:20:37 -0700478 u8 coef;
479 enum async_tx_flags flags = submit->flags;
480 dma_async_tx_callback cb_fn = submit->cb_fn;
481 void *cb_param = submit->cb_param;
482 void *scribble = submit->scribble;
Dan Williamsda17bf42009-10-19 14:05:12 -0700483 int good_srcs, good, i;
Dan Williams0a82a622009-07-14 12:20:37 -0700484 struct page *srcs[2];
Yufen Yu4f86ff52020-08-20 09:22:11 -0400485 unsigned int src_offs[2];
Dan Williams0a82a622009-07-14 12:20:37 -0700486
487 pr_debug("%s: disks: %d len: %zu\n", __func__, disks, bytes);
488
Dan Williams5157b4a2010-05-04 20:41:56 -0700489 /* if a dma resource is not available or a scribble buffer is not
490 * available punt to the synchronous path. In the 'dma not
491 * available' case be sure to use the scribble buffer to
492 * preserve the content of 'blocks' as the caller intended.
Dan Williams0a82a622009-07-14 12:20:37 -0700493 */
Dan Williams5157b4a2010-05-04 20:41:56 -0700494 if (!async_dma_find_channel(DMA_PQ) || !scribble) {
495 void **ptrs = scribble ? scribble : (void **) blocks;
Dan Williams0a82a622009-07-14 12:20:37 -0700496
497 async_tx_quiesce(&submit->depend_tx);
498 for (i = 0; i < disks; i++)
NeilBrown5dd33c92009-10-16 16:40:25 +1100499 if (blocks[i] == NULL)
500 ptrs[i] = (void*)raid6_empty_zero_page;
501 else
Yufen Yu4f86ff52020-08-20 09:22:11 -0400502 ptrs[i] = page_address(blocks[i]) + offs[i];
Dan Williams0a82a622009-07-14 12:20:37 -0700503
504 raid6_datap_recov(disks, bytes, faila, ptrs);
505
506 async_tx_sync_epilog(submit);
507
508 return NULL;
509 }
510
Dan Williamsda17bf42009-10-19 14:05:12 -0700511 good_srcs = 0;
512 good = -1;
513 for (i = 0; i < disks-2; i++) {
514 if (i == faila)
515 continue;
516 if (blocks[i]) {
517 good = i;
518 good_srcs++;
519 if (good_srcs > 1)
520 break;
521 }
522 }
523 BUG_ON(good_srcs == 0);
524
Dan Williams0a82a622009-07-14 12:20:37 -0700525 p = blocks[disks-2];
Yufen Yu4f86ff52020-08-20 09:22:11 -0400526 p_off = offs[disks-2];
Dan Williams0a82a622009-07-14 12:20:37 -0700527 q = blocks[disks-1];
Yufen Yu4f86ff52020-08-20 09:22:11 -0400528 q_off = offs[disks-1];
Dan Williams0a82a622009-07-14 12:20:37 -0700529
530 /* Compute syndrome with zero for the missing data page
531 * Use the dead data page as temporary storage for delta q
532 */
533 dq = blocks[faila];
Yufen Yu4f86ff52020-08-20 09:22:11 -0400534 dq_off = offs[faila];
NeilBrown5dd33c92009-10-16 16:40:25 +1100535 blocks[faila] = NULL;
Dan Williams0a82a622009-07-14 12:20:37 -0700536 blocks[disks-1] = dq;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400537 offs[disks-1] = dq_off;
Dan Williams0a82a622009-07-14 12:20:37 -0700538
Dan Williamsda17bf42009-10-19 14:05:12 -0700539 /* in the 4-disk case we only need to perform a single source
540 * multiplication with the one good data block.
Dan Williams0a82a622009-07-14 12:20:37 -0700541 */
Dan Williamsda17bf42009-10-19 14:05:12 -0700542 if (good_srcs == 1) {
Dan Williams0a82a622009-07-14 12:20:37 -0700543 struct page *g = blocks[good];
Yufen Yu4f86ff52020-08-20 09:22:11 -0400544 unsigned int g_off = offs[good];
Dan Williams0a82a622009-07-14 12:20:37 -0700545
Dan Williams0403e382009-09-08 17:42:50 -0700546 init_async_submit(submit, ASYNC_TX_FENCE, tx, NULL, NULL,
547 scribble);
Yufen Yu4f86ff52020-08-20 09:22:11 -0400548 tx = async_memcpy(p, g, p_off, g_off, bytes, submit);
Dan Williams0a82a622009-07-14 12:20:37 -0700549
Dan Williams0403e382009-09-08 17:42:50 -0700550 init_async_submit(submit, ASYNC_TX_FENCE, tx, NULL, NULL,
551 scribble);
Yufen Yu4f86ff52020-08-20 09:22:11 -0400552 tx = async_mult(dq, dq_off, g, g_off,
553 raid6_gfexp[good], bytes, submit);
Dan Williams0a82a622009-07-14 12:20:37 -0700554 } else {
Dan Williams0403e382009-09-08 17:42:50 -0700555 init_async_submit(submit, ASYNC_TX_FENCE, tx, NULL, NULL,
556 scribble);
Yufen Yu4f86ff52020-08-20 09:22:11 -0400557 tx = async_gen_syndrome(blocks, offs, disks, bytes, submit);
Dan Williams0a82a622009-07-14 12:20:37 -0700558 }
559
560 /* Restore pointer table */
561 blocks[faila] = dq;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400562 offs[faila] = dq_off;
Dan Williams0a82a622009-07-14 12:20:37 -0700563 blocks[disks-1] = q;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400564 offs[disks-1] = q_off;
Dan Williams0a82a622009-07-14 12:20:37 -0700565
566 /* calculate g^{-faila} */
567 coef = raid6_gfinv[raid6_gfexp[faila]];
568
569 srcs[0] = dq;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400570 src_offs[0] = dq_off;
Dan Williams0a82a622009-07-14 12:20:37 -0700571 srcs[1] = q;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400572 src_offs[1] = q_off;
Dan Williams0403e382009-09-08 17:42:50 -0700573 init_async_submit(submit, ASYNC_TX_FENCE|ASYNC_TX_XOR_DROP_DST, tx,
574 NULL, NULL, scribble);
Yufen Yu4f86ff52020-08-20 09:22:11 -0400575 tx = async_xor_offs(dq, dq_off, srcs, src_offs, 2, bytes, submit);
Dan Williams0a82a622009-07-14 12:20:37 -0700576
Dan Williams0403e382009-09-08 17:42:50 -0700577 init_async_submit(submit, ASYNC_TX_FENCE, tx, NULL, NULL, scribble);
Yufen Yu4f86ff52020-08-20 09:22:11 -0400578 tx = async_mult(dq, dq_off, dq, dq_off, coef, bytes, submit);
Dan Williams0a82a622009-07-14 12:20:37 -0700579
580 srcs[0] = p;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400581 src_offs[0] = p_off;
Dan Williams0a82a622009-07-14 12:20:37 -0700582 srcs[1] = dq;
Yufen Yu4f86ff52020-08-20 09:22:11 -0400583 src_offs[1] = dq_off;
Dan Williams0a82a622009-07-14 12:20:37 -0700584 init_async_submit(submit, flags | ASYNC_TX_XOR_DROP_DST, tx, cb_fn,
585 cb_param, scribble);
Yufen Yu4f86ff52020-08-20 09:22:11 -0400586 tx = async_xor_offs(p, p_off, srcs, src_offs, 2, bytes, submit);
Dan Williams0a82a622009-07-14 12:20:37 -0700587
588 return tx;
589}
590EXPORT_SYMBOL_GPL(async_raid6_datap_recov);
591
592MODULE_AUTHOR("Dan Williams <dan.j.williams@intel.com>");
593MODULE_DESCRIPTION("asynchronous RAID-6 recovery api");
594MODULE_LICENSE("GPL");