Thomas Gleixner | fd534e9 | 2019-05-23 11:14:39 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Asynchronous RAID-6 recovery calculations ASYNC_TX API. |
| 4 | * Copyright(c) 2009 Intel Corporation |
| 5 | * |
| 6 | * based on raid6recov.c: |
| 7 | * Copyright 2002 H. Peter Anvin |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 8 | */ |
| 9 | #include <linux/kernel.h> |
| 10 | #include <linux/interrupt.h> |
Paul Gortmaker | 4bb33cc | 2011-05-27 14:41:48 -0400 | [diff] [blame] | 11 | #include <linux/module.h> |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 12 | #include <linux/dma-mapping.h> |
| 13 | #include <linux/raid/pq.h> |
| 14 | #include <linux/async_tx.h> |
Dan Williams | 3bbdd49 | 2013-10-18 19:35:28 +0200 | [diff] [blame] | 15 | #include <linux/dmaengine.h> |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 16 | |
| 17 | static struct dma_async_tx_descriptor * |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 18 | async_sum_product(struct page *dest, unsigned int d_off, |
| 19 | struct page **srcs, unsigned int *src_offs, unsigned char *coef, |
| 20 | size_t len, struct async_submit_ctl *submit) |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 21 | { |
| 22 | struct dma_chan *chan = async_tx_find_channel(submit, DMA_PQ, |
| 23 | &dest, 1, srcs, 2, len); |
| 24 | struct dma_device *dma = chan ? chan->device : NULL; |
Dan Williams | 3bbdd49 | 2013-10-18 19:35:28 +0200 | [diff] [blame] | 25 | struct dmaengine_unmap_data *unmap = NULL; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 26 | const u8 *amul, *bmul; |
| 27 | u8 ax, bx; |
| 28 | u8 *a, *b, *c; |
| 29 | |
Dan Williams | 3bbdd49 | 2013-10-18 19:35:28 +0200 | [diff] [blame] | 30 | if (dma) |
NeilBrown | b02bab6 | 2016-01-07 11:02:34 +1100 | [diff] [blame] | 31 | unmap = dmaengine_get_unmap_data(dma->dev, 3, GFP_NOWAIT); |
Dan Williams | 3bbdd49 | 2013-10-18 19:35:28 +0200 | [diff] [blame] | 32 | |
| 33 | if (unmap) { |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 34 | struct device *dev = dma->dev; |
Dan Williams | 3bbdd49 | 2013-10-18 19:35:28 +0200 | [diff] [blame] | 35 | dma_addr_t pq[2]; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 36 | struct dma_async_tx_descriptor *tx; |
Bartlomiej Zolnierkiewicz | 0776ae7 | 2013-10-18 19:35:33 +0200 | [diff] [blame] | 37 | enum dma_ctrl_flags dma_flags = DMA_PREP_PQ_DISABLE_P; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 38 | |
Dan Williams | 0403e38 | 2009-09-08 17:42:50 -0700 | [diff] [blame] | 39 | if (submit->flags & ASYNC_TX_FENCE) |
| 40 | dma_flags |= DMA_PREP_FENCE; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 41 | unmap->addr[0] = dma_map_page(dev, srcs[0], src_offs[0], |
| 42 | len, DMA_TO_DEVICE); |
| 43 | unmap->addr[1] = dma_map_page(dev, srcs[1], src_offs[1], |
| 44 | len, DMA_TO_DEVICE); |
Dan Williams | 3bbdd49 | 2013-10-18 19:35:28 +0200 | [diff] [blame] | 45 | unmap->to_cnt = 2; |
| 46 | |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 47 | unmap->addr[2] = dma_map_page(dev, dest, d_off, |
| 48 | len, DMA_BIDIRECTIONAL); |
Dan Williams | 3bbdd49 | 2013-10-18 19:35:28 +0200 | [diff] [blame] | 49 | unmap->bidi_cnt = 1; |
| 50 | /* engine only looks at Q, but expects it to follow P */ |
| 51 | pq[1] = unmap->addr[2]; |
| 52 | |
| 53 | unmap->len = len; |
| 54 | tx = dma->device_prep_dma_pq(chan, pq, unmap->addr, 2, coef, |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 55 | len, dma_flags); |
| 56 | if (tx) { |
Dan Williams | 3bbdd49 | 2013-10-18 19:35:28 +0200 | [diff] [blame] | 57 | dma_set_unmap(tx, unmap); |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 58 | async_tx_submit(chan, tx, submit); |
Dan Williams | 3bbdd49 | 2013-10-18 19:35:28 +0200 | [diff] [blame] | 59 | dmaengine_unmap_put(unmap); |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 60 | return tx; |
| 61 | } |
Dan Williams | 1f6672d | 2009-09-21 10:47:40 -0700 | [diff] [blame] | 62 | |
| 63 | /* could not get a descriptor, unmap and fall through to |
| 64 | * the synchronous path |
| 65 | */ |
Dan Williams | 3bbdd49 | 2013-10-18 19:35:28 +0200 | [diff] [blame] | 66 | dmaengine_unmap_put(unmap); |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 67 | } |
| 68 | |
| 69 | /* run the operation synchronously */ |
| 70 | async_tx_quiesce(&submit->depend_tx); |
| 71 | amul = raid6_gfmul[coef[0]]; |
| 72 | bmul = raid6_gfmul[coef[1]]; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 73 | a = page_address(srcs[0]) + src_offs[0]; |
| 74 | b = page_address(srcs[1]) + src_offs[1]; |
| 75 | c = page_address(dest) + d_off; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 76 | |
| 77 | while (len--) { |
| 78 | ax = amul[*a++]; |
| 79 | bx = bmul[*b++]; |
| 80 | *c++ = ax ^ bx; |
| 81 | } |
| 82 | |
| 83 | return NULL; |
| 84 | } |
| 85 | |
| 86 | static struct dma_async_tx_descriptor * |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 87 | async_mult(struct page *dest, unsigned int d_off, struct page *src, |
| 88 | unsigned int s_off, u8 coef, size_t len, |
| 89 | struct async_submit_ctl *submit) |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 90 | { |
| 91 | struct dma_chan *chan = async_tx_find_channel(submit, DMA_PQ, |
| 92 | &dest, 1, &src, 1, len); |
| 93 | struct dma_device *dma = chan ? chan->device : NULL; |
Dan Williams | 3bbdd49 | 2013-10-18 19:35:28 +0200 | [diff] [blame] | 94 | struct dmaengine_unmap_data *unmap = NULL; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 95 | const u8 *qmul; /* Q multiplier table */ |
| 96 | u8 *d, *s; |
| 97 | |
Dan Williams | 3bbdd49 | 2013-10-18 19:35:28 +0200 | [diff] [blame] | 98 | if (dma) |
NeilBrown | b02bab6 | 2016-01-07 11:02:34 +1100 | [diff] [blame] | 99 | unmap = dmaengine_get_unmap_data(dma->dev, 3, GFP_NOWAIT); |
Dan Williams | 3bbdd49 | 2013-10-18 19:35:28 +0200 | [diff] [blame] | 100 | |
| 101 | if (unmap) { |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 102 | dma_addr_t dma_dest[2]; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 103 | struct device *dev = dma->dev; |
| 104 | struct dma_async_tx_descriptor *tx; |
Bartlomiej Zolnierkiewicz | 0776ae7 | 2013-10-18 19:35:33 +0200 | [diff] [blame] | 105 | enum dma_ctrl_flags dma_flags = DMA_PREP_PQ_DISABLE_P; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 106 | |
Dan Williams | 0403e38 | 2009-09-08 17:42:50 -0700 | [diff] [blame] | 107 | if (submit->flags & ASYNC_TX_FENCE) |
| 108 | dma_flags |= DMA_PREP_FENCE; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 109 | unmap->addr[0] = dma_map_page(dev, src, s_off, |
| 110 | len, DMA_TO_DEVICE); |
Dan Williams | 3bbdd49 | 2013-10-18 19:35:28 +0200 | [diff] [blame] | 111 | unmap->to_cnt++; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 112 | unmap->addr[1] = dma_map_page(dev, dest, d_off, |
| 113 | len, DMA_BIDIRECTIONAL); |
Dan Williams | 3bbdd49 | 2013-10-18 19:35:28 +0200 | [diff] [blame] | 114 | dma_dest[1] = unmap->addr[1]; |
| 115 | unmap->bidi_cnt++; |
| 116 | unmap->len = len; |
| 117 | |
| 118 | /* this looks funny, but the engine looks for Q at |
| 119 | * dma_dest[1] and ignores dma_dest[0] as a dest |
| 120 | * due to DMA_PREP_PQ_DISABLE_P |
| 121 | */ |
| 122 | tx = dma->device_prep_dma_pq(chan, dma_dest, unmap->addr, |
| 123 | 1, &coef, len, dma_flags); |
| 124 | |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 125 | if (tx) { |
Dan Williams | 3bbdd49 | 2013-10-18 19:35:28 +0200 | [diff] [blame] | 126 | dma_set_unmap(tx, unmap); |
| 127 | dmaengine_unmap_put(unmap); |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 128 | async_tx_submit(chan, tx, submit); |
| 129 | return tx; |
| 130 | } |
Dan Williams | 1f6672d | 2009-09-21 10:47:40 -0700 | [diff] [blame] | 131 | |
| 132 | /* could not get a descriptor, unmap and fall through to |
| 133 | * the synchronous path |
| 134 | */ |
Dan Williams | 3bbdd49 | 2013-10-18 19:35:28 +0200 | [diff] [blame] | 135 | dmaengine_unmap_put(unmap); |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 136 | } |
| 137 | |
| 138 | /* no channel available, or failed to allocate a descriptor, so |
| 139 | * perform the operation synchronously |
| 140 | */ |
| 141 | async_tx_quiesce(&submit->depend_tx); |
| 142 | qmul = raid6_gfmul[coef]; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 143 | d = page_address(dest) + d_off; |
| 144 | s = page_address(src) + s_off; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 145 | |
| 146 | while (len--) |
| 147 | *d++ = qmul[*s++]; |
| 148 | |
| 149 | return NULL; |
| 150 | } |
| 151 | |
| 152 | static struct dma_async_tx_descriptor * |
Dan Williams | da17bf4 | 2009-10-19 14:05:12 -0700 | [diff] [blame] | 153 | __2data_recov_4(int disks, size_t bytes, int faila, int failb, |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 154 | struct page **blocks, unsigned int *offs, |
| 155 | struct async_submit_ctl *submit) |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 156 | { |
| 157 | struct dma_async_tx_descriptor *tx = NULL; |
| 158 | struct page *p, *q, *a, *b; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 159 | unsigned int p_off, q_off, a_off, b_off; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 160 | struct page *srcs[2]; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 161 | unsigned int src_offs[2]; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 162 | unsigned char coef[2]; |
| 163 | enum async_tx_flags flags = submit->flags; |
| 164 | dma_async_tx_callback cb_fn = submit->cb_fn; |
| 165 | void *cb_param = submit->cb_param; |
| 166 | void *scribble = submit->scribble; |
| 167 | |
Dan Williams | da17bf4 | 2009-10-19 14:05:12 -0700 | [diff] [blame] | 168 | p = blocks[disks-2]; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 169 | p_off = offs[disks-2]; |
Dan Williams | da17bf4 | 2009-10-19 14:05:12 -0700 | [diff] [blame] | 170 | q = blocks[disks-1]; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 171 | q_off = offs[disks-1]; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 172 | |
| 173 | a = blocks[faila]; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 174 | a_off = offs[faila]; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 175 | b = blocks[failb]; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 176 | b_off = offs[failb]; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 177 | |
| 178 | /* in the 4 disk case P + Pxy == P and Q + Qxy == Q */ |
| 179 | /* Dx = A*(P+Pxy) + B*(Q+Qxy) */ |
| 180 | srcs[0] = p; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 181 | src_offs[0] = p_off; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 182 | srcs[1] = q; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 183 | src_offs[1] = q_off; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 184 | coef[0] = raid6_gfexi[failb-faila]; |
| 185 | coef[1] = raid6_gfinv[raid6_gfexp[faila]^raid6_gfexp[failb]]; |
Dan Williams | 0403e38 | 2009-09-08 17:42:50 -0700 | [diff] [blame] | 186 | init_async_submit(submit, ASYNC_TX_FENCE, tx, NULL, NULL, scribble); |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 187 | tx = async_sum_product(b, b_off, srcs, src_offs, coef, bytes, submit); |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 188 | |
| 189 | /* Dy = P+Pxy+Dx */ |
| 190 | srcs[0] = p; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 191 | src_offs[0] = p_off; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 192 | srcs[1] = b; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 193 | src_offs[1] = b_off; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 194 | init_async_submit(submit, flags | ASYNC_TX_XOR_ZERO_DST, tx, cb_fn, |
| 195 | cb_param, scribble); |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 196 | tx = async_xor_offs(a, a_off, srcs, src_offs, 2, bytes, submit); |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 197 | |
| 198 | return tx; |
| 199 | |
| 200 | } |
| 201 | |
| 202 | static struct dma_async_tx_descriptor * |
Dan Williams | da17bf4 | 2009-10-19 14:05:12 -0700 | [diff] [blame] | 203 | __2data_recov_5(int disks, size_t bytes, int faila, int failb, |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 204 | struct page **blocks, unsigned int *offs, |
| 205 | struct async_submit_ctl *submit) |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 206 | { |
| 207 | struct dma_async_tx_descriptor *tx = NULL; |
| 208 | struct page *p, *q, *g, *dp, *dq; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 209 | unsigned int p_off, q_off, g_off, dp_off, dq_off; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 210 | struct page *srcs[2]; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 211 | unsigned int src_offs[2]; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 212 | unsigned char coef[2]; |
| 213 | enum async_tx_flags flags = submit->flags; |
| 214 | dma_async_tx_callback cb_fn = submit->cb_fn; |
| 215 | void *cb_param = submit->cb_param; |
| 216 | void *scribble = submit->scribble; |
Dan Williams | da17bf4 | 2009-10-19 14:05:12 -0700 | [diff] [blame] | 217 | int good_srcs, good, i; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 218 | |
Dan Williams | da17bf4 | 2009-10-19 14:05:12 -0700 | [diff] [blame] | 219 | good_srcs = 0; |
| 220 | good = -1; |
| 221 | for (i = 0; i < disks-2; i++) { |
| 222 | if (blocks[i] == NULL) |
| 223 | continue; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 224 | if (i == faila || i == failb) |
| 225 | continue; |
Dan Williams | da17bf4 | 2009-10-19 14:05:12 -0700 | [diff] [blame] | 226 | good = i; |
| 227 | good_srcs++; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 228 | } |
Dan Williams | da17bf4 | 2009-10-19 14:05:12 -0700 | [diff] [blame] | 229 | BUG_ON(good_srcs > 1); |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 230 | |
Dan Williams | da17bf4 | 2009-10-19 14:05:12 -0700 | [diff] [blame] | 231 | p = blocks[disks-2]; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 232 | p_off = offs[disks-2]; |
Dan Williams | da17bf4 | 2009-10-19 14:05:12 -0700 | [diff] [blame] | 233 | q = blocks[disks-1]; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 234 | q_off = offs[disks-1]; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 235 | g = blocks[good]; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 236 | g_off = offs[good]; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 237 | |
| 238 | /* Compute syndrome with zero for the missing data pages |
| 239 | * Use the dead data pages as temporary storage for delta p and |
| 240 | * delta q |
| 241 | */ |
| 242 | dp = blocks[faila]; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 243 | dp_off = offs[faila]; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 244 | dq = blocks[failb]; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 245 | dq_off = offs[failb]; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 246 | |
Dan Williams | 0403e38 | 2009-09-08 17:42:50 -0700 | [diff] [blame] | 247 | init_async_submit(submit, ASYNC_TX_FENCE, tx, NULL, NULL, scribble); |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 248 | tx = async_memcpy(dp, g, dp_off, g_off, bytes, submit); |
Dan Williams | 0403e38 | 2009-09-08 17:42:50 -0700 | [diff] [blame] | 249 | init_async_submit(submit, ASYNC_TX_FENCE, tx, NULL, NULL, scribble); |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 250 | tx = async_mult(dq, dq_off, g, g_off, |
| 251 | raid6_gfexp[good], bytes, submit); |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 252 | |
| 253 | /* compute P + Pxy */ |
| 254 | srcs[0] = dp; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 255 | src_offs[0] = dp_off; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 256 | srcs[1] = p; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 257 | src_offs[1] = p_off; |
Dan Williams | 0403e38 | 2009-09-08 17:42:50 -0700 | [diff] [blame] | 258 | init_async_submit(submit, ASYNC_TX_FENCE|ASYNC_TX_XOR_DROP_DST, tx, |
| 259 | NULL, NULL, scribble); |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 260 | tx = async_xor_offs(dp, dp_off, srcs, src_offs, 2, bytes, submit); |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 261 | |
| 262 | /* compute Q + Qxy */ |
| 263 | srcs[0] = dq; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 264 | src_offs[0] = dq_off; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 265 | srcs[1] = q; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 266 | src_offs[1] = q_off; |
Dan Williams | 0403e38 | 2009-09-08 17:42:50 -0700 | [diff] [blame] | 267 | init_async_submit(submit, ASYNC_TX_FENCE|ASYNC_TX_XOR_DROP_DST, tx, |
| 268 | NULL, NULL, scribble); |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 269 | tx = async_xor_offs(dq, dq_off, srcs, src_offs, 2, bytes, submit); |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 270 | |
| 271 | /* Dx = A*(P+Pxy) + B*(Q+Qxy) */ |
| 272 | srcs[0] = dp; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 273 | src_offs[0] = dp_off; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 274 | srcs[1] = dq; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 275 | src_offs[1] = dq_off; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 276 | coef[0] = raid6_gfexi[failb-faila]; |
| 277 | coef[1] = raid6_gfinv[raid6_gfexp[faila]^raid6_gfexp[failb]]; |
Dan Williams | 0403e38 | 2009-09-08 17:42:50 -0700 | [diff] [blame] | 278 | init_async_submit(submit, ASYNC_TX_FENCE, tx, NULL, NULL, scribble); |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 279 | tx = async_sum_product(dq, dq_off, srcs, src_offs, coef, bytes, submit); |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 280 | |
| 281 | /* Dy = P+Pxy+Dx */ |
| 282 | srcs[0] = dp; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 283 | src_offs[0] = dp_off; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 284 | srcs[1] = dq; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 285 | src_offs[1] = dq_off; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 286 | init_async_submit(submit, flags | ASYNC_TX_XOR_DROP_DST, tx, cb_fn, |
| 287 | cb_param, scribble); |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 288 | tx = async_xor_offs(dp, dp_off, srcs, src_offs, 2, bytes, submit); |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 289 | |
| 290 | return tx; |
| 291 | } |
| 292 | |
| 293 | static struct dma_async_tx_descriptor * |
| 294 | __2data_recov_n(int disks, size_t bytes, int faila, int failb, |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 295 | struct page **blocks, unsigned int *offs, |
| 296 | struct async_submit_ctl *submit) |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 297 | { |
| 298 | struct dma_async_tx_descriptor *tx = NULL; |
| 299 | struct page *p, *q, *dp, *dq; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 300 | unsigned int p_off, q_off, dp_off, dq_off; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 301 | struct page *srcs[2]; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 302 | unsigned int src_offs[2]; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 303 | unsigned char coef[2]; |
| 304 | enum async_tx_flags flags = submit->flags; |
| 305 | dma_async_tx_callback cb_fn = submit->cb_fn; |
| 306 | void *cb_param = submit->cb_param; |
| 307 | void *scribble = submit->scribble; |
| 308 | |
| 309 | p = blocks[disks-2]; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 310 | p_off = offs[disks-2]; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 311 | q = blocks[disks-1]; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 312 | q_off = offs[disks-1]; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 313 | |
| 314 | /* Compute syndrome with zero for the missing data pages |
| 315 | * Use the dead data pages as temporary storage for |
| 316 | * delta p and delta q |
| 317 | */ |
| 318 | dp = blocks[faila]; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 319 | dp_off = offs[faila]; |
NeilBrown | 5dd33c9 | 2009-10-16 16:40:25 +1100 | [diff] [blame] | 320 | blocks[faila] = NULL; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 321 | blocks[disks-2] = dp; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 322 | offs[disks-2] = dp_off; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 323 | dq = blocks[failb]; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 324 | dq_off = offs[failb]; |
NeilBrown | 5dd33c9 | 2009-10-16 16:40:25 +1100 | [diff] [blame] | 325 | blocks[failb] = NULL; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 326 | blocks[disks-1] = dq; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 327 | offs[disks-1] = dq_off; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 328 | |
Dan Williams | 0403e38 | 2009-09-08 17:42:50 -0700 | [diff] [blame] | 329 | init_async_submit(submit, ASYNC_TX_FENCE, tx, NULL, NULL, scribble); |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 330 | tx = async_gen_syndrome(blocks, offs, disks, bytes, submit); |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 331 | |
| 332 | /* Restore pointer table */ |
| 333 | blocks[faila] = dp; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 334 | offs[faila] = dp_off; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 335 | blocks[failb] = dq; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 336 | offs[failb] = dq_off; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 337 | blocks[disks-2] = p; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 338 | offs[disks-2] = p_off; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 339 | blocks[disks-1] = q; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 340 | offs[disks-1] = q_off; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 341 | |
| 342 | /* compute P + Pxy */ |
| 343 | srcs[0] = dp; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 344 | src_offs[0] = dp_off; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 345 | srcs[1] = p; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 346 | src_offs[1] = p_off; |
Dan Williams | 0403e38 | 2009-09-08 17:42:50 -0700 | [diff] [blame] | 347 | init_async_submit(submit, ASYNC_TX_FENCE|ASYNC_TX_XOR_DROP_DST, tx, |
| 348 | NULL, NULL, scribble); |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 349 | tx = async_xor_offs(dp, dp_off, srcs, src_offs, 2, bytes, submit); |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 350 | |
| 351 | /* compute Q + Qxy */ |
| 352 | srcs[0] = dq; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 353 | src_offs[0] = dq_off; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 354 | srcs[1] = q; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 355 | src_offs[1] = q_off; |
Dan Williams | 0403e38 | 2009-09-08 17:42:50 -0700 | [diff] [blame] | 356 | init_async_submit(submit, ASYNC_TX_FENCE|ASYNC_TX_XOR_DROP_DST, tx, |
| 357 | NULL, NULL, scribble); |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 358 | tx = async_xor_offs(dq, dq_off, srcs, src_offs, 2, bytes, submit); |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 359 | |
| 360 | /* Dx = A*(P+Pxy) + B*(Q+Qxy) */ |
| 361 | srcs[0] = dp; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 362 | src_offs[0] = dp_off; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 363 | srcs[1] = dq; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 364 | src_offs[1] = dq_off; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 365 | coef[0] = raid6_gfexi[failb-faila]; |
| 366 | coef[1] = raid6_gfinv[raid6_gfexp[faila]^raid6_gfexp[failb]]; |
Dan Williams | 0403e38 | 2009-09-08 17:42:50 -0700 | [diff] [blame] | 367 | init_async_submit(submit, ASYNC_TX_FENCE, tx, NULL, NULL, scribble); |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 368 | tx = async_sum_product(dq, dq_off, srcs, src_offs, coef, bytes, submit); |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 369 | |
| 370 | /* Dy = P+Pxy+Dx */ |
| 371 | srcs[0] = dp; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 372 | src_offs[0] = dp_off; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 373 | srcs[1] = dq; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 374 | src_offs[1] = dq_off; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 375 | init_async_submit(submit, flags | ASYNC_TX_XOR_DROP_DST, tx, cb_fn, |
| 376 | cb_param, scribble); |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 377 | tx = async_xor_offs(dp, dp_off, srcs, src_offs, 2, bytes, submit); |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 378 | |
| 379 | return tx; |
| 380 | } |
| 381 | |
| 382 | /** |
| 383 | * async_raid6_2data_recov - asynchronously calculate two missing data blocks |
| 384 | * @disks: number of disks in the RAID-6 array |
| 385 | * @bytes: block size |
| 386 | * @faila: first failed drive index |
| 387 | * @failb: second failed drive index |
| 388 | * @blocks: array of source pointers where the last two entries are p and q |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 389 | * @offs: array of offset for pages in blocks |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 390 | * @submit: submission/completion modifiers |
| 391 | */ |
| 392 | struct dma_async_tx_descriptor * |
| 393 | async_raid6_2data_recov(int disks, size_t bytes, int faila, int failb, |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 394 | struct page **blocks, unsigned int *offs, |
| 395 | struct async_submit_ctl *submit) |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 396 | { |
Dan Williams | 5157b4a | 2010-05-04 20:41:56 -0700 | [diff] [blame] | 397 | void *scribble = submit->scribble; |
Dan Williams | da17bf4 | 2009-10-19 14:05:12 -0700 | [diff] [blame] | 398 | int non_zero_srcs, i; |
| 399 | |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 400 | BUG_ON(faila == failb); |
| 401 | if (failb < faila) |
| 402 | swap(faila, failb); |
| 403 | |
| 404 | pr_debug("%s: disks: %d len: %zu\n", __func__, disks, bytes); |
| 405 | |
Dan Williams | 5157b4a | 2010-05-04 20:41:56 -0700 | [diff] [blame] | 406 | /* if a dma resource is not available or a scribble buffer is not |
| 407 | * available punt to the synchronous path. In the 'dma not |
| 408 | * available' case be sure to use the scribble buffer to |
| 409 | * preserve the content of 'blocks' as the caller intended. |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 410 | */ |
Dan Williams | 5157b4a | 2010-05-04 20:41:56 -0700 | [diff] [blame] | 411 | if (!async_dma_find_channel(DMA_PQ) || !scribble) { |
| 412 | void **ptrs = scribble ? scribble : (void **) blocks; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 413 | |
| 414 | async_tx_quiesce(&submit->depend_tx); |
| 415 | for (i = 0; i < disks; i++) |
NeilBrown | 5dd33c9 | 2009-10-16 16:40:25 +1100 | [diff] [blame] | 416 | if (blocks[i] == NULL) |
Dan Williams | da17bf4 | 2009-10-19 14:05:12 -0700 | [diff] [blame] | 417 | ptrs[i] = (void *) raid6_empty_zero_page; |
NeilBrown | 5dd33c9 | 2009-10-16 16:40:25 +1100 | [diff] [blame] | 418 | else |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 419 | ptrs[i] = page_address(blocks[i]) + offs[i]; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 420 | |
| 421 | raid6_2data_recov(disks, bytes, faila, failb, ptrs); |
| 422 | |
| 423 | async_tx_sync_epilog(submit); |
| 424 | |
| 425 | return NULL; |
| 426 | } |
| 427 | |
Dan Williams | da17bf4 | 2009-10-19 14:05:12 -0700 | [diff] [blame] | 428 | non_zero_srcs = 0; |
| 429 | for (i = 0; i < disks-2 && non_zero_srcs < 4; i++) |
| 430 | if (blocks[i]) |
| 431 | non_zero_srcs++; |
| 432 | switch (non_zero_srcs) { |
| 433 | case 0: |
| 434 | case 1: |
| 435 | /* There must be at least 2 sources - the failed devices. */ |
| 436 | BUG(); |
| 437 | |
| 438 | case 2: |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 439 | /* dma devices do not uniformly understand a zero source pq |
| 440 | * operation (in contrast to the synchronous case), so |
Dan Williams | da17bf4 | 2009-10-19 14:05:12 -0700 | [diff] [blame] | 441 | * explicitly handle the special case of a 4 disk array with |
| 442 | * both data disks missing. |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 443 | */ |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 444 | return __2data_recov_4(disks, bytes, faila, failb, |
| 445 | blocks, offs, submit); |
Dan Williams | da17bf4 | 2009-10-19 14:05:12 -0700 | [diff] [blame] | 446 | case 3: |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 447 | /* dma devices do not uniformly understand a single |
| 448 | * source pq operation (in contrast to the synchronous |
Dan Williams | da17bf4 | 2009-10-19 14:05:12 -0700 | [diff] [blame] | 449 | * case), so explicitly handle the special case of a 5 disk |
| 450 | * array with 2 of 3 data disks missing. |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 451 | */ |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 452 | return __2data_recov_5(disks, bytes, faila, failb, |
| 453 | blocks, offs, submit); |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 454 | default: |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 455 | return __2data_recov_n(disks, bytes, faila, failb, |
| 456 | blocks, offs, submit); |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 457 | } |
| 458 | } |
| 459 | EXPORT_SYMBOL_GPL(async_raid6_2data_recov); |
| 460 | |
| 461 | /** |
| 462 | * async_raid6_datap_recov - asynchronously calculate a data and the 'p' block |
| 463 | * @disks: number of disks in the RAID-6 array |
| 464 | * @bytes: block size |
| 465 | * @faila: failed drive index |
| 466 | * @blocks: array of source pointers where the last two entries are p and q |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 467 | * @offs: array of offset for pages in blocks |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 468 | * @submit: submission/completion modifiers |
| 469 | */ |
| 470 | struct dma_async_tx_descriptor * |
| 471 | async_raid6_datap_recov(int disks, size_t bytes, int faila, |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 472 | struct page **blocks, unsigned int *offs, |
| 473 | struct async_submit_ctl *submit) |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 474 | { |
| 475 | struct dma_async_tx_descriptor *tx = NULL; |
| 476 | struct page *p, *q, *dq; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 477 | unsigned int p_off, q_off, dq_off; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 478 | u8 coef; |
| 479 | enum async_tx_flags flags = submit->flags; |
| 480 | dma_async_tx_callback cb_fn = submit->cb_fn; |
| 481 | void *cb_param = submit->cb_param; |
| 482 | void *scribble = submit->scribble; |
Dan Williams | da17bf4 | 2009-10-19 14:05:12 -0700 | [diff] [blame] | 483 | int good_srcs, good, i; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 484 | struct page *srcs[2]; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 485 | unsigned int src_offs[2]; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 486 | |
| 487 | pr_debug("%s: disks: %d len: %zu\n", __func__, disks, bytes); |
| 488 | |
Dan Williams | 5157b4a | 2010-05-04 20:41:56 -0700 | [diff] [blame] | 489 | /* if a dma resource is not available or a scribble buffer is not |
| 490 | * available punt to the synchronous path. In the 'dma not |
| 491 | * available' case be sure to use the scribble buffer to |
| 492 | * preserve the content of 'blocks' as the caller intended. |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 493 | */ |
Dan Williams | 5157b4a | 2010-05-04 20:41:56 -0700 | [diff] [blame] | 494 | if (!async_dma_find_channel(DMA_PQ) || !scribble) { |
| 495 | void **ptrs = scribble ? scribble : (void **) blocks; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 496 | |
| 497 | async_tx_quiesce(&submit->depend_tx); |
| 498 | for (i = 0; i < disks; i++) |
NeilBrown | 5dd33c9 | 2009-10-16 16:40:25 +1100 | [diff] [blame] | 499 | if (blocks[i] == NULL) |
| 500 | ptrs[i] = (void*)raid6_empty_zero_page; |
| 501 | else |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 502 | ptrs[i] = page_address(blocks[i]) + offs[i]; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 503 | |
| 504 | raid6_datap_recov(disks, bytes, faila, ptrs); |
| 505 | |
| 506 | async_tx_sync_epilog(submit); |
| 507 | |
| 508 | return NULL; |
| 509 | } |
| 510 | |
Dan Williams | da17bf4 | 2009-10-19 14:05:12 -0700 | [diff] [blame] | 511 | good_srcs = 0; |
| 512 | good = -1; |
| 513 | for (i = 0; i < disks-2; i++) { |
| 514 | if (i == faila) |
| 515 | continue; |
| 516 | if (blocks[i]) { |
| 517 | good = i; |
| 518 | good_srcs++; |
| 519 | if (good_srcs > 1) |
| 520 | break; |
| 521 | } |
| 522 | } |
| 523 | BUG_ON(good_srcs == 0); |
| 524 | |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 525 | p = blocks[disks-2]; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 526 | p_off = offs[disks-2]; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 527 | q = blocks[disks-1]; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 528 | q_off = offs[disks-1]; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 529 | |
| 530 | /* Compute syndrome with zero for the missing data page |
| 531 | * Use the dead data page as temporary storage for delta q |
| 532 | */ |
| 533 | dq = blocks[faila]; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 534 | dq_off = offs[faila]; |
NeilBrown | 5dd33c9 | 2009-10-16 16:40:25 +1100 | [diff] [blame] | 535 | blocks[faila] = NULL; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 536 | blocks[disks-1] = dq; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 537 | offs[disks-1] = dq_off; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 538 | |
Dan Williams | da17bf4 | 2009-10-19 14:05:12 -0700 | [diff] [blame] | 539 | /* in the 4-disk case we only need to perform a single source |
| 540 | * multiplication with the one good data block. |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 541 | */ |
Dan Williams | da17bf4 | 2009-10-19 14:05:12 -0700 | [diff] [blame] | 542 | if (good_srcs == 1) { |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 543 | struct page *g = blocks[good]; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 544 | unsigned int g_off = offs[good]; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 545 | |
Dan Williams | 0403e38 | 2009-09-08 17:42:50 -0700 | [diff] [blame] | 546 | init_async_submit(submit, ASYNC_TX_FENCE, tx, NULL, NULL, |
| 547 | scribble); |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 548 | tx = async_memcpy(p, g, p_off, g_off, bytes, submit); |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 549 | |
Dan Williams | 0403e38 | 2009-09-08 17:42:50 -0700 | [diff] [blame] | 550 | init_async_submit(submit, ASYNC_TX_FENCE, tx, NULL, NULL, |
| 551 | scribble); |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 552 | tx = async_mult(dq, dq_off, g, g_off, |
| 553 | raid6_gfexp[good], bytes, submit); |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 554 | } else { |
Dan Williams | 0403e38 | 2009-09-08 17:42:50 -0700 | [diff] [blame] | 555 | init_async_submit(submit, ASYNC_TX_FENCE, tx, NULL, NULL, |
| 556 | scribble); |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 557 | tx = async_gen_syndrome(blocks, offs, disks, bytes, submit); |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 558 | } |
| 559 | |
| 560 | /* Restore pointer table */ |
| 561 | blocks[faila] = dq; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 562 | offs[faila] = dq_off; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 563 | blocks[disks-1] = q; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 564 | offs[disks-1] = q_off; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 565 | |
| 566 | /* calculate g^{-faila} */ |
| 567 | coef = raid6_gfinv[raid6_gfexp[faila]]; |
| 568 | |
| 569 | srcs[0] = dq; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 570 | src_offs[0] = dq_off; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 571 | srcs[1] = q; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 572 | src_offs[1] = q_off; |
Dan Williams | 0403e38 | 2009-09-08 17:42:50 -0700 | [diff] [blame] | 573 | init_async_submit(submit, ASYNC_TX_FENCE|ASYNC_TX_XOR_DROP_DST, tx, |
| 574 | NULL, NULL, scribble); |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 575 | tx = async_xor_offs(dq, dq_off, srcs, src_offs, 2, bytes, submit); |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 576 | |
Dan Williams | 0403e38 | 2009-09-08 17:42:50 -0700 | [diff] [blame] | 577 | init_async_submit(submit, ASYNC_TX_FENCE, tx, NULL, NULL, scribble); |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 578 | tx = async_mult(dq, dq_off, dq, dq_off, coef, bytes, submit); |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 579 | |
| 580 | srcs[0] = p; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 581 | src_offs[0] = p_off; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 582 | srcs[1] = dq; |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 583 | src_offs[1] = dq_off; |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 584 | init_async_submit(submit, flags | ASYNC_TX_XOR_DROP_DST, tx, cb_fn, |
| 585 | cb_param, scribble); |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 586 | tx = async_xor_offs(p, p_off, srcs, src_offs, 2, bytes, submit); |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 587 | |
| 588 | return tx; |
| 589 | } |
| 590 | EXPORT_SYMBOL_GPL(async_raid6_datap_recov); |
| 591 | |
| 592 | MODULE_AUTHOR("Dan Williams <dan.j.williams@intel.com>"); |
| 593 | MODULE_DESCRIPTION("asynchronous RAID-6 recovery api"); |
| 594 | MODULE_LICENSE("GPL"); |