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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / a98ec93d7e378db21a6cdbc6d55feaba9fb4b999 / . / sound / soc / codecs / rt5682.c
blob: baad177908abf90a30f505159fd1288f62c36ea8 [file] [log] [blame]
Bard Liao0ddce712018-06-07 16:37:38 +0800[diff] [blame]1/*
2 * rt5682.c -- RT5682 ALSA SoC audio component driver
3 *
4 * Copyright 2018 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <linux/spi/spi.h>
20#include <linux/acpi.h>
21#include <linux/gpio.h>
22#include <linux/of_gpio.h>
23#include <linux/regulator/consumer.h>
24#include <linux/mutex.h>
25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/jack.h>
29#include <sound/soc.h>
30#include <sound/soc-dapm.h>
31#include <sound/initval.h>
32#include <sound/tlv.h>
33#include <sound/rt5682.h>
34
35#include "rl6231.h"
36#include "rt5682.h"
37
38#define RT5682_NUM_SUPPLIES 3
39
40static const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = {
41 "AVDD",
42 "MICVDD",
43 "VBAT",
44};
45
46struct rt5682_priv {
47 struct snd_soc_component *component;
48 struct rt5682_platform_data pdata;
49 struct regmap *regmap;
50 struct snd_soc_jack *hs_jack;
51 struct regulator_bulk_data supplies[RT5682_NUM_SUPPLIES];
52 struct delayed_work jack_detect_work;
53 struct delayed_work jd_check_work;
54 struct mutex calibrate_mutex;
55
56 int sysclk;
57 int sysclk_src;
58 int lrck[RT5682_AIFS];
59 int bclk[RT5682_AIFS];
60 int master[RT5682_AIFS];
61
62 int pll_src;
63 int pll_in;
64 int pll_out;
65
66 int jack_type;
67};
68
69static const struct reg_sequence patch_list[] = {
70 {0x01c1, 0x1000},
71};
72
73static const struct reg_default rt5682_reg[] = {
74 {0x0002, 0x8080},
75 {0x0003, 0x8000},
76 {0x0005, 0x0000},
77 {0x0006, 0x0000},
78 {0x0008, 0x800f},
79 {0x000b, 0x0000},
80 {0x0010, 0x4040},
81 {0x0011, 0x0000},
82 {0x0012, 0x1404},
83 {0x0013, 0x1000},
84 {0x0014, 0xa00a},
85 {0x0015, 0x0404},
86 {0x0016, 0x0404},
87 {0x0019, 0xafaf},
88 {0x001c, 0x2f2f},
89 {0x001f, 0x0000},
90 {0x0022, 0x5757},
91 {0x0023, 0x0039},
92 {0x0024, 0x000b},
93 {0x0026, 0xc0c4},
94 {0x0029, 0x8080},
95 {0x002a, 0xa0a0},
96 {0x002b, 0x0300},
97 {0x0030, 0x0000},
98 {0x003c, 0x0080},
99 {0x0044, 0x0c0c},
100 {0x0049, 0x0000},
101 {0x0061, 0x0000},
102 {0x0062, 0x0000},
103 {0x0063, 0x003f},
104 {0x0064, 0x0000},
105 {0x0065, 0x0000},
106 {0x0066, 0x0030},
107 {0x0067, 0x0000},
108 {0x006b, 0x0000},
109 {0x006c, 0x0000},
110 {0x006d, 0x2200},
111 {0x006e, 0x0a10},
112 {0x0070, 0x8000},
113 {0x0071, 0x8000},
114 {0x0073, 0x0000},
115 {0x0074, 0x0000},
116 {0x0075, 0x0002},
117 {0x0076, 0x0001},
118 {0x0079, 0x0000},
119 {0x007a, 0x0000},
120 {0x007b, 0x0000},
121 {0x007c, 0x0100},
122 {0x007e, 0x0000},
123 {0x0080, 0x0000},
124 {0x0081, 0x0000},
125 {0x0082, 0x0000},
126 {0x0083, 0x0000},
127 {0x0084, 0x0000},
128 {0x0085, 0x0000},
129 {0x0086, 0x0005},
130 {0x0087, 0x0000},
131 {0x0088, 0x0000},
132 {0x008c, 0x0003},
133 {0x008d, 0x0000},
134 {0x008e, 0x0060},
135 {0x008f, 0x1000},
136 {0x0091, 0x0c26},
137 {0x0092, 0x0073},
138 {0x0093, 0x0000},
139 {0x0094, 0x0080},
140 {0x0098, 0x0000},
141 {0x009a, 0x0000},
142 {0x009b, 0x0000},
143 {0x009c, 0x0000},
144 {0x009d, 0x0000},
145 {0x009e, 0x100c},
146 {0x009f, 0x0000},
147 {0x00a0, 0x0000},
148 {0x00a3, 0x0002},
149 {0x00a4, 0x0001},
150 {0x00ae, 0x2040},
151 {0x00af, 0x0000},
152 {0x00b6, 0x0000},
153 {0x00b7, 0x0000},
154 {0x00b8, 0x0000},
155 {0x00b9, 0x0002},
156 {0x00be, 0x0000},
157 {0x00c0, 0x0160},
158 {0x00c1, 0x82a0},
159 {0x00c2, 0x0000},
160 {0x00d0, 0x0000},
161 {0x00d1, 0x2244},
162 {0x00d2, 0x3300},
163 {0x00d3, 0x2200},
164 {0x00d4, 0x0000},
165 {0x00d9, 0x0009},
166 {0x00da, 0x0000},
167 {0x00db, 0x0000},
168 {0x00dc, 0x00c0},
169 {0x00dd, 0x2220},
170 {0x00de, 0x3131},
171 {0x00df, 0x3131},
172 {0x00e0, 0x3131},
173 {0x00e2, 0x0000},
174 {0x00e3, 0x4000},
175 {0x00e4, 0x0aa0},
176 {0x00e5, 0x3131},
177 {0x00e6, 0x3131},
178 {0x00e7, 0x3131},
179 {0x00e8, 0x3131},
180 {0x00ea, 0xb320},
181 {0x00eb, 0x0000},
182 {0x00f0, 0x0000},
183 {0x00f1, 0x00d0},
184 {0x00f2, 0x00d0},
185 {0x00f6, 0x0000},
186 {0x00fa, 0x0000},
187 {0x00fb, 0x0000},
188 {0x00fc, 0x0000},
189 {0x00fd, 0x0000},
190 {0x00fe, 0x10ec},
191 {0x00ff, 0x6530},
192 {0x0100, 0xa0a0},
193 {0x010b, 0x0000},
194 {0x010c, 0xae00},
195 {0x010d, 0xaaa0},
196 {0x010e, 0x8aa2},
197 {0x010f, 0x02a2},
198 {0x0110, 0xc000},
199 {0x0111, 0x04a2},
200 {0x0112, 0x2800},
201 {0x0113, 0x0000},
202 {0x0117, 0x0100},
203 {0x0125, 0x0410},
204 {0x0132, 0x6026},
205 {0x0136, 0x5555},
206 {0x0138, 0x3700},
207 {0x013a, 0x2000},
208 {0x013b, 0x2000},
209 {0x013c, 0x2005},
210 {0x013f, 0x0000},
211 {0x0142, 0x0000},
212 {0x0145, 0x0002},
213 {0x0146, 0x0000},
214 {0x0147, 0x0000},
215 {0x0148, 0x0000},
216 {0x0149, 0x0000},
217 {0x0150, 0x79a1},
218 {0x0151, 0x0000},
219 {0x0160, 0x4ec0},
220 {0x0161, 0x0080},
221 {0x0162, 0x0200},
222 {0x0163, 0x0800},
223 {0x0164, 0x0000},
224 {0x0165, 0x0000},
225 {0x0166, 0x0000},
226 {0x0167, 0x000f},
227 {0x0168, 0x000f},
228 {0x0169, 0x0021},
229 {0x0190, 0x413d},
230 {0x0194, 0x0000},
231 {0x0195, 0x0000},
232 {0x0197, 0x0022},
233 {0x0198, 0x0000},
234 {0x0199, 0x0000},
235 {0x01af, 0x0000},
236 {0x01b0, 0x0400},
237 {0x01b1, 0x0000},
238 {0x01b2, 0x0000},
239 {0x01b3, 0x0000},
240 {0x01b4, 0x0000},
241 {0x01b5, 0x0000},
242 {0x01b6, 0x01c3},
243 {0x01b7, 0x02a0},
244 {0x01b8, 0x03e9},
245 {0x01b9, 0x1389},
246 {0x01ba, 0xc351},
247 {0x01bb, 0x0009},
248 {0x01bc, 0x0018},
249 {0x01bd, 0x002a},
250 {0x01be, 0x004c},
251 {0x01bf, 0x0097},
252 {0x01c0, 0x433d},
253 {0x01c2, 0x0000},
254 {0x01c3, 0x0000},
255 {0x01c4, 0x0000},
256 {0x01c5, 0x0000},
257 {0x01c6, 0x0000},
258 {0x01c7, 0x0000},
259 {0x01c8, 0x40af},
260 {0x01c9, 0x0702},
261 {0x01ca, 0x0000},
262 {0x01cb, 0x0000},
263 {0x01cc, 0x5757},
264 {0x01cd, 0x5757},
265 {0x01ce, 0x5757},
266 {0x01cf, 0x5757},
267 {0x01d0, 0x5757},
268 {0x01d1, 0x5757},
269 {0x01d2, 0x5757},
270 {0x01d3, 0x5757},
271 {0x01d4, 0x5757},
272 {0x01d5, 0x5757},
273 {0x01d6, 0x0000},
274 {0x01d7, 0x0008},
275 {0x01d8, 0x0029},
276 {0x01d9, 0x3333},
277 {0x01da, 0x0000},
278 {0x01db, 0x0004},
279 {0x01dc, 0x0000},
280 {0x01de, 0x7c00},
281 {0x01df, 0x0320},
282 {0x01e0, 0x06a1},
283 {0x01e1, 0x0000},
284 {0x01e2, 0x0000},
285 {0x01e3, 0x0000},
286 {0x01e4, 0x0000},
287 {0x01e6, 0x0001},
288 {0x01e7, 0x0000},
289 {0x01e8, 0x0000},
290 {0x01ea, 0x0000},
291 {0x01eb, 0x0000},
292 {0x01ec, 0x0000},
293 {0x01ed, 0x0000},
294 {0x01ee, 0x0000},
295 {0x01ef, 0x0000},
296 {0x01f0, 0x0000},
297 {0x01f1, 0x0000},
298 {0x01f2, 0x0000},
299 {0x01f3, 0x0000},
300 {0x01f4, 0x0000},
301 {0x0210, 0x6297},
302 {0x0211, 0xa005},
303 {0x0212, 0x824c},
304 {0x0213, 0xf7ff},
305 {0x0214, 0xf24c},
306 {0x0215, 0x0102},
307 {0x0216, 0x00a3},
308 {0x0217, 0x0048},
309 {0x0218, 0xa2c0},
310 {0x0219, 0x0400},
311 {0x021a, 0x00c8},
312 {0x021b, 0x00c0},
313 {0x021c, 0x0000},
314 {0x0250, 0x4500},
315 {0x0251, 0x40b3},
316 {0x0252, 0x0000},
317 {0x0253, 0x0000},
318 {0x0254, 0x0000},
319 {0x0255, 0x0000},
320 {0x0256, 0x0000},
321 {0x0257, 0x0000},
322 {0x0258, 0x0000},
323 {0x0259, 0x0000},
324 {0x025a, 0x0005},
325 {0x0270, 0x0000},
326 {0x02ff, 0x0110},
327 {0x0300, 0x001f},
328 {0x0301, 0x032c},
329 {0x0302, 0x5f21},
330 {0x0303, 0x4000},
331 {0x0304, 0x4000},
332 {0x0305, 0x06d5},
333 {0x0306, 0x8000},
334 {0x0307, 0x0700},
335 {0x0310, 0x4560},
336 {0x0311, 0xa4a8},
337 {0x0312, 0x7418},
338 {0x0313, 0x0000},
339 {0x0314, 0x0006},
340 {0x0315, 0xffff},
341 {0x0316, 0xc400},
342 {0x0317, 0x0000},
343 {0x03c0, 0x7e00},
344 {0x03c1, 0x8000},
345 {0x03c2, 0x8000},
346 {0x03c3, 0x8000},
347 {0x03c4, 0x8000},
348 {0x03c5, 0x8000},
349 {0x03c6, 0x8000},
350 {0x03c7, 0x8000},
351 {0x03c8, 0x8000},
352 {0x03c9, 0x8000},
353 {0x03ca, 0x8000},
354 {0x03cb, 0x8000},
355 {0x03cc, 0x8000},
356 {0x03d0, 0x0000},
357 {0x03d1, 0x0000},
358 {0x03d2, 0x0000},
359 {0x03d3, 0x0000},
360 {0x03d4, 0x2000},
361 {0x03d5, 0x2000},
362 {0x03d6, 0x0000},
363 {0x03d7, 0x0000},
364 {0x03d8, 0x2000},
365 {0x03d9, 0x2000},
366 {0x03da, 0x2000},
367 {0x03db, 0x2000},
368 {0x03dc, 0x0000},
369 {0x03dd, 0x0000},
370 {0x03de, 0x0000},
371 {0x03df, 0x2000},
372 {0x03e0, 0x0000},
373 {0x03e1, 0x0000},
374 {0x03e2, 0x0000},
375 {0x03e3, 0x0000},
376 {0x03e4, 0x0000},
377 {0x03e5, 0x0000},
378 {0x03e6, 0x0000},
379 {0x03e7, 0x0000},
380 {0x03e8, 0x0000},
381 {0x03e9, 0x0000},
382 {0x03ea, 0x0000},
383 {0x03eb, 0x0000},
384 {0x03ec, 0x0000},
385 {0x03ed, 0x0000},
386 {0x03ee, 0x0000},
387 {0x03ef, 0x0000},
388 {0x03f0, 0x0800},
389 {0x03f1, 0x0800},
390 {0x03f2, 0x0800},
391 {0x03f3, 0x0800},
392};
393
394static bool rt5682_volatile_register(struct device *dev, unsigned int reg)
395{
396 switch (reg) {
397 case RT5682_RESET:
398 case RT5682_CBJ_CTRL_2:
399 case RT5682_INT_ST_1:
400 case RT5682_4BTN_IL_CMD_1:
401 case RT5682_AJD1_CTRL:
402 case RT5682_HP_CALIB_CTRL_1:
403 case RT5682_DEVICE_ID:
404 case RT5682_I2C_MODE:
405 case RT5682_HP_CALIB_CTRL_10:
406 case RT5682_EFUSE_CTRL_2:
407 case RT5682_JD_TOP_VC_VTRL:
408 case RT5682_HP_IMP_SENS_CTRL_19:
409 case RT5682_IL_CMD_1:
410 case RT5682_SAR_IL_CMD_2:
411 case RT5682_SAR_IL_CMD_4:
412 case RT5682_SAR_IL_CMD_10:
413 case RT5682_SAR_IL_CMD_11:
414 case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11:
415 case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11:
416 return true;
417 default:
418 return false;
419 }
420}
421
422static bool rt5682_readable_register(struct device *dev, unsigned int reg)
423{
424 switch (reg) {
425 case RT5682_RESET:
426 case RT5682_VERSION_ID:
427 case RT5682_VENDOR_ID:
428 case RT5682_DEVICE_ID:
429 case RT5682_HP_CTRL_1:
430 case RT5682_HP_CTRL_2:
431 case RT5682_HPL_GAIN:
432 case RT5682_HPR_GAIN:
433 case RT5682_I2C_CTRL:
434 case RT5682_CBJ_BST_CTRL:
435 case RT5682_CBJ_CTRL_1:
436 case RT5682_CBJ_CTRL_2:
437 case RT5682_CBJ_CTRL_3:
438 case RT5682_CBJ_CTRL_4:
439 case RT5682_CBJ_CTRL_5:
440 case RT5682_CBJ_CTRL_6:
441 case RT5682_CBJ_CTRL_7:
442 case RT5682_DAC1_DIG_VOL:
443 case RT5682_STO1_ADC_DIG_VOL:
444 case RT5682_STO1_ADC_BOOST:
445 case RT5682_HP_IMP_GAIN_1:
446 case RT5682_HP_IMP_GAIN_2:
447 case RT5682_SIDETONE_CTRL:
448 case RT5682_STO1_ADC_MIXER:
449 case RT5682_AD_DA_MIXER:
450 case RT5682_STO1_DAC_MIXER:
451 case RT5682_A_DAC1_MUX:
452 case RT5682_DIG_INF2_DATA:
453 case RT5682_REC_MIXER:
454 case RT5682_CAL_REC:
455 case RT5682_ALC_BACK_GAIN:
456 case RT5682_PWR_DIG_1:
457 case RT5682_PWR_DIG_2:
458 case RT5682_PWR_ANLG_1:
459 case RT5682_PWR_ANLG_2:
460 case RT5682_PWR_ANLG_3:
461 case RT5682_PWR_MIXER:
462 case RT5682_PWR_VOL:
463 case RT5682_CLK_DET:
464 case RT5682_RESET_LPF_CTRL:
465 case RT5682_RESET_HPF_CTRL:
466 case RT5682_DMIC_CTRL_1:
467 case RT5682_I2S1_SDP:
468 case RT5682_I2S2_SDP:
469 case RT5682_ADDA_CLK_1:
470 case RT5682_ADDA_CLK_2:
471 case RT5682_I2S1_F_DIV_CTRL_1:
472 case RT5682_I2S1_F_DIV_CTRL_2:
473 case RT5682_TDM_CTRL:
474 case RT5682_TDM_ADDA_CTRL_1:
475 case RT5682_TDM_ADDA_CTRL_2:
476 case RT5682_DATA_SEL_CTRL_1:
477 case RT5682_TDM_TCON_CTRL:
478 case RT5682_GLB_CLK:
479 case RT5682_PLL_CTRL_1:
480 case RT5682_PLL_CTRL_2:
481 case RT5682_PLL_TRACK_1:
482 case RT5682_PLL_TRACK_2:
483 case RT5682_PLL_TRACK_3:
484 case RT5682_PLL_TRACK_4:
485 case RT5682_PLL_TRACK_5:
486 case RT5682_PLL_TRACK_6:
487 case RT5682_PLL_TRACK_11:
488 case RT5682_SDW_REF_CLK:
489 case RT5682_DEPOP_1:
490 case RT5682_DEPOP_2:
491 case RT5682_HP_CHARGE_PUMP_1:
492 case RT5682_HP_CHARGE_PUMP_2:
493 case RT5682_MICBIAS_1:
494 case RT5682_MICBIAS_2:
495 case RT5682_PLL_TRACK_12:
496 case RT5682_PLL_TRACK_14:
497 case RT5682_PLL2_CTRL_1:
498 case RT5682_PLL2_CTRL_2:
499 case RT5682_PLL2_CTRL_3:
500 case RT5682_PLL2_CTRL_4:
501 case RT5682_RC_CLK_CTRL:
502 case RT5682_I2S_M_CLK_CTRL_1:
503 case RT5682_I2S2_F_DIV_CTRL_1:
504 case RT5682_I2S2_F_DIV_CTRL_2:
505 case RT5682_EQ_CTRL_1:
506 case RT5682_EQ_CTRL_2:
507 case RT5682_IRQ_CTRL_1:
508 case RT5682_IRQ_CTRL_2:
509 case RT5682_IRQ_CTRL_3:
510 case RT5682_IRQ_CTRL_4:
511 case RT5682_INT_ST_1:
512 case RT5682_GPIO_CTRL_1:
513 case RT5682_GPIO_CTRL_2:
514 case RT5682_GPIO_CTRL_3:
515 case RT5682_HP_AMP_DET_CTRL_1:
516 case RT5682_HP_AMP_DET_CTRL_2:
517 case RT5682_MID_HP_AMP_DET:
518 case RT5682_LOW_HP_AMP_DET:
519 case RT5682_DELAY_BUF_CTRL:
520 case RT5682_SV_ZCD_1:
521 case RT5682_SV_ZCD_2:
522 case RT5682_IL_CMD_1:
523 case RT5682_IL_CMD_2:
524 case RT5682_IL_CMD_3:
525 case RT5682_IL_CMD_4:
526 case RT5682_IL_CMD_5:
527 case RT5682_IL_CMD_6:
528 case RT5682_4BTN_IL_CMD_1:
529 case RT5682_4BTN_IL_CMD_2:
530 case RT5682_4BTN_IL_CMD_3:
531 case RT5682_4BTN_IL_CMD_4:
532 case RT5682_4BTN_IL_CMD_5:
533 case RT5682_4BTN_IL_CMD_6:
534 case RT5682_4BTN_IL_CMD_7:
535 case RT5682_ADC_STO1_HP_CTRL_1:
536 case RT5682_ADC_STO1_HP_CTRL_2:
537 case RT5682_AJD1_CTRL:
538 case RT5682_JD1_THD:
539 case RT5682_JD2_THD:
540 case RT5682_JD_CTRL_1:
541 case RT5682_DUMMY_1:
542 case RT5682_DUMMY_2:
543 case RT5682_DUMMY_3:
544 case RT5682_DAC_ADC_DIG_VOL1:
545 case RT5682_BIAS_CUR_CTRL_2:
546 case RT5682_BIAS_CUR_CTRL_3:
547 case RT5682_BIAS_CUR_CTRL_4:
548 case RT5682_BIAS_CUR_CTRL_5:
549 case RT5682_BIAS_CUR_CTRL_6:
550 case RT5682_BIAS_CUR_CTRL_7:
551 case RT5682_BIAS_CUR_CTRL_8:
552 case RT5682_BIAS_CUR_CTRL_9:
553 case RT5682_BIAS_CUR_CTRL_10:
554 case RT5682_VREF_REC_OP_FB_CAP_CTRL:
555 case RT5682_CHARGE_PUMP_1:
556 case RT5682_DIG_IN_CTRL_1:
557 case RT5682_PAD_DRIVING_CTRL:
558 case RT5682_SOFT_RAMP_DEPOP:
559 case RT5682_CHOP_DAC:
560 case RT5682_CHOP_ADC:
561 case RT5682_CALIB_ADC_CTRL:
562 case RT5682_VOL_TEST:
563 case RT5682_SPKVDD_DET_STA:
564 case RT5682_TEST_MODE_CTRL_1:
565 case RT5682_TEST_MODE_CTRL_2:
566 case RT5682_TEST_MODE_CTRL_3:
567 case RT5682_TEST_MODE_CTRL_4:
568 case RT5682_TEST_MODE_CTRL_5:
569 case RT5682_PLL1_INTERNAL:
570 case RT5682_PLL2_INTERNAL:
571 case RT5682_STO_NG2_CTRL_1:
572 case RT5682_STO_NG2_CTRL_2:
573 case RT5682_STO_NG2_CTRL_3:
574 case RT5682_STO_NG2_CTRL_4:
575 case RT5682_STO_NG2_CTRL_5:
576 case RT5682_STO_NG2_CTRL_6:
577 case RT5682_STO_NG2_CTRL_7:
578 case RT5682_STO_NG2_CTRL_8:
579 case RT5682_STO_NG2_CTRL_9:
580 case RT5682_STO_NG2_CTRL_10:
581 case RT5682_STO1_DAC_SIL_DET:
582 case RT5682_SIL_PSV_CTRL1:
583 case RT5682_SIL_PSV_CTRL2:
584 case RT5682_SIL_PSV_CTRL3:
585 case RT5682_SIL_PSV_CTRL4:
586 case RT5682_SIL_PSV_CTRL5:
587 case RT5682_HP_IMP_SENS_CTRL_01:
588 case RT5682_HP_IMP_SENS_CTRL_02:
589 case RT5682_HP_IMP_SENS_CTRL_03:
590 case RT5682_HP_IMP_SENS_CTRL_04:
591 case RT5682_HP_IMP_SENS_CTRL_05:
592 case RT5682_HP_IMP_SENS_CTRL_06:
593 case RT5682_HP_IMP_SENS_CTRL_07:
594 case RT5682_HP_IMP_SENS_CTRL_08:
595 case RT5682_HP_IMP_SENS_CTRL_09:
596 case RT5682_HP_IMP_SENS_CTRL_10:
597 case RT5682_HP_IMP_SENS_CTRL_11:
598 case RT5682_HP_IMP_SENS_CTRL_12:
599 case RT5682_HP_IMP_SENS_CTRL_13:
600 case RT5682_HP_IMP_SENS_CTRL_14:
601 case RT5682_HP_IMP_SENS_CTRL_15:
602 case RT5682_HP_IMP_SENS_CTRL_16:
603 case RT5682_HP_IMP_SENS_CTRL_17:
604 case RT5682_HP_IMP_SENS_CTRL_18:
605 case RT5682_HP_IMP_SENS_CTRL_19:
606 case RT5682_HP_IMP_SENS_CTRL_20:
607 case RT5682_HP_IMP_SENS_CTRL_21:
608 case RT5682_HP_IMP_SENS_CTRL_22:
609 case RT5682_HP_IMP_SENS_CTRL_23:
610 case RT5682_HP_IMP_SENS_CTRL_24:
611 case RT5682_HP_IMP_SENS_CTRL_25:
612 case RT5682_HP_IMP_SENS_CTRL_26:
613 case RT5682_HP_IMP_SENS_CTRL_27:
614 case RT5682_HP_IMP_SENS_CTRL_28:
615 case RT5682_HP_IMP_SENS_CTRL_29:
616 case RT5682_HP_IMP_SENS_CTRL_30:
617 case RT5682_HP_IMP_SENS_CTRL_31:
618 case RT5682_HP_IMP_SENS_CTRL_32:
619 case RT5682_HP_IMP_SENS_CTRL_33:
620 case RT5682_HP_IMP_SENS_CTRL_34:
621 case RT5682_HP_IMP_SENS_CTRL_35:
622 case RT5682_HP_IMP_SENS_CTRL_36:
623 case RT5682_HP_IMP_SENS_CTRL_37:
624 case RT5682_HP_IMP_SENS_CTRL_38:
625 case RT5682_HP_IMP_SENS_CTRL_39:
626 case RT5682_HP_IMP_SENS_CTRL_40:
627 case RT5682_HP_IMP_SENS_CTRL_41:
628 case RT5682_HP_IMP_SENS_CTRL_42:
629 case RT5682_HP_IMP_SENS_CTRL_43:
630 case RT5682_HP_LOGIC_CTRL_1:
631 case RT5682_HP_LOGIC_CTRL_2:
632 case RT5682_HP_LOGIC_CTRL_3:
633 case RT5682_HP_CALIB_CTRL_1:
634 case RT5682_HP_CALIB_CTRL_2:
635 case RT5682_HP_CALIB_CTRL_3:
636 case RT5682_HP_CALIB_CTRL_4:
637 case RT5682_HP_CALIB_CTRL_5:
638 case RT5682_HP_CALIB_CTRL_6:
639 case RT5682_HP_CALIB_CTRL_7:
640 case RT5682_HP_CALIB_CTRL_9:
641 case RT5682_HP_CALIB_CTRL_10:
642 case RT5682_HP_CALIB_CTRL_11:
643 case RT5682_HP_CALIB_STA_1:
644 case RT5682_HP_CALIB_STA_2:
645 case RT5682_HP_CALIB_STA_3:
646 case RT5682_HP_CALIB_STA_4:
647 case RT5682_HP_CALIB_STA_5:
648 case RT5682_HP_CALIB_STA_6:
649 case RT5682_HP_CALIB_STA_7:
650 case RT5682_HP_CALIB_STA_8:
651 case RT5682_HP_CALIB_STA_9:
652 case RT5682_HP_CALIB_STA_10:
653 case RT5682_HP_CALIB_STA_11:
654 case RT5682_SAR_IL_CMD_1:
655 case RT5682_SAR_IL_CMD_2:
656 case RT5682_SAR_IL_CMD_3:
657 case RT5682_SAR_IL_CMD_4:
658 case RT5682_SAR_IL_CMD_5:
659 case RT5682_SAR_IL_CMD_6:
660 case RT5682_SAR_IL_CMD_7:
661 case RT5682_SAR_IL_CMD_8:
662 case RT5682_SAR_IL_CMD_9:
663 case RT5682_SAR_IL_CMD_10:
664 case RT5682_SAR_IL_CMD_11:
665 case RT5682_SAR_IL_CMD_12:
666 case RT5682_SAR_IL_CMD_13:
667 case RT5682_EFUSE_CTRL_1:
668 case RT5682_EFUSE_CTRL_2:
669 case RT5682_EFUSE_CTRL_3:
670 case RT5682_EFUSE_CTRL_4:
671 case RT5682_EFUSE_CTRL_5:
672 case RT5682_EFUSE_CTRL_6:
673 case RT5682_EFUSE_CTRL_7:
674 case RT5682_EFUSE_CTRL_8:
675 case RT5682_EFUSE_CTRL_9:
676 case RT5682_EFUSE_CTRL_10:
677 case RT5682_EFUSE_CTRL_11:
678 case RT5682_JD_TOP_VC_VTRL:
679 case RT5682_DRC1_CTRL_0:
680 case RT5682_DRC1_CTRL_1:
681 case RT5682_DRC1_CTRL_2:
682 case RT5682_DRC1_CTRL_3:
683 case RT5682_DRC1_CTRL_4:
684 case RT5682_DRC1_CTRL_5:
685 case RT5682_DRC1_CTRL_6:
686 case RT5682_DRC1_HARD_LMT_CTRL_1:
687 case RT5682_DRC1_HARD_LMT_CTRL_2:
688 case RT5682_DRC1_PRIV_1:
689 case RT5682_DRC1_PRIV_2:
690 case RT5682_DRC1_PRIV_3:
691 case RT5682_DRC1_PRIV_4:
692 case RT5682_DRC1_PRIV_5:
693 case RT5682_DRC1_PRIV_6:
694 case RT5682_DRC1_PRIV_7:
695 case RT5682_DRC1_PRIV_8:
696 case RT5682_EQ_AUTO_RCV_CTRL1:
697 case RT5682_EQ_AUTO_RCV_CTRL2:
698 case RT5682_EQ_AUTO_RCV_CTRL3:
699 case RT5682_EQ_AUTO_RCV_CTRL4:
700 case RT5682_EQ_AUTO_RCV_CTRL5:
701 case RT5682_EQ_AUTO_RCV_CTRL6:
702 case RT5682_EQ_AUTO_RCV_CTRL7:
703 case RT5682_EQ_AUTO_RCV_CTRL8:
704 case RT5682_EQ_AUTO_RCV_CTRL9:
705 case RT5682_EQ_AUTO_RCV_CTRL10:
706 case RT5682_EQ_AUTO_RCV_CTRL11:
707 case RT5682_EQ_AUTO_RCV_CTRL12:
708 case RT5682_EQ_AUTO_RCV_CTRL13:
709 case RT5682_ADC_L_EQ_LPF1_A1:
710 case RT5682_R_EQ_LPF1_A1:
711 case RT5682_L_EQ_LPF1_H0:
712 case RT5682_R_EQ_LPF1_H0:
713 case RT5682_L_EQ_BPF1_A1:
714 case RT5682_R_EQ_BPF1_A1:
715 case RT5682_L_EQ_BPF1_A2:
716 case RT5682_R_EQ_BPF1_A2:
717 case RT5682_L_EQ_BPF1_H0:
718 case RT5682_R_EQ_BPF1_H0:
719 case RT5682_L_EQ_BPF2_A1:
720 case RT5682_R_EQ_BPF2_A1:
721 case RT5682_L_EQ_BPF2_A2:
722 case RT5682_R_EQ_BPF2_A2:
723 case RT5682_L_EQ_BPF2_H0:
724 case RT5682_R_EQ_BPF2_H0:
725 case RT5682_L_EQ_BPF3_A1:
726 case RT5682_R_EQ_BPF3_A1:
727 case RT5682_L_EQ_BPF3_A2:
728 case RT5682_R_EQ_BPF3_A2:
729 case RT5682_L_EQ_BPF3_H0:
730 case RT5682_R_EQ_BPF3_H0:
731 case RT5682_L_EQ_BPF4_A1:
732 case RT5682_R_EQ_BPF4_A1:
733 case RT5682_L_EQ_BPF4_A2:
734 case RT5682_R_EQ_BPF4_A2:
735 case RT5682_L_EQ_BPF4_H0:
736 case RT5682_R_EQ_BPF4_H0:
737 case RT5682_L_EQ_HPF1_A1:
738 case RT5682_R_EQ_HPF1_A1:
739 case RT5682_L_EQ_HPF1_H0:
740 case RT5682_R_EQ_HPF1_H0:
741 case RT5682_L_EQ_PRE_VOL:
742 case RT5682_R_EQ_PRE_VOL:
743 case RT5682_L_EQ_POST_VOL:
744 case RT5682_R_EQ_POST_VOL:
745 case RT5682_I2C_MODE:
746 return true;
747 default:
748 return false;
749 }
750}
751
752static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0);
753static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
754static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
755static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
756
757/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
758static const DECLARE_TLV_DB_RANGE(bst_tlv,
759 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
760 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
761 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
762 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
763 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
764 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
765 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
766);
767
768/* Interface data select */
769static const char * const rt5682_data_select[] = {
770 "L/R", "R/L", "L/L", "R/R"
771};
772
773static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum,
774 RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select);
775
776static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum,
777 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select);
778
779static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum,
780 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select);
781
782static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum,
783 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select);
784
785static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum,
786 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select);
787
788static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux =
789 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum);
790
791static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux =
792 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum);
793
794static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux =
795 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum);
796
797static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux =
798 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum);
799
800static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux =
801 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum);
802
803static void rt5682_reset(struct regmap *regmap)
804{
805 regmap_write(regmap, RT5682_RESET, 0);
806 regmap_write(regmap, RT5682_I2C_MODE, 1);
807}
808/**
809 * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters
810 * @component: SoC audio component device.
811 * @filter_mask: mask of filters.
812 * @clk_src: clock source
813 *
814 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can
815 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
816 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
817 * ASRC function will track i2s clock and generate a corresponding system clock
818 * for codec. This function provides an API to select the clock source for a
819 * set of filters specified by the mask. And the component driver will turn on
820 * ASRC for these filters if ASRC is selected as their clock source.
821 */
822int rt5682_sel_asrc_clk_src(struct snd_soc_component *component,
823 unsigned int filter_mask, unsigned int clk_src)
824{
825
826 switch (clk_src) {
827 case RT5682_CLK_SEL_SYS:
828 case RT5682_CLK_SEL_I2S1_ASRC:
829 case RT5682_CLK_SEL_I2S2_ASRC:
830 break;
831
832 default:
833 return -EINVAL;
834 }
835
836 if (filter_mask & RT5682_DA_STEREO1_FILTER) {
837 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2,
838 RT5682_FILTER_CLK_SEL_MASK,
839 clk_src << RT5682_FILTER_CLK_SEL_SFT);
840 }
841
842 if (filter_mask & RT5682_AD_STEREO1_FILTER) {
843 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3,
844 RT5682_FILTER_CLK_SEL_MASK,
845 clk_src << RT5682_FILTER_CLK_SEL_SFT);
846 }
847
848 return 0;
849}
850EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src);
851
852static int rt5682_button_detect(struct snd_soc_component *component)
853{
854 int btn_type, val;
855
856 val = snd_soc_component_read32(component, RT5682_4BTN_IL_CMD_1);
857 btn_type = val & 0xfff0;
858 snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val);
859 pr_debug("%s btn_type=%x\n", __func__, btn_type);
860
861 return btn_type;
862}
863
864static void rt5682_enable_push_button_irq(struct snd_soc_component *component,
865 bool enable)
866{
867 if (enable) {
868 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
869 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN);
870 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
871 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN);
872 snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040);
873 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
874 RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK,
875 RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR);
876 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
877 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_EN);
878 } else {
879 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
880 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS);
881 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
882 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS);
883 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
884 RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS);
885 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
886 RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST);
887 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
888 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE);
889 }
890}
891
892/**
893 * rt5682_headset_detect - Detect headset.
894 * @component: SoC audio component device.
895 * @jack_insert: Jack insert or not.
896 *
897 * Detect whether is headset or not when jack inserted.
898 *
899 * Returns detect status.
900 */
901static int rt5682_headset_detect(struct snd_soc_component *component,
902 int jack_insert)
903{
904 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
905 struct snd_soc_dapm_context *dapm =
906 snd_soc_component_get_dapm(component);
907 unsigned int val, count;
908
909 if (jack_insert) {
910 snd_soc_dapm_force_enable_pin(dapm, "CBJ Power");
911 snd_soc_dapm_sync(dapm);
912 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
913 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH);
914
915 count = 0;
916 val = snd_soc_component_read32(component, RT5682_CBJ_CTRL_2)
917 & RT5682_JACK_TYPE_MASK;
918 while (val == 0 && count < 50) {
919 usleep_range(10000, 15000);
920 val = snd_soc_component_read32(component,
921 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
922 count++;
923 }
924
925 switch (val) {
926 case 0x1:
927 case 0x2:
928 rt5682->jack_type = SND_JACK_HEADSET;
929 rt5682_enable_push_button_irq(component, true);
930 break;
931 default:
932 rt5682->jack_type = SND_JACK_HEADPHONE;
933 }
934
935 } else {
936 rt5682_enable_push_button_irq(component, false);
937 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
938 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
939 snd_soc_dapm_disable_pin(dapm, "CBJ Power");
940 snd_soc_dapm_sync(dapm);
941
942 rt5682->jack_type = 0;
943 }
944
945 dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type);
946 return rt5682->jack_type;
947}
948
949static irqreturn_t rt5682_irq(int irq, void *data)
950{
951 struct rt5682_priv *rt5682 = data;
952
953 mod_delayed_work(system_power_efficient_wq,
954 &rt5682->jack_detect_work, msecs_to_jiffies(250));
955
956 return IRQ_HANDLED;
957}
958
959static void rt5682_jd_check_handler(struct work_struct *work)
960{
961 struct rt5682_priv *rt5682 = container_of(work, struct rt5682_priv,
962 jd_check_work.work);
963
964 if (snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL)
965 & RT5682_JDH_RS_MASK) {
966 /* jack out */
967 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
968
969 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
970 SND_JACK_HEADSET |
971 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
972 SND_JACK_BTN_2 | SND_JACK_BTN_3);
973 } else {
974 schedule_delayed_work(&rt5682->jd_check_work, 500);
975 }
976}
977
978static int rt5682_set_jack_detect(struct snd_soc_component *component,
979 struct snd_soc_jack *hs_jack, void *data)
980{
981 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
982
983 switch (rt5682->pdata.jd_src) {
984 case RT5682_JD1:
985 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_2,
986 RT5682_EXT_JD_SRC, RT5682_EXT_JD_SRC_MANUAL);
987 snd_soc_component_write(component, RT5682_CBJ_CTRL_1, 0xd042);
988 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_3,
989 RT5682_CBJ_IN_BUF_EN, RT5682_CBJ_IN_BUF_EN);
990 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
991 RT5682_SAR_POW_MASK, RT5682_SAR_POW_EN);
992 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
993 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ);
994 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
995 RT5682_POW_IRQ | RT5682_POW_JDH |
996 RT5682_POW_ANA, RT5682_POW_IRQ |
997 RT5682_POW_JDH | RT5682_POW_ANA);
998 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2,
999 RT5682_PWR_JDH | RT5682_PWR_JDL,
1000 RT5682_PWR_JDH | RT5682_PWR_JDL);
1001 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1002 RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK,
1003 RT5682_JD1_EN | RT5682_JD1_POL_NOR);
1004 mod_delayed_work(system_power_efficient_wq,
1005 &rt5682->jack_detect_work, msecs_to_jiffies(250));
1006 break;
1007
1008 case RT5682_JD_NULL:
1009 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1010 RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1011 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1012 RT5682_POW_JDH | RT5682_POW_JDL, 0);
1013 break;
1014
1015 default:
1016 dev_warn(component->dev, "Wrong JD source\n");
1017 break;
1018 }
1019
1020 rt5682->hs_jack = hs_jack;
1021
1022 return 0;
1023}
1024
1025static void rt5682_jack_detect_handler(struct work_struct *work)
1026{
1027 struct rt5682_priv *rt5682 =
1028 container_of(work, struct rt5682_priv, jack_detect_work.work);
1029 int val, btn_type;
1030
1031 while (!rt5682->component)
1032 usleep_range(10000, 15000);
1033
1034 while (!rt5682->component->card->instantiated)
1035 usleep_range(10000, 15000);
1036
1037 mutex_lock(&rt5682->calibrate_mutex);
1038
1039 val = snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL)
1040 & RT5682_JDH_RS_MASK;
1041 if (!val) {
1042 /* jack in */
1043 if (rt5682->jack_type == 0) {
1044 /* jack was out, report jack type */
1045 rt5682->jack_type =
1046 rt5682_headset_detect(rt5682->component, 1);
1047 } else {
1048 /* jack is already in, report button event */
1049 rt5682->jack_type = SND_JACK_HEADSET;
1050 btn_type = rt5682_button_detect(rt5682->component);
1051 /**
1052 * rt5682 can report three kinds of button behavior,
1053 * one click, double click and hold. However,
1054 * currently we will report button pressed/released
1055 * event. So all the three button behaviors are
1056 * treated as button pressed.
1057 */
1058 switch (btn_type) {
1059 case 0x8000:
1060 case 0x4000:
1061 case 0x2000:
1062 rt5682->jack_type |= SND_JACK_BTN_0;
1063 break;
1064 case 0x1000:
1065 case 0x0800:
1066 case 0x0400:
1067 rt5682->jack_type |= SND_JACK_BTN_1;
1068 break;
1069 case 0x0200:
1070 case 0x0100:
1071 case 0x0080:
1072 rt5682->jack_type |= SND_JACK_BTN_2;
1073 break;
1074 case 0x0040:
1075 case 0x0020:
1076 case 0x0010:
1077 rt5682->jack_type |= SND_JACK_BTN_3;
1078 break;
1079 case 0x0000: /* unpressed */
1080 break;
1081 default:
1082 btn_type = 0;
1083 dev_err(rt5682->component->dev,
1084 "Unexpected button code 0x%04x\n",
1085 btn_type);
1086 break;
1087 }
1088 }
1089 } else {
1090 /* jack out */
1091 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
1092 }
1093
1094 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
1095 SND_JACK_HEADSET |
1096 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1097 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1098
1099 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1100 SND_JACK_BTN_2 | SND_JACK_BTN_3))
1101 schedule_delayed_work(&rt5682->jd_check_work, 0);
1102 else
1103 cancel_delayed_work_sync(&rt5682->jd_check_work);
1104
1105 mutex_unlock(&rt5682->calibrate_mutex);
1106}
1107
1108static const struct snd_kcontrol_new rt5682_snd_controls[] = {
1109 /* Headphone Output Volume */
1110 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5682_HPL_GAIN,
1111 RT5682_HPR_GAIN, RT5682_G_HP_SFT, 15, 1, hp_vol_tlv),
1112
1113 /* DAC Digital Volume */
1114 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL,
1115 RT5682_L_VOL_SFT, RT5682_R_VOL_SFT, 175, 0, dac_vol_tlv),
1116
1117 /* IN Boost Volume */
1118 SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL,
1119 RT5682_BST_CBJ_SFT, 8, 0, bst_tlv),
1120
1121 /* ADC Digital Volume Control */
1122 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL,
1123 RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1),
1124 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL,
1125 RT5682_L_VOL_SFT, RT5682_R_VOL_SFT, 127, 0, adc_vol_tlv),
1126
1127 /* ADC Boost Volume Control */
1128 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST,
1129 RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT,
1130 3, 0, adc_bst_tlv),
1131};
1132
1133
1134static int rt5682_div_sel(struct rt5682_priv *rt5682,
1135 int target, const int div[], int size)
1136{
1137 int i;
1138
1139 if (rt5682->sysclk < target) {
1140 pr_err("sysclk rate %d is too low\n",
1141 rt5682->sysclk);
1142 return 0;
1143 }
1144
1145 for (i = 0; i < size - 1; i++) {
1146 pr_info("div[%d]=%d\n", i, div[i]);
1147 if (target * div[i] == rt5682->sysclk)
1148 return i;
1149 if (target * div[i + 1] > rt5682->sysclk) {
1150 pr_err("can't find div for sysclk %d\n",
1151 rt5682->sysclk);
1152 return i;
1153 }
1154 }
1155
1156 if (target * div[i] < rt5682->sysclk)
1157 pr_err("sysclk rate %d is too high\n",
1158 rt5682->sysclk);
1159
1160 return size - 1;
1161
1162}
1163
1164/**
1165 * set_dmic_clk - Set parameter of dmic.
1166 *
1167 * @w: DAPM widget.
1168 * @kcontrol: The kcontrol of this widget.
1169 * @event: Event id.
1170 *
1171 * Choose dmic clock between 1MHz and 3MHz.
1172 * It is better for clock to approximate 3MHz.
1173 */
1174static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1175 struct snd_kcontrol *kcontrol, int event)
1176{
1177 struct snd_soc_component *component =
1178 snd_soc_dapm_to_component(w->dapm);
1179 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1180 int idx = -EINVAL;
1181 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
1182
1183 idx = rt5682_div_sel(rt5682, 1500000, div, ARRAY_SIZE(div));
1184
1185 snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1,
1186 RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT);
1187
1188 return 0;
1189}
1190
1191static int set_filter_clk(struct snd_soc_dapm_widget *w,
1192 struct snd_kcontrol *kcontrol, int event)
1193{
1194 struct snd_soc_component *component =
1195 snd_soc_dapm_to_component(w->dapm);
1196 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1197 int ref, val, reg, sft, mask, idx = -EINVAL;
1198 static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1199 static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48};
1200
1201 val = snd_soc_component_read32(component, RT5682_GPIO_CTRL_1) &
1202 RT5682_GP4_PIN_MASK;
1203 if (w->shift == RT5682_PWR_ADC_S1F_BIT &&
1204 val == RT5682_GP4_PIN_ADCDAT2)
1205 ref = 256 * rt5682->lrck[RT5682_AIF2];
1206 else
1207 ref = 256 * rt5682->lrck[RT5682_AIF1];
1208
1209 idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f));
1210
1211 if (w->shift == RT5682_PWR_ADC_S1F_BIT) {
1212 reg = RT5682_PLL_TRACK_3;
1213 sft = RT5682_ADC_OSR_SFT;
1214 mask = RT5682_ADC_OSR_MASK;
1215 } else {
1216 reg = RT5682_PLL_TRACK_2;
1217 sft = RT5682_DAC_OSR_SFT;
1218 mask = RT5682_DAC_OSR_MASK;
1219 }
1220
1221 snd_soc_component_update_bits(component, reg,
1222 RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT);
1223
1224 /* select over sample rate */
1225 for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) {
1226 if (rt5682->sysclk <= 12288000 * div_o[idx])
1227 break;
1228 }
1229
1230 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
1231 mask, idx << sft);
1232
1233 return 0;
1234}
1235
1236static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w,
1237 struct snd_soc_dapm_widget *sink)
1238{
1239 unsigned int val;
1240 struct snd_soc_component *component =
1241 snd_soc_dapm_to_component(w->dapm);
1242
1243 val = snd_soc_component_read32(component, RT5682_GLB_CLK);
1244 val &= RT5682_SCLK_SRC_MASK;
1245 if (val == RT5682_SCLK_SRC_PLL1)
1246 return 1;
1247 else
1248 return 0;
1249}
1250
1251static int is_using_asrc(struct snd_soc_dapm_widget *w,
1252 struct snd_soc_dapm_widget *sink)
1253{
1254 unsigned int reg, shift, val;
1255 struct snd_soc_component *component =
1256 snd_soc_dapm_to_component(w->dapm);
1257
1258 switch (w->shift) {
1259 case RT5682_ADC_STO1_ASRC_SFT:
1260 reg = RT5682_PLL_TRACK_3;
1261 shift = RT5682_FILTER_CLK_SEL_SFT;
1262 break;
1263 case RT5682_DAC_STO1_ASRC_SFT:
1264 reg = RT5682_PLL_TRACK_2;
1265 shift = RT5682_FILTER_CLK_SEL_SFT;
1266 break;
1267 default:
1268 return 0;
1269 }
1270
1271 val = (snd_soc_component_read32(component, reg) >> shift) & 0xf;
1272 switch (val) {
1273 case RT5682_CLK_SEL_I2S1_ASRC:
1274 case RT5682_CLK_SEL_I2S2_ASRC:
1275 return 1;
1276 default:
1277 return 0;
1278 }
1279
1280}
1281
1282/* Digital Mixer */
1283static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = {
1284 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1285 RT5682_M_STO1_ADC_L1_SFT, 1, 1),
1286 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1287 RT5682_M_STO1_ADC_L2_SFT, 1, 1),
1288};
1289
1290static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = {
1291 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1292 RT5682_M_STO1_ADC_R1_SFT, 1, 1),
1293 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1294 RT5682_M_STO1_ADC_R2_SFT, 1, 1),
1295};
1296
1297static const struct snd_kcontrol_new rt5682_dac_l_mix[] = {
1298 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1299 RT5682_M_ADCMIX_L_SFT, 1, 1),
1300 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1301 RT5682_M_DAC1_L_SFT, 1, 1),
1302};
1303
1304static const struct snd_kcontrol_new rt5682_dac_r_mix[] = {
1305 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1306 RT5682_M_ADCMIX_R_SFT, 1, 1),
1307 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1308 RT5682_M_DAC1_R_SFT, 1, 1),
1309};
1310
1311static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = {
1312 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1313 RT5682_M_DAC_L1_STO_L_SFT, 1, 1),
1314 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1315 RT5682_M_DAC_R1_STO_L_SFT, 1, 1),
1316};
1317
1318static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = {
1319 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1320 RT5682_M_DAC_L1_STO_R_SFT, 1, 1),
1321 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1322 RT5682_M_DAC_R1_STO_R_SFT, 1, 1),
1323};
1324
1325/* Analog Input Mixer */
1326static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = {
1327 SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER,
1328 RT5682_M_CBJ_RM1_L_SFT, 1, 1),
1329};
1330
1331/* STO1 ADC1 Source */
1332/* MX-26 [13] [5] */
1333static const char * const rt5682_sto1_adc1_src[] = {
1334 "DAC MIX", "ADC"
1335};
1336
1337static SOC_ENUM_SINGLE_DECL(
1338 rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER,
1339 RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src);
1340
1341static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux =
1342 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum);
1343
1344static SOC_ENUM_SINGLE_DECL(
1345 rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER,
1346 RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src);
1347
1348static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux =
1349 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum);
1350
1351/* STO1 ADC Source */
1352/* MX-26 [11:10] [3:2] */
1353static const char * const rt5682_sto1_adc_src[] = {
1354 "ADC1 L", "ADC1 R"
1355};
1356
1357static SOC_ENUM_SINGLE_DECL(
1358 rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER,
1359 RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src);
1360
1361static const struct snd_kcontrol_new rt5682_sto1_adcl_mux =
1362 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum);
1363
1364static SOC_ENUM_SINGLE_DECL(
1365 rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER,
1366 RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src);
1367
1368static const struct snd_kcontrol_new rt5682_sto1_adcr_mux =
1369 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum);
1370
1371/* STO1 ADC2 Source */
1372/* MX-26 [12] [4] */
1373static const char * const rt5682_sto1_adc2_src[] = {
1374 "DAC MIX", "DMIC"
1375};
1376
1377static SOC_ENUM_SINGLE_DECL(
1378 rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER,
1379 RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src);
1380
1381static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux =
1382 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum);
1383
1384static SOC_ENUM_SINGLE_DECL(
1385 rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER,
1386 RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src);
1387
1388static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux =
1389 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum);
1390
1391/* MX-79 [6:4] I2S1 ADC data location */
1392static const unsigned int rt5682_if1_adc_slot_values[] = {
1393 0,
1394 2,
1395 4,
1396 6,
1397};
1398
1399static const char * const rt5682_if1_adc_slot_src[] = {
1400 "Slot 0", "Slot 2", "Slot 4", "Slot 6"
1401};
1402
1403static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum,
1404 RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK,
1405 rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values);
1406
1407static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux =
1408 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum);
1409
1410/* Analog DAC L1 Source, Analog DAC R1 Source*/
1411/* MX-2B [4], MX-2B [0]*/
1412static const char * const rt5682_alg_dac1_src[] = {
1413 "Stereo1 DAC Mixer", "DAC1"
1414};
1415
1416static SOC_ENUM_SINGLE_DECL(
1417 rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX,
1418 RT5682_A_DACL1_SFT, rt5682_alg_dac1_src);
1419
1420static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux =
1421 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum);
1422
1423static SOC_ENUM_SINGLE_DECL(
1424 rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX,
1425 RT5682_A_DACR1_SFT, rt5682_alg_dac1_src);
1426
1427static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux =
1428 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum);
1429
1430/* Out Switch */
1431static const struct snd_kcontrol_new hpol_switch =
1432 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1433 RT5682_L_MUTE_SFT, 1, 1);
1434static const struct snd_kcontrol_new hpor_switch =
1435 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1436 RT5682_R_MUTE_SFT, 1, 1);
1437
1438static int rt5682_hp_event(struct snd_soc_dapm_widget *w,
1439 struct snd_kcontrol *kcontrol, int event)
1440{
1441 struct snd_soc_component *component =
1442 snd_soc_dapm_to_component(w->dapm);
1443
1444 switch (event) {
1445 case SND_SOC_DAPM_PRE_PMU:
1446 snd_soc_component_write(component,
1447 RT5682_HP_LOGIC_CTRL_2, 0x0012);
1448 snd_soc_component_write(component,
1449 RT5682_HP_CTRL_2, 0x6000);
1450 snd_soc_component_update_bits(component, RT5682_STO_NG2_CTRL_1,
1451 RT5682_NG2_EN_MASK, RT5682_NG2_EN);
1452 snd_soc_component_update_bits(component,
1453 RT5682_DEPOP_1, 0x60, 0x60);
1454 break;
1455
1456 case SND_SOC_DAPM_POST_PMD:
1457 snd_soc_component_update_bits(component,
1458 RT5682_DEPOP_1, 0x60, 0x0);
1459 snd_soc_component_write(component,
1460 RT5682_HP_CTRL_2, 0x0000);
1461 break;
1462
1463 default:
1464 return 0;
1465 }
1466
1467 return 0;
1468
1469}
1470
1471static int set_dmic_power(struct snd_soc_dapm_widget *w,
1472 struct snd_kcontrol *kcontrol, int event)
1473{
1474 switch (event) {
1475 case SND_SOC_DAPM_POST_PMU:
1476 /*Add delay to avoid pop noise*/
1477 msleep(150);
1478 break;
1479
1480 default:
1481 return 0;
1482 }
1483
1484 return 0;
1485}
1486
1487static int rt5655_set_verf(struct snd_soc_dapm_widget *w,
1488 struct snd_kcontrol *kcontrol, int event)
1489{
1490 struct snd_soc_component *component =
1491 snd_soc_dapm_to_component(w->dapm);
1492
1493 switch (event) {
1494 case SND_SOC_DAPM_PRE_PMU:
1495 switch (w->shift) {
1496 case RT5682_PWR_VREF1_BIT:
1497 snd_soc_component_update_bits(component,
1498 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0);
1499 break;
1500
1501 case RT5682_PWR_VREF2_BIT:
1502 snd_soc_component_update_bits(component,
1503 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
1504 break;
1505
1506 default:
1507 break;
1508 }
1509 break;
1510
1511 case SND_SOC_DAPM_POST_PMU:
1512 usleep_range(15000, 20000);
1513 switch (w->shift) {
1514 case RT5682_PWR_VREF1_BIT:
1515 snd_soc_component_update_bits(component,
1516 RT5682_PWR_ANLG_1, RT5682_PWR_FV1,
1517 RT5682_PWR_FV1);
1518 break;
1519
1520 case RT5682_PWR_VREF2_BIT:
1521 snd_soc_component_update_bits(component,
1522 RT5682_PWR_ANLG_1, RT5682_PWR_FV2,
1523 RT5682_PWR_FV2);
1524 break;
1525
1526 default:
1527 break;
1528 }
1529 break;
1530
1531 default:
1532 return 0;
1533 }
1534
1535 return 0;
1536}
1537
1538static const unsigned int rt5682_adcdat_pin_values[] = {
1539 1,
1540 3,
1541};
1542
1543static const char * const rt5682_adcdat_pin_select[] = {
1544 "ADCDAT1",
1545 "ADCDAT2",
1546};
1547
1548static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum,
1549 RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK,
1550 rt5682_adcdat_pin_select, rt5682_adcdat_pin_values);
1551
1552static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl =
1553 SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum);
1554
1555static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = {
1556 SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT,
1557 0, NULL, 0),
1558 SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT,
1559 0, NULL, 0),
1560 SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT,
1561 0, NULL, 0),
1562 SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT,
1563 0, NULL, 0),
1564 SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0,
1565 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1566 SND_SOC_DAPM_SUPPLY("Vref2", RT5682_PWR_ANLG_1, RT5682_PWR_VREF2_BIT, 0,
1567 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1568
1569 /* ASRC */
1570 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1571 RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0),
1572 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1573 RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0),
1574 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1,
1575 RT5682_AD_ASRC_SFT, 0, NULL, 0),
1576 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1,
1577 RT5682_DA_ASRC_SFT, 0, NULL, 0),
1578 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1,
1579 RT5682_DMIC_ASRC_SFT, 0, NULL, 0),
1580
1581 /* Input Side */
1582 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT,
1583 0, NULL, 0),
1584 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT,
1585 0, NULL, 0),
1586
1587 /* Input Lines */
1588 SND_SOC_DAPM_INPUT("DMIC L1"),
1589 SND_SOC_DAPM_INPUT("DMIC R1"),
1590
1591 SND_SOC_DAPM_INPUT("IN1P"),
1592
1593 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1594 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1595 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1,
1596 RT5682_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
1597
1598 /* Boost */
1599 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
1600 0, 0, NULL, 0),
1601
1602 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5682_PWR_ANLG_3,
1603 RT5682_PWR_CBJ_BIT, 0, NULL, 0),
1604
1605 /* REC Mixer */
1606 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix,
1607 ARRAY_SIZE(rt5682_rec1_l_mix)),
1608 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2,
1609 RT5682_PWR_RM1_L_BIT, 0, NULL, 0),
1610
1611 /* ADCs */
1612 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
1613 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
1614
1615 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1,
1616 RT5682_PWR_ADC_L1_BIT, 0, NULL, 0),
1617 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1,
1618 RT5682_PWR_ADC_R1_BIT, 0, NULL, 0),
1619 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC,
1620 RT5682_CKGEN_ADC1_SFT, 0, NULL, 0),
1621
1622 /* ADC Mux */
1623 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1624 &rt5682_sto1_adc1l_mux),
1625 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1626 &rt5682_sto1_adc1r_mux),
1627 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1628 &rt5682_sto1_adc2l_mux),
1629 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1630 &rt5682_sto1_adc2r_mux),
1631 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1632 &rt5682_sto1_adcl_mux),
1633 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1634 &rt5682_sto1_adcr_mux),
1635 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
1636 &rt5682_if1_adc_slot_mux),
1637
1638 /* ADC Mixer */
1639 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2,
1640 RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk,
1641 SND_SOC_DAPM_PRE_PMU),
1642 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL,
1643 RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix,
1644 ARRAY_SIZE(rt5682_sto1_adc_l_mix)),
1645 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL,
1646 RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix,
1647 ARRAY_SIZE(rt5682_sto1_adc_r_mix)),
1648
1649 /* ADC PGA */
1650 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1651
1652 /* Digital Interface */
1653 SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT,
1654 0, NULL, 0),
1655 SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT,
1656 0, NULL, 0),
1657 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1658 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1659 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1660
1661 /* Digital Interface Select */
1662 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1663 &rt5682_if1_01_adc_swap_mux),
1664 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1665 &rt5682_if1_23_adc_swap_mux),
1666 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1667 &rt5682_if1_45_adc_swap_mux),
1668 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1669 &rt5682_if1_67_adc_swap_mux),
1670 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1671 &rt5682_if2_adc_swap_mux),
1672
1673 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0,
1674 &rt5682_adcdat_pin_ctrl),
1675
1676 /* Audio Interface */
1677 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
1678 RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1),
1679 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
1680 RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1),
1681 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1682
1683 /* Output Side */
1684 /* DAC mixer before sound effect */
1685 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1686 rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)),
1687 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1688 rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)),
1689
1690 /* DAC channel Mux */
1691 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
1692 &rt5682_alg_dac_l1_mux),
1693 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
1694 &rt5682_alg_dac_r1_mux),
1695
1696 /* DAC Mixer */
1697 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2,
1698 RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk,
1699 SND_SOC_DAPM_PRE_PMU),
1700 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
1701 rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)),
1702 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
1703 rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)),
1704
1705 /* DACs */
1706 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1,
1707 RT5682_PWR_DAC_L1_BIT, 0),
1708 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1,
1709 RT5682_PWR_DAC_R1_BIT, 0),
1710 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC,
1711 RT5682_CKGEN_DAC1_SFT, 0, NULL, 0),
1712
1713 /* HPO */
1714 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event,
1715 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
1716
1717 SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1,
1718 RT5682_PWR_HA_L_BIT, 0, NULL, 0),
1719 SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1,
1720 RT5682_PWR_HA_R_BIT, 0, NULL, 0),
1721 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1,
1722 RT5682_PUMP_EN_SFT, 0, NULL, 0),
1723 SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1,
1724 RT5682_CAPLESS_EN_SFT, 0, NULL, 0),
1725
1726 SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0,
1727 &hpol_switch),
1728 SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0,
1729 &hpor_switch),
1730
1731 /* CLK DET */
1732 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET,
1733 RT5682_SYS_CLK_DET_SFT, 0, NULL, 0),
1734 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET,
1735 RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0),
1736 SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET,
1737 RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0),
1738 SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET,
1739 RT5682_POW_CLK_DET_SFT, 0, NULL, 0),
1740
1741 /* Output Lines */
1742 SND_SOC_DAPM_OUTPUT("HPOL"),
1743 SND_SOC_DAPM_OUTPUT("HPOR"),
1744
1745};
1746
1747static const struct snd_soc_dapm_route rt5682_dapm_routes[] = {
1748 /*PLL*/
1749 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1750 {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1751
1752 /*ASRC*/
1753 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1754 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
1755 {"ADC STO1 ASRC", NULL, "AD ASRC"},
1756 {"ADC STO1 ASRC", NULL, "CLKDET"},
1757 {"DAC STO1 ASRC", NULL, "DA ASRC"},
1758 {"DAC STO1 ASRC", NULL, "CLKDET"},
1759
1760 /*Vref*/
1761 {"MICBIAS1", NULL, "Vref1"},
1762 {"MICBIAS1", NULL, "Vref2"},
1763 {"MICBIAS2", NULL, "Vref1"},
1764 {"MICBIAS2", NULL, "Vref2"},
1765
1766 {"CLKDET SYS", NULL, "CLKDET"},
1767
1768 {"IN1P", NULL, "LDO2"},
1769
1770 {"BST1 CBJ", NULL, "IN1P"},
1771 {"BST1 CBJ", NULL, "CBJ Power"},
1772 {"CBJ Power", NULL, "Vref2"},
1773
1774 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
1775 {"RECMIX1L", NULL, "RECMIX1L Power"},
1776
1777 {"ADC1 L", NULL, "RECMIX1L"},
1778 {"ADC1 L", NULL, "ADC1 L Power"},
1779 {"ADC1 L", NULL, "ADC1 clock"},
1780
1781 {"DMIC L1", NULL, "DMIC CLK"},
1782 {"DMIC L1", NULL, "DMIC1 Power"},
1783 {"DMIC R1", NULL, "DMIC CLK"},
1784 {"DMIC R1", NULL, "DMIC1 Power"},
1785 {"DMIC CLK", NULL, "DMIC ASRC"},
1786
1787 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1788 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1789 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1790 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1791
1792 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1793 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1794 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1795 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1796
1797 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1798 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1799 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1800 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1801
1802 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1803 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1804 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1805
1806 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1807 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1808 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1809
1810 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1811 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1812
1813 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1814 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1815 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1816 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1817 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1818 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1819 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1820 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1821 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1822 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1823 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1824 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1825 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1826 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1827 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1828 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1829
1830 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1831 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1832 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1833 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1834 {"IF1_ADC Mux", NULL, "I2S1"},
1835 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
1836 {"AIF1TX", NULL, "ADCDAT Mux"},
1837 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1838 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1839 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1840 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1841 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1842 {"AIF2TX", NULL, "ADCDAT Mux"},
1843
1844 {"IF1 DAC1 L", NULL, "AIF1RX"},
1845 {"IF1 DAC1 L", NULL, "I2S1"},
1846 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
1847 {"IF1 DAC1 R", NULL, "AIF1RX"},
1848 {"IF1 DAC1 R", NULL, "I2S1"},
1849 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
1850
1851 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1852 {"DAC1 MIXL", "DAC1 Switch", "IF1 DAC1 L"},
1853 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1854 {"DAC1 MIXR", "DAC1 Switch", "IF1 DAC1 R"},
1855
1856 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
1857 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
1858
1859 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
1860 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
1861
1862 {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
1863 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
1864 {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
1865 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
1866
1867 {"DAC L1", NULL, "DAC L1 Source"},
1868 {"DAC R1", NULL, "DAC R1 Source"},
1869
1870 {"DAC L1", NULL, "DAC 1 Clock"},
1871 {"DAC R1", NULL, "DAC 1 Clock"},
1872
1873 {"HP Amp", NULL, "DAC L1"},
1874 {"HP Amp", NULL, "DAC R1"},
1875 {"HP Amp", NULL, "HP Amp L"},
1876 {"HP Amp", NULL, "HP Amp R"},
1877 {"HP Amp", NULL, "Capless"},
1878 {"HP Amp", NULL, "Charge Pump"},
1879 {"HP Amp", NULL, "CLKDET SYS"},
1880 {"HP Amp", NULL, "CBJ Power"},
1881 {"HP Amp", NULL, "Vref2"},
1882 {"HPOL Playback", "Switch", "HP Amp"},
1883 {"HPOR Playback", "Switch", "HP Amp"},
1884 {"HPOL", NULL, "HPOL Playback"},
1885 {"HPOR", NULL, "HPOR Playback"},
1886};
1887
1888static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1889 unsigned int rx_mask, int slots, int slot_width)
1890{
1891 struct snd_soc_component *component = dai->component;
1892 unsigned int cl, val = 0;
1893
1894 if (tx_mask || rx_mask)
1895 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
1896 RT5682_TDM_EN, RT5682_TDM_EN);
1897 else
1898 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
1899 RT5682_TDM_EN, 0);
1900
1901 switch (slots) {
1902 case 4:
1903 val |= RT5682_TDM_TX_CH_4;
1904 val |= RT5682_TDM_RX_CH_4;
1905 break;
1906 case 6:
1907 val |= RT5682_TDM_TX_CH_6;
1908 val |= RT5682_TDM_RX_CH_6;
1909 break;
1910 case 8:
1911 val |= RT5682_TDM_TX_CH_8;
1912 val |= RT5682_TDM_RX_CH_8;
1913 break;
1914 case 2:
1915 break;
1916 default:
1917 return -EINVAL;
1918 }
1919
1920 snd_soc_component_update_bits(component, RT5682_TDM_CTRL,
1921 RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val);
1922
1923 switch (slot_width) {
1924 case 8:
1925 if (tx_mask || rx_mask)
1926 return -EINVAL;
1927 cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8;
1928 break;
1929 case 16:
1930 val = RT5682_TDM_CL_16;
1931 cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16;
1932 break;
1933 case 20:
1934 val = RT5682_TDM_CL_20;
1935 cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20;
1936 break;
1937 case 24:
1938 val = RT5682_TDM_CL_24;
1939 cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24;
1940 break;
1941 case 32:
1942 val = RT5682_TDM_CL_32;
1943 cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32;
1944 break;
1945 default:
1946 return -EINVAL;
1947 }
1948
1949 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
1950 RT5682_TDM_CL_MASK, val);
1951 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
1952 RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl);
1953
1954 return 0;
1955}
1956
1957
1958static int rt5682_hw_params(struct snd_pcm_substream *substream,
1959 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1960{
1961 struct snd_soc_component *component = dai->component;
1962 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1963 unsigned int len_1 = 0, len_2 = 0;
1964 int pre_div, frame_size;
1965
1966 rt5682->lrck[dai->id] = params_rate(params);
1967 pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]);
1968
1969 frame_size = snd_soc_params_to_frame_size(params);
1970 if (frame_size < 0) {
1971 dev_err(component->dev, "Unsupported frame size: %d\n",
1972 frame_size);
1973 return -EINVAL;
1974 }
1975
1976 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
1977 rt5682->lrck[dai->id], pre_div, dai->id);
1978
1979 switch (params_width(params)) {
1980 case 16:
1981 break;
1982 case 20:
1983 len_1 |= RT5682_I2S1_DL_20;
1984 len_2 |= RT5682_I2S2_DL_20;
1985 break;
1986 case 24:
1987 len_1 |= RT5682_I2S1_DL_24;
1988 len_2 |= RT5682_I2S2_DL_24;
1989 break;
1990 case 32:
1991 len_1 |= RT5682_I2S1_DL_32;
1992 len_2 |= RT5682_I2S2_DL_24;
1993 break;
1994 case 8:
1995 len_1 |= RT5682_I2S2_DL_8;
1996 len_2 |= RT5682_I2S2_DL_8;
1997 break;
1998 default:
1999 return -EINVAL;
2000 }
2001
2002 switch (dai->id) {
2003 case RT5682_AIF1:
2004 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2005 RT5682_I2S1_DL_MASK, len_1);
2006 if (rt5682->master[RT5682_AIF1]) {
2007 snd_soc_component_update_bits(component,
2008 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK,
2009 pre_div << RT5682_I2S_M_DIV_SFT);
2010 }
2011 if (params_channels(params) == 1) /* mono mode */
2012 snd_soc_component_update_bits(component,
2013 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2014 RT5682_I2S1_MONO_EN);
2015 else
2016 snd_soc_component_update_bits(component,
2017 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2018 RT5682_I2S1_MONO_DIS);
2019 break;
2020 case RT5682_AIF2:
2021 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2022 RT5682_I2S2_DL_MASK, len_2);
2023 if (rt5682->master[RT5682_AIF2]) {
2024 snd_soc_component_update_bits(component,
2025 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK,
2026 pre_div << RT5682_I2S2_M_PD_SFT);
2027 }
2028 if (params_channels(params) == 1) /* mono mode */
2029 snd_soc_component_update_bits(component,
2030 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2031 RT5682_I2S2_MONO_EN);
2032 else
2033 snd_soc_component_update_bits(component,
2034 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2035 RT5682_I2S2_MONO_DIS);
2036 break;
2037 default:
2038 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2039 return -EINVAL;
2040 }
2041
2042 return 0;
2043}
2044
2045static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2046{
2047 struct snd_soc_component *component = dai->component;
2048 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2049 unsigned int reg_val = 0, tdm_ctrl = 0;
2050
2051 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2052 case SND_SOC_DAIFMT_CBM_CFM:
2053 rt5682->master[dai->id] = 1;
2054 break;
2055 case SND_SOC_DAIFMT_CBS_CFS:
2056 rt5682->master[dai->id] = 0;
2057 break;
2058 default:
2059 return -EINVAL;
2060 }
2061
2062 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2063 case SND_SOC_DAIFMT_NB_NF:
2064 break;
2065 case SND_SOC_DAIFMT_IB_NF:
2066 reg_val |= RT5682_I2S_BP_INV;
2067 tdm_ctrl |= RT5682_TDM_S_BP_INV;
2068 break;
2069 case SND_SOC_DAIFMT_NB_IF:
2070 if (dai->id == RT5682_AIF1)
2071 tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV;
2072 else
2073 return -EINVAL;
2074 break;
2075 case SND_SOC_DAIFMT_IB_IF:
2076 if (dai->id == RT5682_AIF1)
2077 tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV |
2078 RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV;
2079 else
2080 return -EINVAL;
2081 break;
2082 default:
2083 return -EINVAL;
2084 }
2085
2086 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2087 case SND_SOC_DAIFMT_I2S:
2088 break;
2089 case SND_SOC_DAIFMT_LEFT_J:
2090 reg_val |= RT5682_I2S_DF_LEFT;
2091 tdm_ctrl |= RT5682_TDM_DF_LEFT;
2092 break;
2093 case SND_SOC_DAIFMT_DSP_A:
2094 reg_val |= RT5682_I2S_DF_PCM_A;
2095 tdm_ctrl |= RT5682_TDM_DF_PCM_A;
2096 break;
2097 case SND_SOC_DAIFMT_DSP_B:
2098 reg_val |= RT5682_I2S_DF_PCM_B;
2099 tdm_ctrl |= RT5682_TDM_DF_PCM_B;
2100 break;
2101 default:
2102 return -EINVAL;
2103 }
2104
2105 switch (dai->id) {
2106 case RT5682_AIF1:
2107 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2108 RT5682_I2S_DF_MASK, reg_val);
2109 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2110 RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK |
2111 RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK |
2112 RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK,
2113 tdm_ctrl | rt5682->master[dai->id]);
2114 break;
2115 case RT5682_AIF2:
2116 if (rt5682->master[dai->id] == 0)
2117 reg_val |= RT5682_I2S2_MS_S;
2118 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2119 RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK |
2120 RT5682_I2S_DF_MASK, reg_val);
2121 break;
2122 default:
2123 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2124 return -EINVAL;
2125 }
2126 return 0;
2127}
2128
2129static int rt5682_set_component_sysclk(struct snd_soc_component *component,
2130 int clk_id, int source, unsigned int freq, int dir)
2131{
2132 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2133 unsigned int reg_val = 0, src = 0;
2134
2135 if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src)
2136 return 0;
2137
2138 switch (clk_id) {
2139 case RT5682_SCLK_S_MCLK:
2140 reg_val |= RT5682_SCLK_SRC_MCLK;
2141 src = RT5682_CLK_SRC_MCLK;
2142 break;
2143 case RT5682_SCLK_S_PLL1:
2144 reg_val |= RT5682_SCLK_SRC_PLL1;
2145 src = RT5682_CLK_SRC_PLL1;
2146 break;
2147 case RT5682_SCLK_S_PLL2:
2148 reg_val |= RT5682_SCLK_SRC_PLL2;
2149 src = RT5682_CLK_SRC_PLL2;
2150 break;
2151 case RT5682_SCLK_S_RCCLK:
2152 reg_val |= RT5682_SCLK_SRC_RCCLK;
2153 src = RT5682_CLK_SRC_RCCLK;
2154 break;
2155 default:
2156 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2157 return -EINVAL;
2158 }
2159 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2160 RT5682_SCLK_SRC_MASK, reg_val);
2161
2162 if (rt5682->master[RT5682_AIF2]) {
2163 snd_soc_component_update_bits(component,
2164 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK,
2165 src << RT5682_I2S2_SRC_SFT);
2166 }
2167
2168 rt5682->sysclk = freq;
2169 rt5682->sysclk_src = clk_id;
2170
2171 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2172 freq, clk_id);
2173
2174 return 0;
2175}
2176
2177static int rt5682_set_component_pll(struct snd_soc_component *component,
2178 int pll_id, int source, unsigned int freq_in,
2179 unsigned int freq_out)
2180{
2181 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2182 struct rl6231_pll_code pll_code;
2183 int ret;
2184
2185 if (source == rt5682->pll_src && freq_in == rt5682->pll_in &&
2186 freq_out == rt5682->pll_out)
2187 return 0;
2188
2189 if (!freq_in || !freq_out) {
2190 dev_dbg(component->dev, "PLL disabled\n");
2191
2192 rt5682->pll_in = 0;
2193 rt5682->pll_out = 0;
2194 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2195 RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK);
2196 return 0;
2197 }
2198
2199 switch (source) {
2200 case RT5682_PLL1_S_MCLK:
2201 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2202 RT5682_PLL1_SRC_MASK, RT5682_PLL1_SRC_MCLK);
2203 break;
2204 case RT5682_PLL1_S_BCLK1:
2205 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2206 RT5682_PLL1_SRC_MASK, RT5682_PLL1_SRC_BCLK1);
2207 break;
2208 default:
2209 dev_err(component->dev, "Unknown PLL Source %d\n", source);
2210 return -EINVAL;
2211 }
2212
2213 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2214 if (ret < 0) {
2215 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
2216 return ret;
2217 }
2218
2219 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
2220 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2221 pll_code.n_code, pll_code.k_code);
2222
2223 snd_soc_component_write(component, RT5682_PLL_CTRL_1,
2224 pll_code.n_code << RT5682_PLL_N_SFT | pll_code.k_code);
2225 snd_soc_component_write(component, RT5682_PLL_CTRL_2,
2226 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT |
2227 pll_code.m_bp << RT5682_PLL_M_BP_SFT | RT5682_PLL_RST);
2228
2229 rt5682->pll_in = freq_in;
2230 rt5682->pll_out = freq_out;
2231 rt5682->pll_src = source;
2232
2233 return 0;
2234}
2235
2236static int rt5682_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2237{
2238 struct snd_soc_component *component = dai->component;
2239 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2240
2241 rt5682->bclk[dai->id] = ratio;
2242
2243 switch (ratio) {
2244 case 64:
2245 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2246 RT5682_I2S2_BCLK_MS2_MASK,
2247 RT5682_I2S2_BCLK_MS2_64);
2248 break;
2249 case 32:
2250 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2251 RT5682_I2S2_BCLK_MS2_MASK,
2252 RT5682_I2S2_BCLK_MS2_32);
2253 break;
2254 default:
2255 dev_err(dai->dev, "Invalid bclk ratio %d\n", ratio);
2256 return -EINVAL;
2257 }
2258
2259 return 0;
2260}
2261
2262static int rt5682_set_bias_level(struct snd_soc_component *component,
2263 enum snd_soc_bias_level level)
2264{
2265 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2266
2267 switch (level) {
2268 case SND_SOC_BIAS_PREPARE:
2269 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2270 RT5682_PWR_MB | RT5682_PWR_BG,
2271 RT5682_PWR_MB | RT5682_PWR_BG);
2272 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2273 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO,
2274 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO);
2275 break;
2276
2277 case SND_SOC_BIAS_STANDBY:
2278 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2279 RT5682_PWR_MB, RT5682_PWR_MB);
2280 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2281 RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL);
2282 break;
2283 case SND_SOC_BIAS_OFF:
2284 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2285 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0);
2286 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2287 RT5682_PWR_MB | RT5682_PWR_BG, 0);
2288 break;
2289
2290 default:
2291 break;
2292 }
2293
2294 return 0;
2295}
2296
2297static int rt5682_probe(struct snd_soc_component *component)
2298{
2299 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2300
2301 rt5682->component = component;
2302
2303 return 0;
2304}
2305
2306static void rt5682_remove(struct snd_soc_component *component)
2307{
2308 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2309
2310 rt5682_reset(rt5682->regmap);
2311}
2312
2313#ifdef CONFIG_PM
2314static int rt5682_suspend(struct snd_soc_component *component)
2315{
2316 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2317
2318 regcache_cache_only(rt5682->regmap, true);
2319 regcache_mark_dirty(rt5682->regmap);
2320 return 0;
2321}
2322
2323static int rt5682_resume(struct snd_soc_component *component)
2324{
2325 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2326
2327 regcache_cache_only(rt5682->regmap, false);
2328 regcache_sync(rt5682->regmap);
2329
2330 return 0;
2331}
2332#else
2333#define rt5682_suspend NULL
2334#define rt5682_resume NULL
2335#endif
2336
2337#define RT5682_STEREO_RATES SNDRV_PCM_RATE_8000_192000
2338#define RT5682_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2339 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2340
2341static const struct snd_soc_dai_ops rt5682_aif1_dai_ops = {
2342 .hw_params = rt5682_hw_params,
2343 .set_fmt = rt5682_set_dai_fmt,
2344 .set_tdm_slot = rt5682_set_tdm_slot,
2345};
2346
2347static const struct snd_soc_dai_ops rt5682_aif2_dai_ops = {
2348 .hw_params = rt5682_hw_params,
2349 .set_fmt = rt5682_set_dai_fmt,
2350 .set_bclk_ratio = rt5682_set_bclk_ratio,
2351};
2352
2353static struct snd_soc_dai_driver rt5682_dai[] = {
2354 {
2355 .name = "rt5682-aif1",
2356 .id = RT5682_AIF1,
2357 .playback = {
2358 .stream_name = "AIF1 Playback",
2359 .channels_min = 1,
2360 .channels_max = 2,
2361 .rates = RT5682_STEREO_RATES,
2362 .formats = RT5682_FORMATS,
2363 },
2364 .capture = {
2365 .stream_name = "AIF1 Capture",
2366 .channels_min = 1,
2367 .channels_max = 2,
2368 .rates = RT5682_STEREO_RATES,
2369 .formats = RT5682_FORMATS,
2370 },
2371 .ops = &rt5682_aif1_dai_ops,
2372 },
2373 {
2374 .name = "rt5682-aif2",
2375 .id = RT5682_AIF2,
2376 .capture = {
2377 .stream_name = "AIF2 Capture",
2378 .channels_min = 1,
2379 .channels_max = 2,
2380 .rates = RT5682_STEREO_RATES,
2381 .formats = RT5682_FORMATS,
2382 },
2383 .ops = &rt5682_aif2_dai_ops,
2384 },
2385};
2386
2387static const struct snd_soc_component_driver soc_component_dev_rt5682 = {
2388 .probe = rt5682_probe,
2389 .remove = rt5682_remove,
2390 .suspend = rt5682_suspend,
2391 .resume = rt5682_resume,
2392 .set_bias_level = rt5682_set_bias_level,
2393 .controls = rt5682_snd_controls,
2394 .num_controls = ARRAY_SIZE(rt5682_snd_controls),
2395 .dapm_widgets = rt5682_dapm_widgets,
2396 .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets),
2397 .dapm_routes = rt5682_dapm_routes,
2398 .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes),
2399 .set_sysclk = rt5682_set_component_sysclk,
2400 .set_pll = rt5682_set_component_pll,
2401 .set_jack = rt5682_set_jack_detect,
2402 .use_pmdown_time = 1,
2403 .endianness = 1,
2404 .non_legacy_dai_naming = 1,
2405};
2406
2407static const struct regmap_config rt5682_regmap = {
2408 .reg_bits = 16,
2409 .val_bits = 16,
2410 .max_register = RT5682_I2C_MODE,
2411 .volatile_reg = rt5682_volatile_register,
2412 .readable_reg = rt5682_readable_register,
2413 .cache_type = REGCACHE_RBTREE,
2414 .reg_defaults = rt5682_reg,
2415 .num_reg_defaults = ARRAY_SIZE(rt5682_reg),
2416 .use_single_rw = true,
2417};
2418
2419static const struct i2c_device_id rt5682_i2c_id[] = {
2420 {"rt5682", 0},
2421 {}
2422};
2423MODULE_DEVICE_TABLE(i2c, rt5682_i2c_id);
2424
2425static int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev)
2426{
2427
2428 device_property_read_u32(dev, "realtek,dmic1-data-pin",
2429 &rt5682->pdata.dmic1_data_pin);
2430 device_property_read_u32(dev, "realtek,dmic1-clk-pin",
2431 &rt5682->pdata.dmic1_clk_pin);
2432 device_property_read_u32(dev, "realtek,jd-src",
2433 &rt5682->pdata.jd_src);
2434
2435 rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
2436 "realtek,ldo1-en-gpios", 0);
2437
2438 return 0;
2439}
2440
2441static void rt5682_calibrate(struct rt5682_priv *rt5682)
2442{
2443 int value, count;
2444
2445 mutex_lock(&rt5682->calibrate_mutex);
2446
2447 rt5682_reset(rt5682->regmap);
2448 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2bf);
2449 usleep_range(15000, 20000);
2450 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2bf);
2451 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0380);
2452 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x8001);
2453 regmap_write(rt5682->regmap, RT5682_TEST_MODE_CTRL_1, 0x0000);
2454 regmap_write(rt5682->regmap, RT5682_STO1_DAC_MIXER, 0x2080);
2455 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x4040);
2456 regmap_write(rt5682->regmap, RT5682_DEPOP_1, 0x0069);
2457 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000);
2458 regmap_write(rt5682->regmap, RT5682_HP_CTRL_2, 0x6000);
2459 regmap_write(rt5682->regmap, RT5682_HP_CHARGE_PUMP_1, 0x0f26);
2460 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7f05);
2461 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c);
2462 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d);
2463 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_9, 0x000f);
2464 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x8d01);
2465 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321);
2466 regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004);
2467 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
2468 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1);
2469 regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311);
2470 regmap_write(rt5682->regmap, RT5682_RESET_HPF_CTRL, 0x0000);
2471 regmap_write(rt5682->regmap, RT5682_ADC_STO1_HP_CTRL_1, 0x3320);
2472
2473 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00);
2474
2475 for (count = 0; count < 60; count++) {
2476 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value);
2477 if (!(value & 0x8000))
2478 break;
2479
2480 usleep_range(10000, 10005);
2481 }
2482
2483 if (count >= 60)
2484 pr_err("HP Calibration Failure\n");
2485
2486 /* restore settings */
2487 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4);
2488 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000);
2489
2490 mutex_unlock(&rt5682->calibrate_mutex);
2491
2492}
2493
2494static int rt5682_i2c_probe(struct i2c_client *i2c,
2495 const struct i2c_device_id *id)
2496{
2497 struct rt5682_platform_data *pdata = dev_get_platdata(&i2c->dev);
2498 struct rt5682_priv *rt5682;
2499 int i, ret;
2500 unsigned int val;
2501
2502 rt5682 = devm_kzalloc(&i2c->dev, sizeof(struct rt5682_priv),
2503 GFP_KERNEL);
2504
2505 if (rt5682 == NULL)
2506 return -ENOMEM;
2507
2508 i2c_set_clientdata(i2c, rt5682);
2509
2510 if (pdata)
2511 rt5682->pdata = *pdata;
2512 else
2513 rt5682_parse_dt(rt5682, &i2c->dev);
2514
2515 rt5682->regmap = devm_regmap_init_i2c(i2c, &rt5682_regmap);
2516 if (IS_ERR(rt5682->regmap)) {
2517 ret = PTR_ERR(rt5682->regmap);
2518 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2519 ret);
2520 return ret;
2521 }
2522
2523 for (i = 0; i < ARRAY_SIZE(rt5682->supplies); i++)
2524 rt5682->supplies[i].supply = rt5682_supply_names[i];
2525
2526 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5682->supplies),
2527 rt5682->supplies);
2528 if (ret != 0) {
2529 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
2530 return ret;
2531 }
2532
2533 ret = regulator_bulk_enable(ARRAY_SIZE(rt5682->supplies),
2534 rt5682->supplies);
2535 if (ret != 0) {
2536 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
2537 return ret;
2538 }
2539
2540 if (gpio_is_valid(rt5682->pdata.ldo1_en)) {
2541 if (devm_gpio_request_one(&i2c->dev, rt5682->pdata.ldo1_en,
2542 GPIOF_OUT_INIT_HIGH, "rt5682"))
2543 dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n");
2544 }
2545
2546 /* Sleep for 300 ms miniumum */
2547 usleep_range(300000, 350000);
2548
2549 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 0x1);
2550 usleep_range(10000, 15000);
2551
2552 regmap_read(rt5682->regmap, RT5682_DEVICE_ID, &val);
2553 if (val != DEVICE_ID) {
2554 pr_err("Device with ID register %x is not rt5682\n", val);
2555 return -ENODEV;
2556 }
2557
2558 rt5682_reset(rt5682->regmap);
2559
2560 rt5682_calibrate(rt5682);
2561
2562 ret = regmap_register_patch(rt5682->regmap, patch_list,
2563 ARRAY_SIZE(patch_list));
2564 if (ret != 0)
2565 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
2566
2567 regmap_write(rt5682->regmap, RT5682_DEPOP_1, 0x0000);
2568
2569 /* DMIC pin*/
2570 if (rt5682->pdata.dmic1_data_pin != RT5682_DMIC1_NULL) {
2571 switch (rt5682->pdata.dmic1_data_pin) {
2572 case RT5682_DMIC1_DATA_GPIO2: /* share with LRCK2 */
2573 regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1,
2574 RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO2);
2575 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2576 RT5682_GP2_PIN_MASK, RT5682_GP2_PIN_DMIC_SDA);
2577 break;
2578
2579 case RT5682_DMIC1_DATA_GPIO5: /* share with DACDAT1 */
2580 regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1,
2581 RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO5);
2582 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2583 RT5682_GP5_PIN_MASK, RT5682_GP5_PIN_DMIC_SDA);
2584 break;
2585
2586 default:
2587 dev_warn(&i2c->dev, "invalid DMIC_DAT pin\n");
2588 break;
2589 }
2590
2591 switch (rt5682->pdata.dmic1_clk_pin) {
2592 case RT5682_DMIC1_CLK_GPIO1: /* share with IRQ */
2593 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2594 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_DMIC_CLK);
2595 break;
2596
2597 case RT5682_DMIC1_CLK_GPIO3: /* share with BCLK2 */
2598 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2599 RT5682_GP3_PIN_MASK, RT5682_GP3_PIN_DMIC_CLK);
2600 break;
2601
2602 default:
2603 dev_warn(&i2c->dev, "invalid DMIC_CLK pin\n");
2604 break;
2605 }
2606 }
2607
2608 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2609 RT5682_LDO1_DVO_MASK | RT5682_HP_DRIVER_MASK,
2610 RT5682_LDO1_DVO_12 | RT5682_HP_DRIVER_5X);
2611 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0380);
2612 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2613 RT5682_GP4_PIN_MASK | RT5682_GP5_PIN_MASK,
2614 RT5682_GP4_PIN_ADCDAT1 | RT5682_GP5_PIN_DACDAT1);
2615 regmap_write(rt5682->regmap, RT5682_TEST_MODE_CTRL_1, 0x0000);
2616
2617 INIT_DELAYED_WORK(&rt5682->jack_detect_work,
2618 rt5682_jack_detect_handler);
2619 INIT_DELAYED_WORK(&rt5682->jd_check_work,
2620 rt5682_jd_check_handler);
2621
2622 mutex_init(&rt5682->calibrate_mutex);
2623
2624 if (i2c->irq) {
2625 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
2626 rt5682_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2627 | IRQF_ONESHOT, "rt5682", rt5682);
2628 if (ret)
2629 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
2630
2631 }
2632
Wei Yongjuna98ec932018-06-22 02:23:24 +0000[diff] [blame^]2633 return devm_snd_soc_register_component(&i2c->dev,
2634 &soc_component_dev_rt5682,
Bard Liao0ddce712018-06-07 16:37:38 +0800[diff] [blame]2635 rt5682_dai, ARRAY_SIZE(rt5682_dai));
2636}
2637
Bard Liao0ddce712018-06-07 16:37:38 +0800[diff] [blame]2638static void rt5682_i2c_shutdown(struct i2c_client *client)
2639{
2640 struct rt5682_priv *rt5682 = i2c_get_clientdata(client);
2641
2642 rt5682_reset(rt5682->regmap);
2643}
2644
2645#ifdef CONFIG_OF
2646static const struct of_device_id rt5682_of_match[] = {
2647 {.compatible = "realtek,rt5682i"},
2648 {},
2649};
2650MODULE_DEVICE_TABLE(of, rt5682_of_match);
2651#endif
2652
2653#ifdef CONFIG_ACPI
2654static const struct acpi_device_id rt5682_acpi_match[] = {
2655 {"10EC5682", 0,},
2656 {},
2657};
2658MODULE_DEVICE_TABLE(acpi, rt5682_acpi_match);
2659#endif
2660
2661static struct i2c_driver rt5682_i2c_driver = {
2662 .driver = {
2663 .name = "rt5682",
2664 .of_match_table = of_match_ptr(rt5682_of_match),
2665 .acpi_match_table = ACPI_PTR(rt5682_acpi_match),
2666 },
2667 .probe = rt5682_i2c_probe,
Bard Liao0ddce712018-06-07 16:37:38 +0800[diff] [blame]2668 .shutdown = rt5682_i2c_shutdown,
2669 .id_table = rt5682_i2c_id,
2670};
2671module_i2c_driver(rt5682_i2c_driver);
2672
2673MODULE_DESCRIPTION("ASoC RT5682 driver");
2674MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
2675MODULE_LICENSE("GPL v2");