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Thomas Gleixnera912e802019-05-27 08:55:00 +02001// SPDX-License-Identifier: GPL-2.0-or-later
Lars-Peter Clausen98698482010-07-17 11:08:43 +00002/*
3 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
4 * JZ4740 platform IRQ support
Lars-Peter Clausen98698482010-07-17 11:08:43 +00005 */
6
7#include <linux/errno.h>
8#include <linux/init.h>
9#include <linux/types.h>
10#include <linux/interrupt.h>
11#include <linux/ioport.h>
Joel Porquet41a83e062015-07-07 17:11:46 -040012#include <linux/irqchip.h>
Paul Burton44e08e72015-05-24 16:11:31 +010013#include <linux/irqchip/ingenic.h>
Paul Burton3aa94592015-05-24 16:11:28 +010014#include <linux/of_address.h>
Paul Burtonadbdce72015-05-24 16:11:21 +010015#include <linux/of_irq.h>
Lars-Peter Clausen98698482010-07-17 11:08:43 +000016#include <linux/timex.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
19
Lars-Peter Clausen98698482010-07-17 11:08:43 +000020#include <asm/io.h>
Brian Norris942e22d2014-12-17 18:39:01 -080021#include <asm/mach-jz4740/irq.h>
22
Paul Burtonfe778ec2015-05-24 16:11:25 +010023struct ingenic_intc_data {
24 void __iomem *base;
Paul Burton943d69c2015-05-24 16:11:26 +010025 unsigned num_chips;
Paul Burtonfe778ec2015-05-24 16:11:25 +010026};
Lars-Peter Clausen98698482010-07-17 11:08:43 +000027
28#define JZ_REG_INTC_STATUS 0x00
29#define JZ_REG_INTC_MASK 0x04
30#define JZ_REG_INTC_SET_MASK 0x08
31#define JZ_REG_INTC_CLEAR_MASK 0x0c
32#define JZ_REG_INTC_PENDING 0x10
Paul Burton943d69c2015-05-24 16:11:26 +010033#define CHIP_SIZE 0x20
Lars-Peter Clausen98698482010-07-17 11:08:43 +000034
Paul Burton2da01882015-05-24 16:11:29 +010035static irqreturn_t intc_cascade(int irq, void *data)
Lars-Peter Clausen98698482010-07-17 11:08:43 +000036{
Paul Burtonfe778ec2015-05-24 16:11:25 +010037 struct ingenic_intc_data *intc = irq_get_handler_data(irq);
Lars-Peter Clausen98698482010-07-17 11:08:43 +000038 uint32_t irq_reg;
Paul Burton943d69c2015-05-24 16:11:26 +010039 unsigned i;
Lars-Peter Clausen98698482010-07-17 11:08:43 +000040
Paul Burton943d69c2015-05-24 16:11:26 +010041 for (i = 0; i < intc->num_chips; i++) {
42 irq_reg = readl(intc->base + (i * CHIP_SIZE) +
43 JZ_REG_INTC_PENDING);
44 if (!irq_reg)
45 continue;
Lars-Peter Clausen98698482010-07-17 11:08:43 +000046
Paul Burton943d69c2015-05-24 16:11:26 +010047 generic_handle_irq(__fls(irq_reg) + (i * 32) + JZ4740_IRQ_BASE);
48 }
Lars-Peter Clausen98698482010-07-17 11:08:43 +000049
50 return IRQ_HANDLED;
51}
52
Paul Burton2da01882015-05-24 16:11:29 +010053static void intc_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask)
Lars-Peter Clausen83bc7692011-09-24 02:29:46 +020054{
55 struct irq_chip_regs *regs = &gc->chip_types->regs;
56
57 writel(mask, gc->reg_base + regs->enable);
58 writel(~mask, gc->reg_base + regs->disable);
59}
60
Paul Burton2da01882015-05-24 16:11:29 +010061void ingenic_intc_irq_suspend(struct irq_data *data)
Lars-Peter Clausen83bc7692011-09-24 02:29:46 +020062{
63 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
Paul Burton2da01882015-05-24 16:11:29 +010064 intc_irq_set_mask(gc, gc->wake_active);
Lars-Peter Clausen83bc7692011-09-24 02:29:46 +020065}
66
Paul Burton2da01882015-05-24 16:11:29 +010067void ingenic_intc_irq_resume(struct irq_data *data)
Lars-Peter Clausen83bc7692011-09-24 02:29:46 +020068{
69 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
Paul Burton2da01882015-05-24 16:11:29 +010070 intc_irq_set_mask(gc, gc->mask_cache);
Lars-Peter Clausen83bc7692011-09-24 02:29:46 +020071}
72
Paul Burton2da01882015-05-24 16:11:29 +010073static struct irqaction intc_cascade_action = {
74 .handler = intc_cascade,
75 .name = "SoC intc cascade interrupt",
Lars-Peter Clausen98698482010-07-17 11:08:43 +000076};
77
Paul Burton943d69c2015-05-24 16:11:26 +010078static int __init ingenic_intc_of_init(struct device_node *node,
79 unsigned num_chips)
Lars-Peter Clausen98698482010-07-17 11:08:43 +000080{
Paul Burtonfe778ec2015-05-24 16:11:25 +010081 struct ingenic_intc_data *intc;
Lars-Peter Clausen83bc7692011-09-24 02:29:46 +020082 struct irq_chip_generic *gc;
83 struct irq_chip_type *ct;
Paul Burton638c8852015-05-24 16:11:23 +010084 struct irq_domain *domain;
Paul Burtonfe778ec2015-05-24 16:11:25 +010085 int parent_irq, err = 0;
Paul Burton943d69c2015-05-24 16:11:26 +010086 unsigned i;
Paul Burtonfe778ec2015-05-24 16:11:25 +010087
88 intc = kzalloc(sizeof(*intc), GFP_KERNEL);
89 if (!intc) {
90 err = -ENOMEM;
91 goto out_err;
92 }
Paul Burton69ce4b22015-05-24 16:11:22 +010093
94 parent_irq = irq_of_parse_and_map(node, 0);
Paul Burtonfe778ec2015-05-24 16:11:25 +010095 if (!parent_irq) {
96 err = -EINVAL;
97 goto out_free;
98 }
Lars-Peter Clausen83bc7692011-09-24 02:29:46 +020099
Paul Burtonfe778ec2015-05-24 16:11:25 +0100100 err = irq_set_handler_data(parent_irq, intc);
101 if (err)
102 goto out_unmap_irq;
103
Paul Burton943d69c2015-05-24 16:11:26 +0100104 intc->num_chips = num_chips;
Paul Burton3aa94592015-05-24 16:11:28 +0100105 intc->base = of_iomap(node, 0);
106 if (!intc->base) {
107 err = -ENODEV;
108 goto out_unmap_irq;
109 }
Lars-Peter Clausen98698482010-07-17 11:08:43 +0000110
Paul Burton943d69c2015-05-24 16:11:26 +0100111 for (i = 0; i < num_chips; i++) {
112 /* Mask all irqs */
113 writel(0xffffffff, intc->base + (i * CHIP_SIZE) +
114 JZ_REG_INTC_SET_MASK);
Thomas Gleixner42b64f32011-03-23 21:08:53 +0000115
Paul Burton943d69c2015-05-24 16:11:26 +0100116 gc = irq_alloc_generic_chip("INTC", 1,
117 JZ4740_IRQ_BASE + (i * 32),
118 intc->base + (i * CHIP_SIZE),
119 handle_level_irq);
Lars-Peter Clausen83bc7692011-09-24 02:29:46 +0200120
Paul Burton943d69c2015-05-24 16:11:26 +0100121 gc->wake_enabled = IRQ_MSK(32);
Lars-Peter Clausen83bc7692011-09-24 02:29:46 +0200122
Paul Burton943d69c2015-05-24 16:11:26 +0100123 ct = gc->chip_types;
124 ct->regs.enable = JZ_REG_INTC_CLEAR_MASK;
125 ct->regs.disable = JZ_REG_INTC_SET_MASK;
126 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
127 ct->chip.irq_mask = irq_gc_mask_disable_reg;
128 ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
129 ct->chip.irq_set_wake = irq_gc_set_wake;
Paul Burton2da01882015-05-24 16:11:29 +0100130 ct->chip.irq_suspend = ingenic_intc_irq_suspend;
131 ct->chip.irq_resume = ingenic_intc_irq_resume;
Lars-Peter Clausen83bc7692011-09-24 02:29:46 +0200132
Paul Burton943d69c2015-05-24 16:11:26 +0100133 irq_setup_generic_chip(gc, IRQ_MSK(32), 0, 0,
134 IRQ_NOPROBE | IRQ_LEVEL);
135 }
Lars-Peter Clausen98698482010-07-17 11:08:43 +0000136
Paul Burton638c8852015-05-24 16:11:23 +0100137 domain = irq_domain_add_legacy(node, num_chips * 32, JZ4740_IRQ_BASE, 0,
138 &irq_domain_simple_ops, NULL);
139 if (!domain)
140 pr_warn("unable to register IRQ domain\n");
141
Paul Burton2da01882015-05-24 16:11:29 +0100142 setup_irq(parent_irq, &intc_cascade_action);
Paul Burtonadbdce72015-05-24 16:11:21 +0100143 return 0;
Paul Burtonfe778ec2015-05-24 16:11:25 +0100144
145out_unmap_irq:
146 irq_dispose_mapping(parent_irq);
147out_free:
148 kfree(intc);
149out_err:
150 return err;
Lars-Peter Clausen98698482010-07-17 11:08:43 +0000151}
Paul Burton943d69c2015-05-24 16:11:26 +0100152
153static int __init intc_1chip_of_init(struct device_node *node,
154 struct device_node *parent)
155{
156 return ingenic_intc_of_init(node, 1);
157}
158IRQCHIP_DECLARE(jz4740_intc, "ingenic,jz4740-intc", intc_1chip_of_init);
Paul Cercueil10475572018-07-13 16:49:09 +0200159IRQCHIP_DECLARE(jz4725b_intc, "ingenic,jz4725b-intc", intc_1chip_of_init);
Paul Burton24ccfa02015-05-24 16:11:30 +0100160
161static int __init intc_2chip_of_init(struct device_node *node,
162 struct device_node *parent)
163{
164 return ingenic_intc_of_init(node, 2);
165}
166IRQCHIP_DECLARE(jz4770_intc, "ingenic,jz4770-intc", intc_2chip_of_init);
167IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", intc_2chip_of_init);
168IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", intc_2chip_of_init);