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Ulrich Hecht0dce5452014-09-05 12:23:48 +02001/*
2 * Device Tree Source for the r8a7794 SoC
3 *
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2014 Ulrich Hecht
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12#include <dt-bindings/clock/r8a7794-clock.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15
16/ {
17 compatible = "renesas,r8a7794";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
Sergei Shtylyov740b4a92015-08-11 00:59:24 +030022 aliases {
Sergei Shtylyov54285212015-08-20 01:00:09 +030023 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 i2c2 = &i2c2;
26 i2c3 = &i2c3;
27 i2c4 = &i2c4;
28 i2c5 = &i2c5;
Sergei Shtylyov740b4a92015-08-11 00:59:24 +030029 spi0 = &qspi;
Sergei Shtylyov1afe77c2015-08-20 01:22:24 +030030 vin0 = &vin0;
31 vin1 = &vin1;
Sergei Shtylyov740b4a92015-08-11 00:59:24 +030032 };
33
Ulrich Hecht0dce5452014-09-05 12:23:48 +020034 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 cpu0: cpu@0 {
39 device_type = "cpu";
40 compatible = "arm,cortex-a7";
41 reg = <0>;
42 clock-frequency = <1000000000>;
Geert Uytterhoevend12a3842015-06-02 14:34:35 +020043 next-level-cache = <&L2_CA7>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +020044 };
45
46 cpu1: cpu@1 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a7";
49 reg = <1>;
50 clock-frequency = <1000000000>;
Geert Uytterhoevend12a3842015-06-02 14:34:35 +020051 next-level-cache = <&L2_CA7>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +020052 };
53 };
54
Geert Uytterhoevend12a3842015-06-02 14:34:35 +020055 L2_CA7: cache-controller@1 {
56 compatible = "cache";
57 cache-unified;
58 cache-level = <2>;
59 };
60
Ulrich Hecht0dce5452014-09-05 12:23:48 +020061 gic: interrupt-controller@f1001000 {
Geert Uytterhoevenc73ddf42015-06-17 15:03:36 +020062 compatible = "arm,gic-400";
Ulrich Hecht0dce5452014-09-05 12:23:48 +020063 #interrupt-cells = <3>;
64 #address-cells = <0>;
65 interrupt-controller;
66 reg = <0 0xf1001000 0 0x1000>,
67 <0 0xf1002000 0 0x1000>,
68 <0 0xf1004000 0 0x2000>,
69 <0 0xf1006000 0 0x2000>;
Simon Horman8d47e6a2016-01-18 14:18:44 +090070 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +020071 };
72
Sergei Shtylyove8f5de32015-08-09 01:09:31 +030073 gpio0: gpio@e6050000 {
74 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
75 reg = <0 0xe6050000 0 0x50>;
Simon Horman8d47e6a2016-01-18 14:18:44 +090076 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyove8f5de32015-08-09 01:09:31 +030077 #gpio-cells = <2>;
78 gpio-controller;
79 gpio-ranges = <&pfc 0 0 32>;
80 #interrupt-cells = <2>;
81 interrupt-controller;
82 clocks = <&mstp9_clks R8A7794_CLK_GPIO0>;
83 power-domains = <&cpg_clocks>;
84 };
85
86 gpio1: gpio@e6051000 {
87 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
88 reg = <0 0xe6051000 0 0x50>;
Simon Horman8d47e6a2016-01-18 14:18:44 +090089 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyove8f5de32015-08-09 01:09:31 +030090 #gpio-cells = <2>;
91 gpio-controller;
92 gpio-ranges = <&pfc 0 32 26>;
93 #interrupt-cells = <2>;
94 interrupt-controller;
95 clocks = <&mstp9_clks R8A7794_CLK_GPIO1>;
96 power-domains = <&cpg_clocks>;
97 };
98
99 gpio2: gpio@e6052000 {
100 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
101 reg = <0 0xe6052000 0 0x50>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900102 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyove8f5de32015-08-09 01:09:31 +0300103 #gpio-cells = <2>;
104 gpio-controller;
105 gpio-ranges = <&pfc 0 64 32>;
106 #interrupt-cells = <2>;
107 interrupt-controller;
108 clocks = <&mstp9_clks R8A7794_CLK_GPIO2>;
109 power-domains = <&cpg_clocks>;
110 };
111
112 gpio3: gpio@e6053000 {
113 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
114 reg = <0 0xe6053000 0 0x50>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900115 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyove8f5de32015-08-09 01:09:31 +0300116 #gpio-cells = <2>;
117 gpio-controller;
118 gpio-ranges = <&pfc 0 96 32>;
119 #interrupt-cells = <2>;
120 interrupt-controller;
121 clocks = <&mstp9_clks R8A7794_CLK_GPIO3>;
122 power-domains = <&cpg_clocks>;
123 };
124
125 gpio4: gpio@e6054000 {
126 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
127 reg = <0 0xe6054000 0 0x50>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900128 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyove8f5de32015-08-09 01:09:31 +0300129 #gpio-cells = <2>;
130 gpio-controller;
131 gpio-ranges = <&pfc 0 128 32>;
132 #interrupt-cells = <2>;
133 interrupt-controller;
134 clocks = <&mstp9_clks R8A7794_CLK_GPIO4>;
135 power-domains = <&cpg_clocks>;
136 };
137
138 gpio5: gpio@e6055000 {
139 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
140 reg = <0 0xe6055000 0 0x50>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900141 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyove8f5de32015-08-09 01:09:31 +0300142 #gpio-cells = <2>;
143 gpio-controller;
144 gpio-ranges = <&pfc 0 160 28>;
145 #interrupt-cells = <2>;
146 interrupt-controller;
147 clocks = <&mstp9_clks R8A7794_CLK_GPIO5>;
148 power-domains = <&cpg_clocks>;
149 };
150
151 gpio6: gpio@e6055400 {
152 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
153 reg = <0 0xe6055400 0 0x50>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900154 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyove8f5de32015-08-09 01:09:31 +0300155 #gpio-cells = <2>;
156 gpio-controller;
157 gpio-ranges = <&pfc 0 192 26>;
158 #interrupt-cells = <2>;
159 interrupt-controller;
160 clocks = <&mstp9_clks R8A7794_CLK_GPIO6>;
161 power-domains = <&cpg_clocks>;
162 };
163
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200164 cmt0: timer@ffca0000 {
165 compatible = "renesas,cmt-48-gen2";
166 reg = <0 0xffca0000 0 0x1004>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900167 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
168 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200169 clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
170 clock-names = "fck";
Geert Uytterhoeven60c07452015-08-04 14:28:13 +0200171 power-domains = <&cpg_clocks>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200172
173 renesas,channels-mask = <0x60>;
174
175 status = "disabled";
176 };
177
178 cmt1: timer@e6130000 {
179 compatible = "renesas,cmt-48-gen2";
180 reg = <0 0xe6130000 0 0x1004>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900181 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200189 clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
190 clock-names = "fck";
Geert Uytterhoeven60c07452015-08-04 14:28:13 +0200191 power-domains = <&cpg_clocks>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200192
193 renesas,channels-mask = <0xff>;
194
195 status = "disabled";
196 };
197
Hisashi Nakamurada336482014-09-12 10:52:06 +0200198 timer {
199 compatible = "arm,armv7-timer";
Simon Horman8d47e6a2016-01-18 14:18:44 +0900200 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
201 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
202 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
203 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
Hisashi Nakamurada336482014-09-12 10:52:06 +0200204 };
205
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200206 irqc0: interrupt-controller@e61c0000 {
207 compatible = "renesas,irqc-r8a7794", "renesas,irqc";
208 #interrupt-cells = <2>;
209 interrupt-controller;
210 reg = <0 0xe61c0000 0 0x200>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900211 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoeven1c5ca5d2015-03-18 19:56:01 +0100221 clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
Geert Uytterhoeven60c07452015-08-04 14:28:13 +0200222 power-domains = <&cpg_clocks>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200223 };
224
Sergei Shtylyovfd1683c2015-07-28 01:29:31 +0300225 pfc: pin-controller@e6060000 {
226 compatible = "renesas,pfc-r8a7794";
227 reg = <0 0xe6060000 0 0x11c>;
Sergei Shtylyovfd1683c2015-07-28 01:29:31 +0300228 };
229
Laurent Pinchartbd847482015-01-27 19:12:17 +0200230 dmac0: dma-controller@e6700000 {
Simon Horman0a3d0582015-11-13 11:23:51 +0900231 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
Laurent Pinchartbd847482015-01-27 19:12:17 +0200232 reg = <0 0xe6700000 0 0x20000>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900233 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
234 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
235 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
236 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
237 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
238 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
239 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
240 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
241 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
242 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
243 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
244 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
245 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
246 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
247 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
248 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchartbd847482015-01-27 19:12:17 +0200249 interrupt-names = "error",
250 "ch0", "ch1", "ch2", "ch3",
251 "ch4", "ch5", "ch6", "ch7",
252 "ch8", "ch9", "ch10", "ch11",
253 "ch12", "ch13", "ch14";
254 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
255 clock-names = "fck";
Geert Uytterhoeven60c07452015-08-04 14:28:13 +0200256 power-domains = <&cpg_clocks>;
Laurent Pinchartbd847482015-01-27 19:12:17 +0200257 #dma-cells = <1>;
258 dma-channels = <15>;
259 };
260
261 dmac1: dma-controller@e6720000 {
Simon Horman0a3d0582015-11-13 11:23:51 +0900262 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
Laurent Pinchartbd847482015-01-27 19:12:17 +0200263 reg = <0 0xe6720000 0 0x20000>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900264 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
265 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
266 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
267 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
268 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
269 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
270 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
271 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
272 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
273 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
274 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
275 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
276 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
277 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
278 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
279 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchartbd847482015-01-27 19:12:17 +0200280 interrupt-names = "error",
281 "ch0", "ch1", "ch2", "ch3",
282 "ch4", "ch5", "ch6", "ch7",
283 "ch8", "ch9", "ch10", "ch11",
284 "ch12", "ch13", "ch14";
285 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
286 clock-names = "fck";
Geert Uytterhoeven60c07452015-08-04 14:28:13 +0200287 power-domains = <&cpg_clocks>;
Laurent Pinchartbd847482015-01-27 19:12:17 +0200288 #dma-cells = <1>;
289 dma-channels = <15>;
290 };
291
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200292 scifa0: serial@e6c40000 {
Geert Uytterhoeven06930a12016-01-29 10:32:07 +0100293 compatible = "renesas,scifa-r8a7794",
294 "renesas,rcar-gen2-scifa", "renesas,scifa";
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200295 reg = <0 0xe6c40000 0 64>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900296 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200297 clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
Laurent Pinchart1b463bd2016-01-29 10:47:40 +0100298 clock-names = "fck";
Geert Uytterhoeven8233a0d2015-05-20 19:46:27 +0200299 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
300 dma-names = "tx", "rx";
Geert Uytterhoeven60c07452015-08-04 14:28:13 +0200301 power-domains = <&cpg_clocks>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200302 status = "disabled";
303 };
304
305 scifa1: serial@e6c50000 {
Geert Uytterhoeven06930a12016-01-29 10:32:07 +0100306 compatible = "renesas,scifa-r8a7794",
307 "renesas,rcar-gen2-scifa", "renesas,scifa";
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200308 reg = <0 0xe6c50000 0 64>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900309 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200310 clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
Laurent Pinchart1b463bd2016-01-29 10:47:40 +0100311 clock-names = "fck";
Geert Uytterhoeven8233a0d2015-05-20 19:46:27 +0200312 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
313 dma-names = "tx", "rx";
Geert Uytterhoeven60c07452015-08-04 14:28:13 +0200314 power-domains = <&cpg_clocks>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200315 status = "disabled";
316 };
317
318 scifa2: serial@e6c60000 {
Geert Uytterhoeven06930a12016-01-29 10:32:07 +0100319 compatible = "renesas,scifa-r8a7794",
320 "renesas,rcar-gen2-scifa", "renesas,scifa";
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200321 reg = <0 0xe6c60000 0 64>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900322 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200323 clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
Laurent Pinchart1b463bd2016-01-29 10:47:40 +0100324 clock-names = "fck";
Geert Uytterhoeven8233a0d2015-05-20 19:46:27 +0200325 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
326 dma-names = "tx", "rx";
Geert Uytterhoeven60c07452015-08-04 14:28:13 +0200327 power-domains = <&cpg_clocks>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200328 status = "disabled";
329 };
330
331 scifa3: serial@e6c70000 {
Geert Uytterhoeven06930a12016-01-29 10:32:07 +0100332 compatible = "renesas,scifa-r8a7794",
333 "renesas,rcar-gen2-scifa", "renesas,scifa";
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200334 reg = <0 0xe6c70000 0 64>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900335 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200336 clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
Laurent Pinchart1b463bd2016-01-29 10:47:40 +0100337 clock-names = "fck";
Geert Uytterhoeven8233a0d2015-05-20 19:46:27 +0200338 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
339 dma-names = "tx", "rx";
Geert Uytterhoeven60c07452015-08-04 14:28:13 +0200340 power-domains = <&cpg_clocks>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200341 status = "disabled";
342 };
343
344 scifa4: serial@e6c78000 {
Geert Uytterhoeven06930a12016-01-29 10:32:07 +0100345 compatible = "renesas,scifa-r8a7794",
346 "renesas,rcar-gen2-scifa", "renesas,scifa";
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200347 reg = <0 0xe6c78000 0 64>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900348 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200349 clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
Laurent Pinchart1b463bd2016-01-29 10:47:40 +0100350 clock-names = "fck";
Geert Uytterhoeven8233a0d2015-05-20 19:46:27 +0200351 dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
352 dma-names = "tx", "rx";
Geert Uytterhoeven60c07452015-08-04 14:28:13 +0200353 power-domains = <&cpg_clocks>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200354 status = "disabled";
355 };
356
357 scifa5: serial@e6c80000 {
Geert Uytterhoeven06930a12016-01-29 10:32:07 +0100358 compatible = "renesas,scifa-r8a7794",
359 "renesas,rcar-gen2-scifa", "renesas,scifa";
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200360 reg = <0 0xe6c80000 0 64>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900361 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200362 clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
Laurent Pinchart1b463bd2016-01-29 10:47:40 +0100363 clock-names = "fck";
Geert Uytterhoeven8233a0d2015-05-20 19:46:27 +0200364 dmas = <&dmac0 0x23>, <&dmac0 0x24>;
365 dma-names = "tx", "rx";
Geert Uytterhoeven60c07452015-08-04 14:28:13 +0200366 power-domains = <&cpg_clocks>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200367 status = "disabled";
368 };
369
370 scifb0: serial@e6c20000 {
Geert Uytterhoeven06930a12016-01-29 10:32:07 +0100371 compatible = "renesas,scifb-r8a7794",
372 "renesas,rcar-gen2-scifb", "renesas,scifb";
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200373 reg = <0 0xe6c20000 0 64>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900374 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200375 clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
Laurent Pinchart1b463bd2016-01-29 10:47:40 +0100376 clock-names = "fck";
Geert Uytterhoeven8233a0d2015-05-20 19:46:27 +0200377 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
378 dma-names = "tx", "rx";
Geert Uytterhoeven60c07452015-08-04 14:28:13 +0200379 power-domains = <&cpg_clocks>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200380 status = "disabled";
381 };
382
383 scifb1: serial@e6c30000 {
Geert Uytterhoeven06930a12016-01-29 10:32:07 +0100384 compatible = "renesas,scifb-r8a7794",
385 "renesas,rcar-gen2-scifb", "renesas,scifb";
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200386 reg = <0 0xe6c30000 0 64>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900387 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200388 clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
Laurent Pinchart1b463bd2016-01-29 10:47:40 +0100389 clock-names = "fck";
Geert Uytterhoeven8233a0d2015-05-20 19:46:27 +0200390 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
391 dma-names = "tx", "rx";
Geert Uytterhoeven60c07452015-08-04 14:28:13 +0200392 power-domains = <&cpg_clocks>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200393 status = "disabled";
394 };
395
396 scifb2: serial@e6ce0000 {
Geert Uytterhoeven06930a12016-01-29 10:32:07 +0100397 compatible = "renesas,scifb-r8a7794",
398 "renesas,rcar-gen2-scifb", "renesas,scifb";
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200399 reg = <0 0xe6ce0000 0 64>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900400 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200401 clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
Laurent Pinchart1b463bd2016-01-29 10:47:40 +0100402 clock-names = "fck";
Geert Uytterhoeven8233a0d2015-05-20 19:46:27 +0200403 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
404 dma-names = "tx", "rx";
Geert Uytterhoeven60c07452015-08-04 14:28:13 +0200405 power-domains = <&cpg_clocks>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200406 status = "disabled";
407 };
408
409 scif0: serial@e6e60000 {
Geert Uytterhoeven06930a12016-01-29 10:32:07 +0100410 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
411 "renesas,scif";
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200412 reg = <0 0xe6e60000 0 64>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900413 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoevena8644462016-01-29 11:04:42 +0100414 clocks = <&mstp7_clks R8A7794_CLK_SCIF0>, <&zs_clk>,
415 <&scif_clk>;
416 clock-names = "fck", "brg_int", "scif_clk";
Geert Uytterhoeven8233a0d2015-05-20 19:46:27 +0200417 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
418 dma-names = "tx", "rx";
Geert Uytterhoeven60c07452015-08-04 14:28:13 +0200419 power-domains = <&cpg_clocks>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200420 status = "disabled";
421 };
422
423 scif1: serial@e6e68000 {
Geert Uytterhoeven06930a12016-01-29 10:32:07 +0100424 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
425 "renesas,scif";
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200426 reg = <0 0xe6e68000 0 64>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900427 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoevena8644462016-01-29 11:04:42 +0100428 clocks = <&mstp7_clks R8A7794_CLK_SCIF1>, <&zs_clk>,
429 <&scif_clk>;
430 clock-names = "fck", "brg_int", "scif_clk";
Geert Uytterhoeven8233a0d2015-05-20 19:46:27 +0200431 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
432 dma-names = "tx", "rx";
Geert Uytterhoeven60c07452015-08-04 14:28:13 +0200433 power-domains = <&cpg_clocks>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200434 status = "disabled";
435 };
436
437 scif2: serial@e6e58000 {
Geert Uytterhoeven06930a12016-01-29 10:32:07 +0100438 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
439 "renesas,scif";
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200440 reg = <0 0xe6e58000 0 64>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900441 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoevena8644462016-01-29 11:04:42 +0100442 clocks = <&mstp7_clks R8A7794_CLK_SCIF2>, <&zs_clk>,
443 <&scif_clk>;
444 clock-names = "fck", "brg_int", "scif_clk";
Geert Uytterhoeven8233a0d2015-05-20 19:46:27 +0200445 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
446 dma-names = "tx", "rx";
Geert Uytterhoeven60c07452015-08-04 14:28:13 +0200447 power-domains = <&cpg_clocks>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200448 status = "disabled";
449 };
450
451 scif3: serial@e6ea8000 {
Geert Uytterhoeven06930a12016-01-29 10:32:07 +0100452 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
453 "renesas,scif";
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200454 reg = <0 0xe6ea8000 0 64>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900455 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoevena8644462016-01-29 11:04:42 +0100456 clocks = <&mstp7_clks R8A7794_CLK_SCIF3>, <&zs_clk>,
457 <&scif_clk>;
458 clock-names = "fck", "brg_int", "scif_clk";
Geert Uytterhoeven8233a0d2015-05-20 19:46:27 +0200459 dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
460 dma-names = "tx", "rx";
Geert Uytterhoeven60c07452015-08-04 14:28:13 +0200461 power-domains = <&cpg_clocks>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200462 status = "disabled";
463 };
464
465 scif4: serial@e6ee0000 {
Geert Uytterhoeven06930a12016-01-29 10:32:07 +0100466 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
467 "renesas,scif";
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200468 reg = <0 0xe6ee0000 0 64>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900469 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoevena8644462016-01-29 11:04:42 +0100470 clocks = <&mstp7_clks R8A7794_CLK_SCIF4>, <&zs_clk>,
471 <&scif_clk>;
472 clock-names = "fck", "brg_int", "scif_clk";
Geert Uytterhoeven8233a0d2015-05-20 19:46:27 +0200473 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
474 dma-names = "tx", "rx";
Geert Uytterhoeven60c07452015-08-04 14:28:13 +0200475 power-domains = <&cpg_clocks>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200476 status = "disabled";
477 };
478
479 scif5: serial@e6ee8000 {
Geert Uytterhoeven06930a12016-01-29 10:32:07 +0100480 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
481 "renesas,scif";
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200482 reg = <0 0xe6ee8000 0 64>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900483 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoevena8644462016-01-29 11:04:42 +0100484 clocks = <&mstp7_clks R8A7794_CLK_SCIF5>, <&zs_clk>,
485 <&scif_clk>;
486 clock-names = "fck", "brg_int", "scif_clk";
Geert Uytterhoeven8233a0d2015-05-20 19:46:27 +0200487 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
488 dma-names = "tx", "rx";
Geert Uytterhoeven60c07452015-08-04 14:28:13 +0200489 power-domains = <&cpg_clocks>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200490 status = "disabled";
491 };
492
493 hscif0: serial@e62c0000 {
Geert Uytterhoeven06930a12016-01-29 10:32:07 +0100494 compatible = "renesas,hscif-r8a7794",
495 "renesas,rcar-gen2-hscif", "renesas,hscif";
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200496 reg = <0 0xe62c0000 0 96>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900497 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoevena8644462016-01-29 11:04:42 +0100498 clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>, <&zs_clk>,
499 <&scif_clk>;
500 clock-names = "fck", "brg_int", "scif_clk";
Geert Uytterhoeven8233a0d2015-05-20 19:46:27 +0200501 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
502 dma-names = "tx", "rx";
Geert Uytterhoeven60c07452015-08-04 14:28:13 +0200503 power-domains = <&cpg_clocks>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200504 status = "disabled";
505 };
506
507 hscif1: serial@e62c8000 {
Geert Uytterhoeven06930a12016-01-29 10:32:07 +0100508 compatible = "renesas,hscif-r8a7794",
509 "renesas,rcar-gen2-hscif", "renesas,hscif";
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200510 reg = <0 0xe62c8000 0 96>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900511 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoevena8644462016-01-29 11:04:42 +0100512 clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>, <&zs_clk>,
513 <&scif_clk>;
514 clock-names = "fck", "brg_int", "scif_clk";
Geert Uytterhoeven8233a0d2015-05-20 19:46:27 +0200515 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
516 dma-names = "tx", "rx";
Geert Uytterhoeven60c07452015-08-04 14:28:13 +0200517 power-domains = <&cpg_clocks>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200518 status = "disabled";
519 };
520
521 hscif2: serial@e62d0000 {
Geert Uytterhoeven06930a12016-01-29 10:32:07 +0100522 compatible = "renesas,hscif-r8a7794",
523 "renesas,rcar-gen2-hscif", "renesas,hscif";
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200524 reg = <0 0xe62d0000 0 96>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900525 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoevena8644462016-01-29 11:04:42 +0100526 clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>, <&zs_clk>,
527 <&scif_clk>;
528 clock-names = "fck", "brg_int", "scif_clk";
Geert Uytterhoeven8233a0d2015-05-20 19:46:27 +0200529 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
530 dma-names = "tx", "rx";
Geert Uytterhoeven60c07452015-08-04 14:28:13 +0200531 power-domains = <&cpg_clocks>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200532 status = "disabled";
533 };
534
Laurent Pinchart82818d32015-01-27 10:45:55 +0200535 ether: ethernet@ee700000 {
536 compatible = "renesas,ether-r8a7794";
537 reg = <0 0xee700000 0 0x400>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900538 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart82818d32015-01-27 10:45:55 +0200539 clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
Geert Uytterhoeven60c07452015-08-04 14:28:13 +0200540 power-domains = <&cpg_clocks>;
Laurent Pinchart82818d32015-01-27 10:45:55 +0200541 phy-mode = "rmii";
542 #address-cells = <1>;
543 #size-cells = <0>;
544 status = "disabled";
545 };
546
Sergei Shtylyov89aac8a2016-02-17 23:45:10 +0300547 avb: ethernet@e6800000 {
548 compatible = "renesas,etheravb-r8a7794",
549 "renesas,etheravb-rcar-gen2";
550 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
551 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
552 clocks = <&mstp8_clks R8A7794_CLK_ETHERAVB>;
553 power-domains = <&cpg_clocks>;
554 #address-cells = <1>;
555 #size-cells = <0>;
556 status = "disabled";
557 };
558
Sergei Shtylyov54285212015-08-20 01:00:09 +0300559 /* The memory map in the User's Manual maps the cores to bus numbers */
560 i2c0: i2c@e6508000 {
561 compatible = "renesas,i2c-r8a7794";
562 reg = <0 0xe6508000 0 0x40>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900563 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyov54285212015-08-20 01:00:09 +0300564 clocks = <&mstp9_clks R8A7794_CLK_I2C0>;
565 power-domains = <&cpg_clocks>;
566 #address-cells = <1>;
567 #size-cells = <0>;
Wolfram Sang691cd0a2015-12-08 10:37:52 +0100568 i2c-scl-internal-delay-ns = <6>;
Sergei Shtylyov54285212015-08-20 01:00:09 +0300569 status = "disabled";
570 };
571
572 i2c1: i2c@e6518000 {
573 compatible = "renesas,i2c-r8a7794";
574 reg = <0 0xe6518000 0 0x40>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900575 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyov54285212015-08-20 01:00:09 +0300576 clocks = <&mstp9_clks R8A7794_CLK_I2C1>;
577 power-domains = <&cpg_clocks>;
578 #address-cells = <1>;
579 #size-cells = <0>;
Wolfram Sang691cd0a2015-12-08 10:37:52 +0100580 i2c-scl-internal-delay-ns = <6>;
Sergei Shtylyov54285212015-08-20 01:00:09 +0300581 status = "disabled";
582 };
583
584 i2c2: i2c@e6530000 {
585 compatible = "renesas,i2c-r8a7794";
586 reg = <0 0xe6530000 0 0x40>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900587 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyov54285212015-08-20 01:00:09 +0300588 clocks = <&mstp9_clks R8A7794_CLK_I2C2>;
589 power-domains = <&cpg_clocks>;
590 #address-cells = <1>;
591 #size-cells = <0>;
Wolfram Sang691cd0a2015-12-08 10:37:52 +0100592 i2c-scl-internal-delay-ns = <6>;
Sergei Shtylyov54285212015-08-20 01:00:09 +0300593 status = "disabled";
594 };
595
596 i2c3: i2c@e6540000 {
597 compatible = "renesas,i2c-r8a7794";
598 reg = <0 0xe6540000 0 0x40>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900599 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyov54285212015-08-20 01:00:09 +0300600 clocks = <&mstp9_clks R8A7794_CLK_I2C3>;
601 power-domains = <&cpg_clocks>;
602 #address-cells = <1>;
603 #size-cells = <0>;
Wolfram Sang691cd0a2015-12-08 10:37:52 +0100604 i2c-scl-internal-delay-ns = <6>;
Sergei Shtylyov54285212015-08-20 01:00:09 +0300605 status = "disabled";
606 };
607
608 i2c4: i2c@e6520000 {
609 compatible = "renesas,i2c-r8a7794";
610 reg = <0 0xe6520000 0 0x40>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900611 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyov54285212015-08-20 01:00:09 +0300612 clocks = <&mstp9_clks R8A7794_CLK_I2C4>;
613 power-domains = <&cpg_clocks>;
614 #address-cells = <1>;
615 #size-cells = <0>;
Wolfram Sang691cd0a2015-12-08 10:37:52 +0100616 i2c-scl-internal-delay-ns = <6>;
Sergei Shtylyov54285212015-08-20 01:00:09 +0300617 status = "disabled";
618 };
619
620 i2c5: i2c@e6528000 {
621 compatible = "renesas,i2c-r8a7794";
622 reg = <0 0xe6528000 0 0x40>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900623 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyov54285212015-08-20 01:00:09 +0300624 clocks = <&mstp9_clks R8A7794_CLK_I2C5>;
625 power-domains = <&cpg_clocks>;
626 #address-cells = <1>;
627 #size-cells = <0>;
Wolfram Sang691cd0a2015-12-08 10:37:52 +0100628 i2c-scl-internal-delay-ns = <6>;
Sergei Shtylyov54285212015-08-20 01:00:09 +0300629 status = "disabled";
630 };
631
Sergei Shtylyov6cdf6ba2015-07-31 00:54:05 +0300632 mmcif0: mmc@ee200000 {
633 compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif";
634 reg = <0 0xee200000 0 0x80>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900635 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyov6cdf6ba2015-07-31 00:54:05 +0300636 clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>;
637 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
638 dma-names = "tx", "rx";
Geert Uytterhoeven60c07452015-08-04 14:28:13 +0200639 power-domains = <&cpg_clocks>;
Sergei Shtylyov6cdf6ba2015-07-31 00:54:05 +0300640 reg-io-width = <4>;
641 status = "disabled";
642 };
643
Sergei Shtylyovb8e8ea12015-02-22 01:26:37 +0300644 sdhi0: sd@ee100000 {
645 compatible = "renesas,sdhi-r8a7794";
646 reg = <0 0xee100000 0 0x200>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900647 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyovb8e8ea12015-02-22 01:26:37 +0300648 clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
Geert Uytterhoeven60c07452015-08-04 14:28:13 +0200649 power-domains = <&cpg_clocks>;
Sergei Shtylyovb8e8ea12015-02-22 01:26:37 +0300650 status = "disabled";
651 };
652
653 sdhi1: sd@ee140000 {
654 compatible = "renesas,sdhi-r8a7794";
655 reg = <0 0xee140000 0 0x100>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900656 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyovb8e8ea12015-02-22 01:26:37 +0300657 clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
Geert Uytterhoeven60c07452015-08-04 14:28:13 +0200658 power-domains = <&cpg_clocks>;
Sergei Shtylyovb8e8ea12015-02-22 01:26:37 +0300659 status = "disabled";
660 };
661
662 sdhi2: sd@ee160000 {
663 compatible = "renesas,sdhi-r8a7794";
664 reg = <0 0xee160000 0 0x100>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900665 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyovb8e8ea12015-02-22 01:26:37 +0300666 clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
Geert Uytterhoeven60c07452015-08-04 14:28:13 +0200667 power-domains = <&cpg_clocks>;
Sergei Shtylyovb8e8ea12015-02-22 01:26:37 +0300668 status = "disabled";
669 };
670
Sergei Shtylyov740b4a92015-08-11 00:59:24 +0300671 qspi: spi@e6b10000 {
672 compatible = "renesas,qspi-r8a7794", "renesas,qspi";
673 reg = <0 0xe6b10000 0 0x2c>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900674 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyov740b4a92015-08-11 00:59:24 +0300675 clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>;
676 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
677 dma-names = "tx", "rx";
678 power-domains = <&cpg_clocks>;
679 num-cs = <1>;
680 #address-cells = <1>;
681 #size-cells = <0>;
682 status = "disabled";
683 };
684
Sergei Shtylyov1afe77c2015-08-20 01:22:24 +0300685 vin0: video@e6ef0000 {
686 compatible = "renesas,vin-r8a7794";
687 reg = <0 0xe6ef0000 0 0x1000>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900688 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyov1afe77c2015-08-20 01:22:24 +0300689 clocks = <&mstp8_clks R8A7794_CLK_VIN0>;
690 power-domains = <&cpg_clocks>;
691 status = "disabled";
692 };
693
694 vin1: video@e6ef1000 {
695 compatible = "renesas,vin-r8a7794";
696 reg = <0 0xe6ef1000 0 0x1000>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900697 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyov1afe77c2015-08-20 01:22:24 +0300698 clocks = <&mstp8_clks R8A7794_CLK_VIN1>;
699 power-domains = <&cpg_clocks>;
700 status = "disabled";
701 };
702
Sergei Shtylyova6a130b2015-09-13 01:30:05 +0300703 pci0: pci@ee090000 {
Simon Hormanc99fbe62015-12-18 11:42:39 +0900704 compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
Sergei Shtylyova6a130b2015-09-13 01:30:05 +0300705 device_type = "pci";
706 reg = <0 0xee090000 0 0xc00>,
707 <0 0xee080000 0 0x1100>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900708 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyova6a130b2015-09-13 01:30:05 +0300709 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
710 power-domains = <&cpg_clocks>;
711 status = "disabled";
712
713 bus-range = <0 0>;
714 #address-cells = <3>;
715 #size-cells = <2>;
716 #interrupt-cells = <1>;
717 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
718 interrupt-map-mask = <0xff00 0 0 0x7>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900719 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
720 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
721 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyov45cb0bd2015-09-13 02:00:19 +0300722
723 usb@0,1 {
724 reg = <0x800 0 0 0 0>;
725 device_type = "pci";
726 phys = <&usb0 0>;
727 phy-names = "usb";
728 };
729
730 usb@0,2 {
731 reg = <0x1000 0 0 0 0>;
732 device_type = "pci";
733 phys = <&usb0 0>;
734 phy-names = "usb";
735 };
Sergei Shtylyova6a130b2015-09-13 01:30:05 +0300736 };
737
738 pci1: pci@ee0d0000 {
Simon Hormanc99fbe62015-12-18 11:42:39 +0900739 compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
Sergei Shtylyova6a130b2015-09-13 01:30:05 +0300740 device_type = "pci";
741 reg = <0 0xee0d0000 0 0xc00>,
742 <0 0xee0c0000 0 0x1100>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900743 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyova6a130b2015-09-13 01:30:05 +0300744 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
745 power-domains = <&cpg_clocks>;
746 status = "disabled";
747
748 bus-range = <1 1>;
749 #address-cells = <3>;
750 #size-cells = <2>;
751 #interrupt-cells = <1>;
752 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
753 interrupt-map-mask = <0xff00 0 0 0x7>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900754 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
755 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
756 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyov45cb0bd2015-09-13 02:00:19 +0300757
758 usb@0,1 {
759 reg = <0x800 0 0 0 0>;
760 device_type = "pci";
761 phys = <&usb2 0>;
762 phy-names = "usb";
763 };
764
765 usb@0,2 {
766 reg = <0x1000 0 0 0 0>;
767 device_type = "pci";
768 phys = <&usb2 0>;
769 phy-names = "usb";
770 };
Sergei Shtylyova6a130b2015-09-13 01:30:05 +0300771 };
772
Sergei Shtylyov2f33b9f2015-09-17 02:53:58 +0300773 hsusb: usb@e6590000 {
Simon Horman1472ffa2015-12-08 14:24:50 +0900774 compatible = "renesas,usbhs-r8a7794", "renesas,rcar-gen2-usbhs";
Sergei Shtylyov2f33b9f2015-09-17 02:53:58 +0300775 reg = <0 0xe6590000 0 0x100>;
Simon Horman8d47e6a2016-01-18 14:18:44 +0900776 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyov2f33b9f2015-09-17 02:53:58 +0300777 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
778 power-domains = <&cpg_clocks>;
779 renesas,buswait = <4>;
780 phys = <&usb0 1>;
781 phy-names = "usb";
782 status = "disabled";
783 };
784
Sergei Shtylyov74ef4572015-10-02 01:05:12 +0300785 usbphy: usb-phy@e6590100 {
786 compatible = "renesas,usb-phy-r8a7794";
787 reg = <0 0xe6590100 0 0x100>;
788 #address-cells = <1>;
789 #size-cells = <0>;
790 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
791 clock-names = "usbhs";
792 power-domains = <&cpg_clocks>;
793 status = "disabled";
794
795 usb0: usb-channel@0 {
796 reg = <0>;
797 #phy-cells = <1>;
798 };
799 usb2: usb-channel@2 {
800 reg = <2>;
801 #phy-cells = <1>;
802 };
803 };
804
Laurent Pinchart46c4f132015-11-16 17:57:20 +0900805 du: display@feb00000 {
806 compatible = "renesas,du-r8a7794";
807 reg = <0 0xfeb00000 0 0x40000>;
808 reg-names = "du";
Simon Horman8d47e6a2016-01-18 14:18:44 +0900809 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
810 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart46c4f132015-11-16 17:57:20 +0900811 clocks = <&mstp7_clks R8A7794_CLK_DU0>,
812 <&mstp7_clks R8A7794_CLK_DU0>;
813 clock-names = "du.0", "du.1";
814 status = "disabled";
815
816 ports {
817 #address-cells = <1>;
818 #size-cells = <0>;
819
820 port@0 {
821 reg = <0>;
822 du_out_rgb0: endpoint {
823 };
824 };
825 port@1 {
826 reg = <1>;
827 du_out_rgb1: endpoint {
828 };
829 };
830 };
831 };
832
Simon Horman9f1c1a22016-03-15 09:26:34 +0900833 can0: can@e6e80000 {
834 compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
835 reg = <0 0xe6e80000 0 0x1000>;
836 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
837 clocks = <&mstp9_clks R8A7794_CLK_RCAN0>,
838 <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
839 clock-names = "clkp1", "clkp2", "can_clk";
840 power-domains = <&cpg_clocks>;
841 status = "disabled";
842 };
843
844 can1: can@e6e88000 {
845 compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
846 reg = <0 0xe6e88000 0 0x1000>;
847 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
848 clocks = <&mstp9_clks R8A7794_CLK_RCAN1>,
849 <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
850 clock-names = "clkp1", "clkp2", "can_clk";
851 power-domains = <&cpg_clocks>;
852 status = "disabled";
853 };
854
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200855 clocks {
856 #address-cells = <2>;
857 #size-cells = <2>;
858 ranges;
859
860 /* External root clock */
Simon Horman337f6be2016-03-18 08:17:57 +0900861 extal_clk: extal {
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200862 compatible = "fixed-clock";
863 #clock-cells = <0>;
864 /* This value must be overriden by the board. */
865 clock-frequency = <0>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200866 };
867
Simon Hormane980f942016-03-15 09:26:33 +0900868 /* External USB clock - can be overridden by the board */
869 usb_extal_clk: usb_extal {
870 compatible = "fixed-clock";
871 #clock-cells = <0>;
872 clock-frequency = <48000000>;
873 };
874
875 /* External CAN clock */
876 can_clk: can {
877 compatible = "fixed-clock";
878 #clock-cells = <0>;
879 /* This value must be overridden by the board. */
880 clock-frequency = <0>;
881 status = "disabled";
882 };
883
Geert Uytterhoevena8644462016-01-29 11:04:42 +0100884 /* External SCIF clock */
885 scif_clk: scif {
886 compatible = "fixed-clock";
887 #clock-cells = <0>;
888 /* This value must be overridden by the board. */
889 clock-frequency = <0>;
890 status = "disabled";
891 };
892
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200893 /* Special CPG clocks */
894 cpg_clocks: cpg_clocks@e6150000 {
895 compatible = "renesas,r8a7794-cpg-clocks",
896 "renesas,rcar-gen2-cpg-clocks";
897 reg = <0 0xe6150000 0 0x1000>;
Simon Hormane980f942016-03-15 09:26:33 +0900898 clocks = <&extal_clk &usb_extal_clk>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200899 #clock-cells = <1>;
900 clock-output-names = "main", "pll0", "pll1", "pll3",
Simon Hormane980f942016-03-15 09:26:33 +0900901 "lb", "qspi", "sdh", "sd0", "z",
902 "rcan";
Geert Uytterhoeven60c07452015-08-04 14:28:13 +0200903 #power-domain-cells = <0>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200904 };
Shinobu Uehara8e181632014-05-23 11:37:45 +0900905 /* Variable factor clocks */
Simon Horman337f6be2016-03-18 08:17:57 +0900906 sd2_clk: sd2@e6150078 {
Shinobu Uehara8e181632014-05-23 11:37:45 +0900907 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
908 reg = <0 0xe6150078 0 4>;
909 clocks = <&pll1_div2_clk>;
910 #clock-cells = <0>;
Shinobu Uehara8e181632014-05-23 11:37:45 +0900911 };
Simon Horman337f6be2016-03-18 08:17:57 +0900912 sd3_clk: sd3@e615026c {
Shinobu Uehara8e181632014-05-23 11:37:45 +0900913 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
Simon Horman5e7e1552015-01-05 09:40:49 +0900914 reg = <0 0xe615026c 0 4>;
Shinobu Uehara8e181632014-05-23 11:37:45 +0900915 clocks = <&pll1_div2_clk>;
916 #clock-cells = <0>;
Shinobu Uehara8e181632014-05-23 11:37:45 +0900917 };
Simon Horman337f6be2016-03-18 08:17:57 +0900918 mmc0_clk: mmc0@e6150240 {
Shinobu Ueharadeac1502014-05-27 10:39:26 +0900919 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
920 reg = <0 0xe6150240 0 4>;
921 clocks = <&pll1_div2_clk>;
922 #clock-cells = <0>;
Shinobu Ueharadeac1502014-05-27 10:39:26 +0900923 };
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200924
925 /* Fixed factor clocks */
Simon Horman337f6be2016-03-18 08:17:57 +0900926 pll1_div2_clk: pll1_div2 {
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200927 compatible = "fixed-factor-clock";
928 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
929 #clock-cells = <0>;
930 clock-div = <2>;
931 clock-mult = <1>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200932 };
Simon Horman337f6be2016-03-18 08:17:57 +0900933 zg_clk: zg {
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200934 compatible = "fixed-factor-clock";
935 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
936 #clock-cells = <0>;
937 clock-div = <6>;
938 clock-mult = <1>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200939 };
Simon Horman337f6be2016-03-18 08:17:57 +0900940 zx_clk: zx {
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200941 compatible = "fixed-factor-clock";
942 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
943 #clock-cells = <0>;
944 clock-div = <3>;
945 clock-mult = <1>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200946 };
Simon Horman337f6be2016-03-18 08:17:57 +0900947 zs_clk: zs {
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200948 compatible = "fixed-factor-clock";
949 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
950 #clock-cells = <0>;
951 clock-div = <6>;
952 clock-mult = <1>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200953 };
Simon Horman337f6be2016-03-18 08:17:57 +0900954 hp_clk: hp {
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200955 compatible = "fixed-factor-clock";
956 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
957 #clock-cells = <0>;
958 clock-div = <12>;
959 clock-mult = <1>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200960 };
Simon Horman337f6be2016-03-18 08:17:57 +0900961 i_clk: i {
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200962 compatible = "fixed-factor-clock";
963 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
964 #clock-cells = <0>;
965 clock-div = <2>;
966 clock-mult = <1>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200967 };
Simon Horman337f6be2016-03-18 08:17:57 +0900968 b_clk: b {
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200969 compatible = "fixed-factor-clock";
970 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
971 #clock-cells = <0>;
972 clock-div = <12>;
973 clock-mult = <1>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200974 };
Simon Horman337f6be2016-03-18 08:17:57 +0900975 p_clk: p {
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200976 compatible = "fixed-factor-clock";
977 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
978 #clock-cells = <0>;
979 clock-div = <24>;
980 clock-mult = <1>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200981 };
Simon Horman337f6be2016-03-18 08:17:57 +0900982 cl_clk: cl {
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200983 compatible = "fixed-factor-clock";
984 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
985 #clock-cells = <0>;
986 clock-div = <48>;
987 clock-mult = <1>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200988 };
Simon Horman337f6be2016-03-18 08:17:57 +0900989 m2_clk: m2 {
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200990 compatible = "fixed-factor-clock";
991 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
992 #clock-cells = <0>;
993 clock-div = <8>;
994 clock-mult = <1>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200995 };
Simon Horman337f6be2016-03-18 08:17:57 +0900996 rclk_clk: rclk {
Ulrich Hecht0dce5452014-09-05 12:23:48 +0200997 compatible = "fixed-factor-clock";
998 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
999 #clock-cells = <0>;
1000 clock-div = <(48 * 1024)>;
1001 clock-mult = <1>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001002 };
Simon Horman337f6be2016-03-18 08:17:57 +09001003 oscclk_clk: oscclk {
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001004 compatible = "fixed-factor-clock";
1005 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1006 #clock-cells = <0>;
1007 clock-div = <(12 * 1024)>;
1008 clock-mult = <1>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001009 };
Simon Horman337f6be2016-03-18 08:17:57 +09001010 zb3_clk: zb3 {
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001011 compatible = "fixed-factor-clock";
1012 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
1013 #clock-cells = <0>;
1014 clock-div = <4>;
1015 clock-mult = <1>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001016 };
Simon Horman337f6be2016-03-18 08:17:57 +09001017 zb3d2_clk: zb3d2 {
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001018 compatible = "fixed-factor-clock";
1019 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
1020 #clock-cells = <0>;
1021 clock-div = <8>;
1022 clock-mult = <1>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001023 };
Simon Horman337f6be2016-03-18 08:17:57 +09001024 ddr_clk: ddr {
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001025 compatible = "fixed-factor-clock";
1026 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
1027 #clock-cells = <0>;
1028 clock-div = <8>;
1029 clock-mult = <1>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001030 };
Simon Horman337f6be2016-03-18 08:17:57 +09001031 mp_clk: mp {
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001032 compatible = "fixed-factor-clock";
1033 clocks = <&pll1_div2_clk>;
1034 #clock-cells = <0>;
1035 clock-div = <15>;
1036 clock-mult = <1>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001037 };
Simon Horman337f6be2016-03-18 08:17:57 +09001038 cp_clk: cp {
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001039 compatible = "fixed-factor-clock";
1040 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1041 #clock-cells = <0>;
1042 clock-div = <48>;
1043 clock-mult = <1>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001044 };
1045
Simon Horman337f6be2016-03-18 08:17:57 +09001046 acp_clk: acp {
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001047 compatible = "fixed-factor-clock";
1048 clocks = <&extal_clk>;
1049 #clock-cells = <0>;
1050 clock-div = <2>;
1051 clock-mult = <1>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001052 };
1053
1054 /* Gate clocks */
1055 mstp0_clks: mstp0_clks@e6150130 {
1056 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1057 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1058 clocks = <&mp_clk>;
1059 #clock-cells = <1>;
Geert Uytterhoeven1045d062014-11-10 19:49:39 +01001060 clock-indices = <R8A7794_CLK_MSIOF0>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001061 clock-output-names = "msiof0";
1062 };
1063 mstp1_clks: mstp1_clks@e6150134 {
1064 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1065 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
Yoshifumi Hosoyadc3cf932014-11-12 17:55:57 +09001066 clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>,
1067 <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
1068 <&zs_clk>, <&zs_clk>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001069 #clock-cells = <1>;
Geert Uytterhoeven1045d062014-11-10 19:49:39 +01001070 clock-indices = <
Yoshifumi Hosoyadc3cf932014-11-12 17:55:57 +09001071 R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
1072 R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
1073 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
1074 R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001075 >;
1076 clock-output-names =
Yoshifumi Hosoyadc3cf932014-11-12 17:55:57 +09001077 "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0",
1078 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps";
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001079 };
1080 mstp2_clks: mstp2_clks@e6150138 {
1081 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1082 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1083 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
Hiroyuki Yokoyamabe16cd32014-12-10 10:21:12 +09001084 <&mp_clk>, <&mp_clk>, <&mp_clk>,
1085 <&zs_clk>, <&zs_clk>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001086 #clock-cells = <1>;
Geert Uytterhoeven1045d062014-11-10 19:49:39 +01001087 clock-indices = <
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001088 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
1089 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
1090 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
Hiroyuki Yokoyamabe16cd32014-12-10 10:21:12 +09001091 R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001092 >;
1093 clock-output-names =
1094 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
Hiroyuki Yokoyamabe16cd32014-12-10 10:21:12 +09001095 "scifb1", "msiof1", "scifb2",
1096 "sys-dmac1", "sys-dmac0";
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001097 };
1098 mstp3_clks: mstp3_clks@e615013c {
1099 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1100 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
Simon Horman5e7e1552015-01-05 09:40:49 +09001101 clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
Simon Hormana856b192016-03-17 16:33:10 +09001102 <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>,
1103 <&hp_clk>, <&hp_clk>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001104 #clock-cells = <1>;
Geert Uytterhoeven1045d062014-11-10 19:49:39 +01001105 clock-indices = <
Shinobu Uehara8e181632014-05-23 11:37:45 +09001106 R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
Simon Hormana856b192016-03-17 16:33:10 +09001107 R8A7794_CLK_MMCIF0 R8A7794_CLK_IIC0
1108 R8A7794_CLK_IIC1 R8A7794_CLK_CMT1
Shinobu Ueharadeac1502014-05-27 10:39:26 +09001109 R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001110 >;
1111 clock-output-names =
Shinobu Uehara8e181632014-05-23 11:37:45 +09001112 "sdhi2", "sdhi1", "sdhi0",
Simon Hormana856b192016-03-17 16:33:10 +09001113 "mmcif0", "i2c6", "i2c7",
1114 "cmt1", "usbdmac0", "usbdmac1";
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001115 };
Geert Uytterhoeven1c5ca5d2015-03-18 19:56:01 +01001116 mstp4_clks: mstp4_clks@e6150140 {
1117 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1118 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1119 clocks = <&cp_clk>;
1120 #clock-cells = <1>;
1121 clock-indices = <R8A7794_CLK_IRQC>;
1122 clock-output-names = "irqc";
1123 };
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001124 mstp7_clks: mstp7_clks@e615014c {
1125 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1126 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
Shinobu Ueharac7bab9f2014-12-05 12:01:12 +09001127 clocks = <&mp_clk>, <&mp_clk>,
1128 <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
Laurent Pinchart9859cd32015-11-16 17:57:11 +09001129 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1130 <&zx_clk>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001131 #clock-cells = <1>;
Geert Uytterhoeven1045d062014-11-10 19:49:39 +01001132 clock-indices = <
Shinobu Ueharac7bab9f2014-12-05 12:01:12 +09001133 R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001134 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
1135 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
1136 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
Laurent Pinchart9859cd32015-11-16 17:57:11 +09001137 R8A7794_CLK_SCIF0 R8A7794_CLK_DU0
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001138 >;
1139 clock-output-names =
Shinobu Ueharac7bab9f2014-12-05 12:01:12 +09001140 "ehci", "hsusb",
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001141 "hscif2", "scif5", "scif4", "hscif1", "hscif0",
Laurent Pinchart9859cd32015-11-16 17:57:11 +09001142 "scif3", "scif2", "scif1", "scif0", "du0";
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001143 };
1144 mstp8_clks: mstp8_clks@e6150990 {
1145 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1146 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
Sergei Shtylyov255a4042016-02-17 23:43:41 +03001147 clocks = <&zg_clk>, <&zg_clk>, <&hp_clk>, <&p_clk>;
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001148 #clock-cells = <1>;
Geert Uytterhoeven1045d062014-11-10 19:49:39 +01001149 clock-indices = <
Sergei Shtylyov255a4042016-02-17 23:43:41 +03001150 R8A7794_CLK_VIN1 R8A7794_CLK_VIN0
1151 R8A7794_CLK_ETHERAVB R8A7794_CLK_ETHER
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001152 >;
1153 clock-output-names =
Sergei Shtylyov255a4042016-02-17 23:43:41 +03001154 "vin1", "vin0", "etheravb", "ether";
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001155 };
Hisashi Nakamura32814802014-12-11 12:21:14 +09001156 mstp9_clks: mstp9_clks@e6150994 {
1157 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1158 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
Sergei Shtylyov3f37e012015-08-09 01:08:21 +03001159 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
Simon Hormane980f942016-03-15 09:26:33 +09001160 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&p_clk>,
1161 <&p_clk>, <&cpg_clocks R8A7794_CLK_QSPI>,
1162 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1163 <&hp_clk>, <&hp_clk>;
Hisashi Nakamura32814802014-12-11 12:21:14 +09001164 #clock-cells = <1>;
Sergei Shtylyov3f37e012015-08-09 01:08:21 +03001165 clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5
1166 R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3
1167 R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1
Simon Hormane980f942016-03-15 09:26:33 +09001168 R8A7794_CLK_GPIO0 R8A7794_CLK_RCAN1
1169 R8A7794_CLK_RCAN0 R8A7794_CLK_QSPI_MOD
Sergei Shtylyov3f37e012015-08-09 01:08:21 +03001170 R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
1171 R8A7794_CLK_I2C3 R8A7794_CLK_I2C2
1172 R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>;
Koji Matsuokac5d82c92014-05-23 18:37:04 +09001173 clock-output-names =
Sergei Shtylyov3f37e012015-08-09 01:08:21 +03001174 "gpio6", "gpio5", "gpio4", "gpio3", "gpio2",
Simon Hormane980f942016-03-15 09:26:33 +09001175 "gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod",
Sergei Shtylyov3f37e012015-08-09 01:08:21 +03001176 "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
Hisashi Nakamura32814802014-12-11 12:21:14 +09001177 };
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001178 mstp11_clks: mstp11_clks@e615099c {
1179 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1180 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1181 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1182 #clock-cells = <1>;
Geert Uytterhoeven1045d062014-11-10 19:49:39 +01001183 clock-indices = <
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001184 R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
1185 >;
1186 clock-output-names = "scifa3", "scifa4", "scifa5";
1187 };
1188 };
Laurent Pinchart1cb27942015-01-27 11:13:25 +02001189
1190 ipmmu_sy0: mmu@e6280000 {
Magnus Damm0da4cfd2015-11-17 13:31:22 +09001191 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
Laurent Pinchart1cb27942015-01-27 11:13:25 +02001192 reg = <0 0xe6280000 0 0x1000>;
Simon Horman8d47e6a2016-01-18 14:18:44 +09001193 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1194 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart1cb27942015-01-27 11:13:25 +02001195 #iommu-cells = <1>;
1196 status = "disabled";
1197 };
1198
1199 ipmmu_sy1: mmu@e6290000 {
Magnus Damm0da4cfd2015-11-17 13:31:22 +09001200 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
Laurent Pinchart1cb27942015-01-27 11:13:25 +02001201 reg = <0 0xe6290000 0 0x1000>;
Simon Horman8d47e6a2016-01-18 14:18:44 +09001202 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart1cb27942015-01-27 11:13:25 +02001203 #iommu-cells = <1>;
1204 status = "disabled";
1205 };
1206
1207 ipmmu_ds: mmu@e6740000 {
Magnus Damm0da4cfd2015-11-17 13:31:22 +09001208 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
Laurent Pinchart1cb27942015-01-27 11:13:25 +02001209 reg = <0 0xe6740000 0 0x1000>;
Simon Horman8d47e6a2016-01-18 14:18:44 +09001210 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1211 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart1cb27942015-01-27 11:13:25 +02001212 #iommu-cells = <1>;
Magnus Damm832d3e42015-10-18 14:26:56 +09001213 status = "disabled";
Laurent Pinchart1cb27942015-01-27 11:13:25 +02001214 };
1215
1216 ipmmu_mp: mmu@ec680000 {
Magnus Damm0da4cfd2015-11-17 13:31:22 +09001217 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
Laurent Pinchart1cb27942015-01-27 11:13:25 +02001218 reg = <0 0xec680000 0 0x1000>;
Simon Horman8d47e6a2016-01-18 14:18:44 +09001219 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart1cb27942015-01-27 11:13:25 +02001220 #iommu-cells = <1>;
1221 status = "disabled";
1222 };
1223
1224 ipmmu_mx: mmu@fe951000 {
Magnus Damm0da4cfd2015-11-17 13:31:22 +09001225 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
Laurent Pinchart1cb27942015-01-27 11:13:25 +02001226 reg = <0 0xfe951000 0 0x1000>;
Simon Horman8d47e6a2016-01-18 14:18:44 +09001227 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1228 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart1cb27942015-01-27 11:13:25 +02001229 #iommu-cells = <1>;
Magnus Damm832d3e42015-10-18 14:26:56 +09001230 status = "disabled";
Laurent Pinchart1cb27942015-01-27 11:13:25 +02001231 };
1232
1233 ipmmu_gp: mmu@e62a0000 {
Magnus Damm0da4cfd2015-11-17 13:31:22 +09001234 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
Laurent Pinchart1cb27942015-01-27 11:13:25 +02001235 reg = <0 0xe62a0000 0 0x1000>;
Simon Horman8d47e6a2016-01-18 14:18:44 +09001236 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1237 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart1cb27942015-01-27 11:13:25 +02001238 #iommu-cells = <1>;
1239 status = "disabled";
1240 };
Ulrich Hecht0dce5452014-09-05 12:23:48 +02001241};