| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 1 | /* |
| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 2 | * Copyright (C) 2003-2005 SAN People |
| 3 | * |
| 4 | * Debugging macro include header |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | */ |
| 11 | |
| Jean-Christophe PLAGNIOL-VILLARD | 13079a7 | 2011-11-02 01:43:31 +0800 | [diff] [blame] | 12 | #if defined(CONFIG_AT91_DEBUG_LL_DBGU0) |
| Alexandre Belloni | 5f58c97 | 2015-01-12 19:42:14 +0100 | [diff] [blame] | 13 | #define AT91_DBGU 0xfffff200 /* AT91_BASE_DBGU0 */ |
| Nicolas Ferre | 726d32b | 2014-09-15 18:15:55 +0200 | [diff] [blame] | 14 | #elif defined(CONFIG_AT91_DEBUG_LL_DBGU1) |
| Alexandre Belloni | 5f58c97 | 2015-01-12 19:42:14 +0100 | [diff] [blame] | 15 | #define AT91_DBGU 0xffffee00 /* AT91_BASE_DBGU1 */ |
| Nicolas Ferre | c268a74 | 2015-07-30 19:12:12 +0200 | [diff] [blame] | 16 | #elif defined(CONFIG_AT91_DEBUG_LL_DBGU2) |
| Nicolas Ferre | 726d32b | 2014-09-15 18:15:55 +0200 | [diff] [blame] | 17 | /* On sama5d4, use USART3 as low level serial console */ |
| Alexandre Belloni | 5f58c97 | 2015-01-12 19:42:14 +0100 | [diff] [blame] | 18 | #define AT91_DBGU 0xfc00c000 /* SAMA5D4_BASE_USART3 */ |
| Nicolas Ferre | c268a74 | 2015-07-30 19:12:12 +0200 | [diff] [blame] | 19 | #else |
| 20 | /* On sama5d2, use UART1 as low level serial console */ |
| 21 | #define AT91_DBGU 0xf8020000 |
| Jean-Christophe PLAGNIOL-VILLARD | 13079a7 | 2011-11-02 01:43:31 +0800 | [diff] [blame] | 22 | #endif |
| 23 | |
| Alexandre Belloni | 5a5a645 | 2015-03-04 15:41:27 +0100 | [diff] [blame] | 24 | #ifdef CONFIG_MMU |
| Alexandre Belloni | 5f58c97 | 2015-01-12 19:42:14 +0100 | [diff] [blame] | 25 | #define AT91_IO_P2V(x) ((x) - 0x01000000) |
| Alexandre Belloni | 5a5a645 | 2015-03-04 15:41:27 +0100 | [diff] [blame] | 26 | #else |
| 27 | #define AT91_IO_P2V(x) (x) |
| 28 | #endif |
| Alexandre Belloni | 5f58c97 | 2015-01-12 19:42:14 +0100 | [diff] [blame] | 29 | |
| 30 | #define AT91_DBGU_SR (0x14) /* Status Register */ |
| 31 | #define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */ |
| 32 | #define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */ |
| 33 | #define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */ |
| 34 | |
| Nicolas Pitre | 639da5e | 2011-08-31 22:55:46 -0400 | [diff] [blame] | 35 | .macro addruart, rp, rv, tmp |
| Jean-Christophe PLAGNIOL-VILLARD | 13079a7 | 2011-11-02 01:43:31 +0800 | [diff] [blame] | 36 | ldr \rp, =AT91_DBGU @ System peripherals (phys address) |
| 37 | ldr \rv, =AT91_IO_P2V(AT91_DBGU) @ System peripherals (virt address) |
| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 38 | .endm |
| 39 | |
| 40 | .macro senduart,rd,rx |
| Jean-Christophe PLAGNIOL-VILLARD | 1ff5b1b | 2011-05-03 01:11:25 +0800 | [diff] [blame] | 41 | strb \rd, [\rx, #(AT91_DBGU_THR)] @ Write to Transmitter Holding Register |
| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 42 | .endm |
| 43 | |
| 44 | .macro waituart,rd,rx |
| Jean-Christophe PLAGNIOL-VILLARD | 1ff5b1b | 2011-05-03 01:11:25 +0800 | [diff] [blame] | 45 | 1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register |
| 46 | tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit |
| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 47 | beq 1001b |
| 48 | .endm |
| 49 | |
| 50 | .macro busyuart,rd,rx |
| Jean-Christophe PLAGNIOL-VILLARD | 1ff5b1b | 2011-05-03 01:11:25 +0800 | [diff] [blame] | 51 | 1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register |
| 52 | tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete |
| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 53 | beq 1001b |
| 54 | .endm |
| 55 | |