Boris BREZILLON | e4e3d1b | 2014-05-09 13:11:48 +0200 | [diff] [blame] | 1 | * Allwinner PRCM (Power/Reset/Clock Management) Multi-Functional Device |
| 2 | |
| 3 | PRCM is an MFD device exposing several Power Management related devices |
| 4 | (like clks and reset controllers). |
| 5 | |
| 6 | Required properties: |
Chen-Yu Tsai | 4eb9560 | 2014-07-09 15:54:36 +0800 | [diff] [blame] | 7 | - compatible: "allwinner,sun6i-a31-prcm" or "allwinner,sun8i-a23-prcm" |
Boris BREZILLON | e4e3d1b | 2014-05-09 13:11:48 +0200 | [diff] [blame] | 8 | - reg: The PRCM registers range |
| 9 | |
| 10 | The prcm node may contain several subdevices definitions: |
Mauro Carvalho Chehab | e5ca425 | 2018-06-14 12:30:30 -0300 | [diff] [blame] | 11 | - see Documentation/devicetree/bindings/clock/sunxi.txt for clock devices |
Mauro Carvalho Chehab | 34962fb | 2018-05-08 15:14:57 -0300 | [diff] [blame] | 12 | - see Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt for reset |
Boris BREZILLON | e4e3d1b | 2014-05-09 13:11:48 +0200 | [diff] [blame] | 13 | controller devices |
| 14 | |
| 15 | |
| 16 | Example: |
| 17 | |
Marco Franchi | 48c926c | 2017-11-08 14:27:48 -0200 | [diff] [blame] | 18 | prcm: prcm@1f01400 { |
Boris BREZILLON | e4e3d1b | 2014-05-09 13:11:48 +0200 | [diff] [blame] | 19 | compatible = "allwinner,sun6i-a31-prcm"; |
| 20 | reg = <0x01f01400 0x200>; |
| 21 | |
| 22 | /* Put subdevices here */ |
| 23 | ar100: ar100_clk { |
| 24 | compatible = "allwinner,sun6i-a31-ar100-clk"; |
| 25 | #clock-cells = <0>; |
| 26 | clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; |
| 27 | }; |
| 28 | |
| 29 | ahb0: ahb0_clk { |
| 30 | compatible = "fixed-factor-clock"; |
| 31 | #clock-cells = <0>; |
| 32 | clock-div = <1>; |
| 33 | clock-mult = <1>; |
| 34 | clocks = <&ar100_div>; |
| 35 | clock-output-names = "ahb0"; |
| 36 | }; |
| 37 | |
| 38 | apb0: apb0_clk { |
| 39 | compatible = "allwinner,sun6i-a31-apb0-clk"; |
| 40 | #clock-cells = <0>; |
| 41 | clocks = <&ahb0>; |
| 42 | clock-output-names = "apb0"; |
| 43 | }; |
| 44 | |
| 45 | apb0_gates: apb0_gates_clk { |
| 46 | compatible = "allwinner,sun6i-a31-apb0-gates-clk"; |
| 47 | #clock-cells = <1>; |
| 48 | clocks = <&apb0>; |
| 49 | clock-output-names = "apb0_pio", "apb0_ir", |
| 50 | "apb0_timer01", "apb0_p2wi", |
| 51 | "apb0_uart", "apb0_1wire", |
| 52 | "apb0_i2c"; |
| 53 | }; |
| 54 | |
| 55 | apb0_rst: apb0_rst { |
| 56 | compatible = "allwinner,sun6i-a31-clock-reset"; |
| 57 | #reset-cells = <1>; |
| 58 | }; |
| 59 | }; |