blob: 5443a29da7b1be7c334154a06f3015be61df0c7f [file] [log] [blame]
Trevor Wu0261e362021-10-20 15:14:27 +08001// SPDX-License-Identifier: GPL-2.0
2//
3// mt8195-mt6359-rt1011-rt5682.c --
4// MT8195-MT6359-RT1011-RT5682 ALSA SoC machine driver
5//
6// Copyright (c) 2021 MediaTek Inc.
7// Author: Trevor Wu <trevor.wu@mediatek.com>
8//
9
10#include <linux/input.h>
11#include <linux/module.h>
12#include <linux/pm_runtime.h>
13#include <sound/jack.h>
14#include <sound/pcm_params.h>
15#include <sound/rt5682.h>
16#include <sound/soc.h>
17#include "../../codecs/mt6359.h"
18#include "../../codecs/rt1011.h"
19#include "../../codecs/rt5682.h"
20#include "../common/mtk-afe-platform-driver.h"
Trevor Wuc5ab93e2021-12-28 14:48:21 +080021#include "mt8195-afe-clk.h"
Trevor Wu0261e362021-10-20 15:14:27 +080022#include "mt8195-afe-common.h"
23
24#define RT1011_CODEC_DAI "rt1011-aif"
25#define RT1011_DEV0_NAME "rt1011.2-0038"
26#define RT1011_DEV1_NAME "rt1011.2-0039"
27
28#define RT5682_CODEC_DAI "rt5682-aif1"
29#define RT5682_DEV0_NAME "rt5682.2-001a"
30
Trevor Wuc9d57a22021-11-29 22:10:54 +080031#define RT5682S_CODEC_DAI "rt5682s-aif1"
32#define RT5682S_DEV0_NAME "rt5682s.2-001a"
33
Trevor Wu0261e362021-10-20 15:14:27 +080034struct mt8195_mt6359_rt1011_rt5682_priv {
Trevor Wu0261e362021-10-20 15:14:27 +080035 struct snd_soc_jack headset_jack;
36 struct snd_soc_jack dp_jack;
37 struct snd_soc_jack hdmi_jack;
Trevor Wuc5ab93e2021-12-28 14:48:21 +080038 struct clk *i2so1_mclk;
Trevor Wu0261e362021-10-20 15:14:27 +080039};
40
41static const struct snd_soc_dapm_widget
42mt8195_mt6359_rt1011_rt5682_widgets[] = {
43 SND_SOC_DAPM_SPK("Left Speaker", NULL),
44 SND_SOC_DAPM_SPK("Right Speaker", NULL),
45 SND_SOC_DAPM_HP("Headphone Jack", NULL),
46 SND_SOC_DAPM_MIC("Headset Mic", NULL),
47};
48
49static const struct snd_soc_dapm_route mt8195_mt6359_rt1011_rt5682_routes[] = {
50 /* speaker */
51 { "Left Speaker", NULL, "Left SPO" },
52 { "Right Speaker", NULL, "Right SPO" },
53 /* headset */
54 { "Headphone Jack", NULL, "HPOL" },
55 { "Headphone Jack", NULL, "HPOR" },
56 { "IN1P", NULL, "Headset Mic" },
57};
58
59static const struct snd_kcontrol_new mt8195_mt6359_rt1011_rt5682_controls[] = {
60 SOC_DAPM_PIN_SWITCH("Left Speaker"),
61 SOC_DAPM_PIN_SWITCH("Right Speaker"),
62 SOC_DAPM_PIN_SWITCH("Headphone Jack"),
63 SOC_DAPM_PIN_SWITCH("Headset Mic"),
64};
65
66static int mt8195_rt5682_etdm_hw_params(struct snd_pcm_substream *substream,
67 struct snd_pcm_hw_params *params)
68{
69 struct snd_soc_pcm_runtime *rtd = substream->private_data;
70 struct snd_soc_card *card = rtd->card;
71 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
72 struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
73 unsigned int rate = params_rate(params);
74 int bitwidth;
75 int ret;
76
77 bitwidth = snd_pcm_format_width(params_format(params));
78 if (bitwidth < 0) {
79 dev_err(card->dev, "invalid bit width: %d\n", bitwidth);
80 return bitwidth;
81 }
82
83 ret = snd_soc_dai_set_tdm_slot(codec_dai, 0x00, 0x0, 0x2, bitwidth);
84 if (ret) {
85 dev_err(card->dev, "failed to set tdm slot\n");
86 return ret;
87 }
88
Trevor Wuc5ab93e2021-12-28 14:48:21 +080089 ret = snd_soc_dai_set_pll(codec_dai, RT5682_PLL1, RT5682_PLL1_S_MCLK,
90 rate * 256, rate * 512);
Trevor Wu0261e362021-10-20 15:14:27 +080091 if (ret) {
92 dev_err(card->dev, "failed to set pll\n");
93 return ret;
94 }
95
96 ret = snd_soc_dai_set_sysclk(codec_dai, RT5682_SCLK_S_PLL1,
97 rate * 512, SND_SOC_CLOCK_IN);
98 if (ret) {
99 dev_err(card->dev, "failed to set sysclk\n");
100 return ret;
101 }
102
Trevor Wuc5ab93e2021-12-28 14:48:21 +0800103 return snd_soc_dai_set_sysclk(cpu_dai, 0, rate * 256,
Trevor Wu0261e362021-10-20 15:14:27 +0800104 SND_SOC_CLOCK_OUT);
105}
106
107static const struct snd_soc_ops mt8195_rt5682_etdm_ops = {
108 .hw_params = mt8195_rt5682_etdm_hw_params,
109};
110
111static int mt8195_rt1011_etdm_hw_params(struct snd_pcm_substream *substream,
112 struct snd_pcm_hw_params *params)
113{
114 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
115 struct snd_soc_dai *codec_dai;
116 struct snd_soc_card *card = rtd->card;
117 int srate, i, ret = 0;
118
119 srate = params_rate(params);
120
121 for_each_rtd_codec_dais(rtd, i, codec_dai) {
122 ret = snd_soc_dai_set_pll(codec_dai, 0, RT1011_PLL1_S_BCLK,
123 64 * srate, 256 * srate);
124 if (ret < 0) {
125 dev_err(card->dev, "codec_dai clock not set\n");
126 return ret;
127 }
128
129 ret = snd_soc_dai_set_sysclk(codec_dai,
130 RT1011_FS_SYS_PRE_S_PLL1,
131 256 * srate, SND_SOC_CLOCK_IN);
132 if (ret < 0) {
133 dev_err(card->dev, "codec_dai clock not set\n");
134 return ret;
135 }
136 }
137 return ret;
138}
139
140static const struct snd_soc_ops mt8195_rt1011_etdm_ops = {
141 .hw_params = mt8195_rt1011_etdm_hw_params,
142};
143
144#define CKSYS_AUD_TOP_CFG 0x032c
145#define CKSYS_AUD_TOP_MON 0x0330
146
147static int mt8195_mt6359_mtkaif_calibration(struct snd_soc_pcm_runtime *rtd)
148{
149 struct snd_soc_component *cmpnt_afe =
150 snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
151 struct snd_soc_component *cmpnt_codec =
152 asoc_rtd_to_codec(rtd, 0)->component;
153 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt_afe);
154 struct mt8195_afe_private *afe_priv = afe->platform_priv;
155 struct mtkaif_param *param = &afe_priv->mtkaif_params;
156 int chosen_phase_1, chosen_phase_2, chosen_phase_3;
157 int prev_cycle_1, prev_cycle_2, prev_cycle_3;
158 int test_done_1, test_done_2, test_done_3;
159 int cycle_1, cycle_2, cycle_3;
160 int mtkaif_chosen_phase[MT8195_MTKAIF_MISO_NUM];
161 int mtkaif_phase_cycle[MT8195_MTKAIF_MISO_NUM];
162 int mtkaif_calibration_num_phase;
163 bool mtkaif_calibration_ok;
164 unsigned int monitor;
165 int counter;
166 int phase;
167 int i;
168
169 dev_dbg(afe->dev, "%s(), start\n", __func__);
170
171 param->mtkaif_calibration_ok = false;
172 for (i = 0; i < MT8195_MTKAIF_MISO_NUM; i++) {
173 param->mtkaif_chosen_phase[i] = -1;
174 param->mtkaif_phase_cycle[i] = 0;
175 mtkaif_chosen_phase[i] = -1;
176 mtkaif_phase_cycle[i] = 0;
177 }
178
179 if (IS_ERR(afe_priv->topckgen)) {
180 dev_info(afe->dev, "%s() Cannot find topckgen controller\n",
181 __func__);
182 return 0;
183 }
184
185 pm_runtime_get_sync(afe->dev);
186 mt6359_mtkaif_calibration_enable(cmpnt_codec);
187
188 /* set test type to synchronizer pulse */
189 regmap_update_bits(afe_priv->topckgen,
190 CKSYS_AUD_TOP_CFG, 0xffff, 0x4);
191 mtkaif_calibration_num_phase = 42; /* mt6359: 0 ~ 42 */
192 mtkaif_calibration_ok = true;
193
194 for (phase = 0;
195 phase <= mtkaif_calibration_num_phase && mtkaif_calibration_ok;
196 phase++) {
197 mt6359_set_mtkaif_calibration_phase(cmpnt_codec,
198 phase, phase, phase);
199
200 regmap_update_bits(afe_priv->topckgen,
201 CKSYS_AUD_TOP_CFG, 0x1, 0x1);
202
203 test_done_1 = 0;
204 test_done_2 = 0;
205 test_done_3 = 0;
206 cycle_1 = -1;
207 cycle_2 = -1;
208 cycle_3 = -1;
209 counter = 0;
210 while (!(test_done_1 & test_done_2 & test_done_3)) {
211 regmap_read(afe_priv->topckgen,
212 CKSYS_AUD_TOP_MON, &monitor);
213 test_done_1 = (monitor >> 28) & 0x1;
214 test_done_2 = (monitor >> 29) & 0x1;
215 test_done_3 = (monitor >> 30) & 0x1;
216 if (test_done_1 == 1)
217 cycle_1 = monitor & 0xf;
218
219 if (test_done_2 == 1)
220 cycle_2 = (monitor >> 4) & 0xf;
221
222 if (test_done_3 == 1)
223 cycle_3 = (monitor >> 8) & 0xf;
224
225 /* handle if never test done */
226 if (++counter > 10000) {
227 dev_info(afe->dev, "%s(), test fail, cycle_1 %d, cycle_2 %d, cycle_3 %d, monitor 0x%x\n",
228 __func__,
229 cycle_1, cycle_2, cycle_3, monitor);
230 mtkaif_calibration_ok = false;
231 break;
232 }
233 }
234
235 if (phase == 0) {
236 prev_cycle_1 = cycle_1;
237 prev_cycle_2 = cycle_2;
238 prev_cycle_3 = cycle_3;
239 }
240
241 if (cycle_1 != prev_cycle_1 &&
242 mtkaif_chosen_phase[MT8195_MTKAIF_MISO_0] < 0) {
243 mtkaif_chosen_phase[MT8195_MTKAIF_MISO_0] = phase - 1;
244 mtkaif_phase_cycle[MT8195_MTKAIF_MISO_0] = prev_cycle_1;
245 }
246
247 if (cycle_2 != prev_cycle_2 &&
248 mtkaif_chosen_phase[MT8195_MTKAIF_MISO_1] < 0) {
249 mtkaif_chosen_phase[MT8195_MTKAIF_MISO_1] = phase - 1;
250 mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1] = prev_cycle_2;
251 }
252
253 if (cycle_3 != prev_cycle_3 &&
254 mtkaif_chosen_phase[MT8195_MTKAIF_MISO_2] < 0) {
255 mtkaif_chosen_phase[MT8195_MTKAIF_MISO_2] = phase - 1;
256 mtkaif_phase_cycle[MT8195_MTKAIF_MISO_2] = prev_cycle_3;
257 }
258
259 regmap_update_bits(afe_priv->topckgen,
260 CKSYS_AUD_TOP_CFG, 0x1, 0x0);
261
262 if (mtkaif_chosen_phase[MT8195_MTKAIF_MISO_0] >= 0 &&
263 mtkaif_chosen_phase[MT8195_MTKAIF_MISO_1] >= 0 &&
264 mtkaif_chosen_phase[MT8195_MTKAIF_MISO_2] >= 0)
265 break;
266 }
267
268 if (mtkaif_chosen_phase[MT8195_MTKAIF_MISO_0] < 0) {
269 mtkaif_calibration_ok = false;
270 chosen_phase_1 = 0;
271 } else {
272 chosen_phase_1 = mtkaif_chosen_phase[MT8195_MTKAIF_MISO_0];
273 }
274
275 if (mtkaif_chosen_phase[MT8195_MTKAIF_MISO_1] < 0) {
276 mtkaif_calibration_ok = false;
277 chosen_phase_2 = 0;
278 } else {
279 chosen_phase_2 = mtkaif_chosen_phase[MT8195_MTKAIF_MISO_1];
280 }
281
282 if (mtkaif_chosen_phase[MT8195_MTKAIF_MISO_2] < 0) {
283 mtkaif_calibration_ok = false;
284 chosen_phase_3 = 0;
285 } else {
286 chosen_phase_3 = mtkaif_chosen_phase[MT8195_MTKAIF_MISO_2];
287 }
288
289 mt6359_set_mtkaif_calibration_phase(cmpnt_codec,
290 chosen_phase_1,
291 chosen_phase_2,
292 chosen_phase_3);
293
294 mt6359_mtkaif_calibration_disable(cmpnt_codec);
295 pm_runtime_put(afe->dev);
296
297 param->mtkaif_calibration_ok = mtkaif_calibration_ok;
298 param->mtkaif_chosen_phase[MT8195_MTKAIF_MISO_0] = chosen_phase_1;
299 param->mtkaif_chosen_phase[MT8195_MTKAIF_MISO_1] = chosen_phase_2;
300 param->mtkaif_chosen_phase[MT8195_MTKAIF_MISO_2] = chosen_phase_3;
301 for (i = 0; i < MT8195_MTKAIF_MISO_NUM; i++)
302 param->mtkaif_phase_cycle[i] = mtkaif_phase_cycle[i];
303
304 dev_info(afe->dev, "%s(), end, calibration ok %d\n",
305 __func__, param->mtkaif_calibration_ok);
306
307 return 0;
308}
309
310static int mt8195_mt6359_init(struct snd_soc_pcm_runtime *rtd)
311{
312 struct snd_soc_component *cmpnt_codec =
313 asoc_rtd_to_codec(rtd, 0)->component;
314
315 /* set mtkaif protocol */
316 mt6359_set_mtkaif_protocol(cmpnt_codec,
317 MT6359_MTKAIF_PROTOCOL_2_CLK_P2);
318
319 /* mtkaif calibration */
320 mt8195_mt6359_mtkaif_calibration(rtd);
321
322 return 0;
323}
324
325static int mt8195_rt5682_init(struct snd_soc_pcm_runtime *rtd)
326{
327 struct snd_soc_component *cmpnt_codec =
328 asoc_rtd_to_codec(rtd, 0)->component;
329 struct mt8195_mt6359_rt1011_rt5682_priv *priv =
330 snd_soc_card_get_drvdata(rtd->card);
331 struct snd_soc_jack *jack = &priv->headset_jack;
Trevor Wuc5ab93e2021-12-28 14:48:21 +0800332 struct snd_soc_component *cmpnt_afe =
333 snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
334 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt_afe);
335 struct mt8195_afe_private *afe_priv = afe->platform_priv;
Trevor Wu0261e362021-10-20 15:14:27 +0800336 int ret;
337
Trevor Wuc5ab93e2021-12-28 14:48:21 +0800338 priv->i2so1_mclk = afe_priv->clk[MT8195_CLK_TOP_APLL12_DIV2];
339
Trevor Wu0261e362021-10-20 15:14:27 +0800340 ret = snd_soc_card_jack_new(rtd->card, "Headset Jack",
341 SND_JACK_HEADSET | SND_JACK_BTN_0 |
342 SND_JACK_BTN_1 | SND_JACK_BTN_2 |
343 SND_JACK_BTN_3,
344 jack, NULL, 0);
345 if (ret) {
346 dev_err(rtd->dev, "Headset Jack creation failed: %d\n", ret);
347 return ret;
348 }
349
350 snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
351 snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOICECOMMAND);
352 snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEUP);
353 snd_jack_set_key(jack->jack, SND_JACK_BTN_3, KEY_VOLUMEDOWN);
354
355 ret = snd_soc_component_set_jack(cmpnt_codec, jack, NULL);
356 if (ret) {
357 dev_err(rtd->dev, "Headset Jack set failed: %d\n", ret);
358 return ret;
359 }
360
361 return 0;
362};
363
364static int mt8195_etdm_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
365 struct snd_pcm_hw_params *params)
366{
Jiaxin Yu03c21922021-12-09 15:32:24 +0800367 /* fix BE i2s format to S24_LE, clean param mask first */
Trevor Wu0261e362021-10-20 15:14:27 +0800368 snd_mask_reset_range(hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT),
369 0, (__force unsigned int)SNDRV_PCM_FORMAT_LAST);
370
371 params_set_format(params, SNDRV_PCM_FORMAT_S24_LE);
372
373 return 0;
374}
375
376static int mt8195_hdmitx_dptx_startup(struct snd_pcm_substream *substream)
377{
378 static const unsigned int rates[] = {
379 48000
380 };
381 static const unsigned int channels[] = {
382 2, 4, 6, 8
383 };
384 static const struct snd_pcm_hw_constraint_list constraints_rates = {
385 .count = ARRAY_SIZE(rates),
386 .list = rates,
387 .mask = 0,
388 };
389 static const struct snd_pcm_hw_constraint_list constraints_channels = {
390 .count = ARRAY_SIZE(channels),
391 .list = channels,
392 .mask = 0,
393 };
394
395 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
396 struct snd_pcm_runtime *runtime = substream->runtime;
397 int ret;
398
399 ret = snd_pcm_hw_constraint_list(runtime, 0,
400 SNDRV_PCM_HW_PARAM_RATE,
401 &constraints_rates);
402 if (ret < 0) {
403 dev_err(rtd->dev, "hw_constraint_list rate failed\n");
404 return ret;
405 }
406
407 ret = snd_pcm_hw_constraint_list(runtime, 0,
408 SNDRV_PCM_HW_PARAM_CHANNELS,
409 &constraints_channels);
410 if (ret < 0) {
411 dev_err(rtd->dev, "hw_constraint_list channel failed\n");
412 return ret;
413 }
414
415 return 0;
416}
417
418static const struct snd_soc_ops mt8195_hdmitx_dptx_playback_ops = {
419 .startup = mt8195_hdmitx_dptx_startup,
420};
421
422static int mt8195_dptx_hw_params(struct snd_pcm_substream *substream,
423 struct snd_pcm_hw_params *params)
424{
425 struct snd_soc_pcm_runtime *rtd = substream->private_data;
426 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
427
428 return snd_soc_dai_set_sysclk(cpu_dai, 0, params_rate(params) * 256,
429 SND_SOC_CLOCK_OUT);
430}
431
Rikard Falkeborn8752d9a2021-11-27 10:31:47 +0100432static const struct snd_soc_ops mt8195_dptx_ops = {
Trevor Wu0261e362021-10-20 15:14:27 +0800433 .hw_params = mt8195_dptx_hw_params,
434};
435
436static int mt8195_dptx_codec_init(struct snd_soc_pcm_runtime *rtd)
437{
438 struct mt8195_mt6359_rt1011_rt5682_priv *priv =
439 snd_soc_card_get_drvdata(rtd->card);
440 struct snd_soc_component *cmpnt_codec =
441 asoc_rtd_to_codec(rtd, 0)->component;
442 int ret;
443
444 ret = snd_soc_card_jack_new(rtd->card, "DP Jack", SND_JACK_LINEOUT,
445 &priv->dp_jack, NULL, 0);
446 if (ret)
447 return ret;
448
449 return snd_soc_component_set_jack(cmpnt_codec, &priv->dp_jack, NULL);
450}
451
452static int mt8195_hdmi_codec_init(struct snd_soc_pcm_runtime *rtd)
453{
454 struct mt8195_mt6359_rt1011_rt5682_priv *priv =
455 snd_soc_card_get_drvdata(rtd->card);
456 struct snd_soc_component *cmpnt_codec =
457 asoc_rtd_to_codec(rtd, 0)->component;
458 int ret;
459
460 ret = snd_soc_card_jack_new(rtd->card, "HDMI Jack", SND_JACK_LINEOUT,
461 &priv->hdmi_jack, NULL, 0);
462 if (ret)
463 return ret;
464
465 return snd_soc_component_set_jack(cmpnt_codec, &priv->hdmi_jack, NULL);
466}
467
468static int mt8195_dptx_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
469 struct snd_pcm_hw_params *params)
470
471{
Jiaxin Yu03c21922021-12-09 15:32:24 +0800472 /* fix BE i2s format to S24_LE, clean param mask first */
Trevor Wu0261e362021-10-20 15:14:27 +0800473 snd_mask_reset_range(hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT),
474 0, (__force unsigned int)SNDRV_PCM_FORMAT_LAST);
475
476 params_set_format(params, SNDRV_PCM_FORMAT_S24_LE);
477
478 return 0;
479}
480
481static int mt8195_playback_startup(struct snd_pcm_substream *substream)
482{
483 static const unsigned int rates[] = {
484 48000
485 };
486 static const unsigned int channels[] = {
487 2
488 };
489 static const struct snd_pcm_hw_constraint_list constraints_rates = {
490 .count = ARRAY_SIZE(rates),
491 .list = rates,
492 .mask = 0,
493 };
494 static const struct snd_pcm_hw_constraint_list constraints_channels = {
495 .count = ARRAY_SIZE(channels),
496 .list = channels,
497 .mask = 0,
498 };
499
500 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
501 struct snd_pcm_runtime *runtime = substream->runtime;
502 int ret;
503
504 ret = snd_pcm_hw_constraint_list(runtime, 0,
505 SNDRV_PCM_HW_PARAM_RATE,
506 &constraints_rates);
507 if (ret < 0) {
508 dev_err(rtd->dev, "hw_constraint_list rate failed\n");
509 return ret;
510 }
511
512 ret = snd_pcm_hw_constraint_list(runtime, 0,
513 SNDRV_PCM_HW_PARAM_CHANNELS,
514 &constraints_channels);
515 if (ret < 0) {
516 dev_err(rtd->dev, "hw_constraint_list channel failed\n");
517 return ret;
518 }
519
520 return 0;
521}
522
523static const struct snd_soc_ops mt8195_playback_ops = {
524 .startup = mt8195_playback_startup,
525};
526
527static int mt8195_capture_startup(struct snd_pcm_substream *substream)
528{
529 static const unsigned int rates[] = {
530 48000
531 };
532 static const unsigned int channels[] = {
533 1, 2
534 };
535 static const struct snd_pcm_hw_constraint_list constraints_rates = {
536 .count = ARRAY_SIZE(rates),
537 .list = rates,
538 .mask = 0,
539 };
540 static const struct snd_pcm_hw_constraint_list constraints_channels = {
541 .count = ARRAY_SIZE(channels),
542 .list = channels,
543 .mask = 0,
544 };
545
546 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
547 struct snd_pcm_runtime *runtime = substream->runtime;
548 int ret;
549
550 ret = snd_pcm_hw_constraint_list(runtime, 0,
551 SNDRV_PCM_HW_PARAM_RATE,
552 &constraints_rates);
553 if (ret < 0) {
554 dev_err(rtd->dev, "hw_constraint_list rate failed\n");
555 return ret;
556 }
557
558 ret = snd_pcm_hw_constraint_list(runtime, 0,
559 SNDRV_PCM_HW_PARAM_CHANNELS,
560 &constraints_channels);
561 if (ret < 0) {
562 dev_err(rtd->dev, "hw_constraint_list channel failed\n");
563 return ret;
564 }
565
566 return 0;
567}
568
569static const struct snd_soc_ops mt8195_capture_ops = {
570 .startup = mt8195_capture_startup,
571};
572
Trevor Wuc5ab93e2021-12-28 14:48:21 +0800573static int mt8195_set_bias_level_post(struct snd_soc_card *card,
574 struct snd_soc_dapm_context *dapm, enum snd_soc_bias_level level)
575{
576 struct snd_soc_component *component = dapm->component;
577 struct mt8195_mt6359_rt1011_rt5682_priv *priv =
578 snd_soc_card_get_drvdata(card);
579 int ret;
580
581 /*
582 * It's required to control mclk directly in the set_bias_level_post
583 * function for rt5682 and rt5682s codec, or the unexpected pop happens
584 * at the end of playback.
585 */
586 if (!component ||
587 (strcmp(component->name, RT5682_DEV0_NAME) &&
588 strcmp(component->name, RT5682S_DEV0_NAME)))
589 return 0;
590
591 switch (level) {
592 case SND_SOC_BIAS_OFF:
593 if (!__clk_is_enabled(priv->i2so1_mclk))
594 return 0;
595
596 clk_disable_unprepare(priv->i2so1_mclk);
597 dev_dbg(card->dev, "Disable i2so1 mclk\n");
598 break;
599 case SND_SOC_BIAS_ON:
600 ret = clk_prepare_enable(priv->i2so1_mclk);
601 if (ret) {
602 dev_err(card->dev, "Can't enable i2so1 mclk: %d\n", ret);
603 return ret;
604 }
605 dev_dbg(card->dev, "Enable i2so1 mclk\n");
606 break;
607 default:
608 break;
609 }
610
611 return 0;
612}
613
Trevor Wu0261e362021-10-20 15:14:27 +0800614enum {
615 DAI_LINK_DL2_FE,
616 DAI_LINK_DL3_FE,
617 DAI_LINK_DL6_FE,
618 DAI_LINK_DL7_FE,
619 DAI_LINK_DL8_FE,
620 DAI_LINK_DL10_FE,
621 DAI_LINK_DL11_FE,
622 DAI_LINK_UL1_FE,
623 DAI_LINK_UL2_FE,
624 DAI_LINK_UL3_FE,
625 DAI_LINK_UL4_FE,
626 DAI_LINK_UL5_FE,
627 DAI_LINK_UL6_FE,
628 DAI_LINK_UL8_FE,
629 DAI_LINK_UL9_FE,
630 DAI_LINK_UL10_FE,
631 DAI_LINK_DL_SRC_BE,
632 DAI_LINK_DPTX_BE,
633 DAI_LINK_ETDM1_IN_BE,
634 DAI_LINK_ETDM2_IN_BE,
635 DAI_LINK_ETDM1_OUT_BE,
636 DAI_LINK_ETDM2_OUT_BE,
637 DAI_LINK_ETDM3_OUT_BE,
638 DAI_LINK_PCM1_BE,
639 DAI_LINK_UL_SRC1_BE,
640 DAI_LINK_UL_SRC2_BE,
641};
642
643/* FE */
644SND_SOC_DAILINK_DEFS(DL2_FE,
645 DAILINK_COMP_ARRAY(COMP_CPU("DL2")),
646 DAILINK_COMP_ARRAY(COMP_DUMMY()),
647 DAILINK_COMP_ARRAY(COMP_EMPTY()));
648
649SND_SOC_DAILINK_DEFS(DL3_FE,
650 DAILINK_COMP_ARRAY(COMP_CPU("DL3")),
651 DAILINK_COMP_ARRAY(COMP_DUMMY()),
652 DAILINK_COMP_ARRAY(COMP_EMPTY()));
653
654SND_SOC_DAILINK_DEFS(DL6_FE,
655 DAILINK_COMP_ARRAY(COMP_CPU("DL6")),
656 DAILINK_COMP_ARRAY(COMP_DUMMY()),
657 DAILINK_COMP_ARRAY(COMP_EMPTY()));
658
659SND_SOC_DAILINK_DEFS(DL7_FE,
660 DAILINK_COMP_ARRAY(COMP_CPU("DL7")),
661 DAILINK_COMP_ARRAY(COMP_DUMMY()),
662 DAILINK_COMP_ARRAY(COMP_EMPTY()));
663
664SND_SOC_DAILINK_DEFS(DL8_FE,
665 DAILINK_COMP_ARRAY(COMP_CPU("DL8")),
666 DAILINK_COMP_ARRAY(COMP_DUMMY()),
667 DAILINK_COMP_ARRAY(COMP_EMPTY()));
668
669SND_SOC_DAILINK_DEFS(DL10_FE,
670 DAILINK_COMP_ARRAY(COMP_CPU("DL10")),
671 DAILINK_COMP_ARRAY(COMP_DUMMY()),
672 DAILINK_COMP_ARRAY(COMP_EMPTY()));
673
674SND_SOC_DAILINK_DEFS(DL11_FE,
675 DAILINK_COMP_ARRAY(COMP_CPU("DL11")),
676 DAILINK_COMP_ARRAY(COMP_DUMMY()),
677 DAILINK_COMP_ARRAY(COMP_EMPTY()));
678
679SND_SOC_DAILINK_DEFS(UL1_FE,
680 DAILINK_COMP_ARRAY(COMP_CPU("UL1")),
681 DAILINK_COMP_ARRAY(COMP_DUMMY()),
682 DAILINK_COMP_ARRAY(COMP_EMPTY()));
683
684SND_SOC_DAILINK_DEFS(UL2_FE,
685 DAILINK_COMP_ARRAY(COMP_CPU("UL2")),
686 DAILINK_COMP_ARRAY(COMP_DUMMY()),
687 DAILINK_COMP_ARRAY(COMP_EMPTY()));
688
689SND_SOC_DAILINK_DEFS(UL3_FE,
690 DAILINK_COMP_ARRAY(COMP_CPU("UL3")),
691 DAILINK_COMP_ARRAY(COMP_DUMMY()),
692 DAILINK_COMP_ARRAY(COMP_EMPTY()));
693
694SND_SOC_DAILINK_DEFS(UL4_FE,
695 DAILINK_COMP_ARRAY(COMP_CPU("UL4")),
696 DAILINK_COMP_ARRAY(COMP_DUMMY()),
697 DAILINK_COMP_ARRAY(COMP_EMPTY()));
698
699SND_SOC_DAILINK_DEFS(UL5_FE,
700 DAILINK_COMP_ARRAY(COMP_CPU("UL5")),
701 DAILINK_COMP_ARRAY(COMP_DUMMY()),
702 DAILINK_COMP_ARRAY(COMP_EMPTY()));
703
704SND_SOC_DAILINK_DEFS(UL6_FE,
705 DAILINK_COMP_ARRAY(COMP_CPU("UL6")),
706 DAILINK_COMP_ARRAY(COMP_DUMMY()),
707 DAILINK_COMP_ARRAY(COMP_EMPTY()));
708
709SND_SOC_DAILINK_DEFS(UL8_FE,
710 DAILINK_COMP_ARRAY(COMP_CPU("UL8")),
711 DAILINK_COMP_ARRAY(COMP_DUMMY()),
712 DAILINK_COMP_ARRAY(COMP_EMPTY()));
713
714SND_SOC_DAILINK_DEFS(UL9_FE,
715 DAILINK_COMP_ARRAY(COMP_CPU("UL9")),
716 DAILINK_COMP_ARRAY(COMP_DUMMY()),
717 DAILINK_COMP_ARRAY(COMP_EMPTY()));
718
719SND_SOC_DAILINK_DEFS(UL10_FE,
720 DAILINK_COMP_ARRAY(COMP_CPU("UL10")),
721 DAILINK_COMP_ARRAY(COMP_DUMMY()),
722 DAILINK_COMP_ARRAY(COMP_EMPTY()));
723
724/* BE */
725SND_SOC_DAILINK_DEFS(DL_SRC_BE,
726 DAILINK_COMP_ARRAY(COMP_CPU("DL_SRC")),
727 DAILINK_COMP_ARRAY(COMP_CODEC("mt6359-sound",
728 "mt6359-snd-codec-aif1")),
729 DAILINK_COMP_ARRAY(COMP_EMPTY()));
730
731SND_SOC_DAILINK_DEFS(DPTX_BE,
732 DAILINK_COMP_ARRAY(COMP_CPU("DPTX")),
733 DAILINK_COMP_ARRAY(COMP_DUMMY()),
734 DAILINK_COMP_ARRAY(COMP_EMPTY()));
735
736SND_SOC_DAILINK_DEFS(ETDM1_IN_BE,
737 DAILINK_COMP_ARRAY(COMP_CPU("ETDM1_IN")),
738 DAILINK_COMP_ARRAY(COMP_DUMMY()),
739 DAILINK_COMP_ARRAY(COMP_EMPTY()));
740
741SND_SOC_DAILINK_DEFS(ETDM2_IN_BE,
742 DAILINK_COMP_ARRAY(COMP_CPU("ETDM2_IN")),
Trevor Wuc9d57a22021-11-29 22:10:54 +0800743 DAILINK_COMP_ARRAY(COMP_DUMMY()),
Trevor Wu0261e362021-10-20 15:14:27 +0800744 DAILINK_COMP_ARRAY(COMP_EMPTY()));
745
746SND_SOC_DAILINK_DEFS(ETDM1_OUT_BE,
747 DAILINK_COMP_ARRAY(COMP_CPU("ETDM1_OUT")),
Trevor Wuc9d57a22021-11-29 22:10:54 +0800748 DAILINK_COMP_ARRAY(COMP_DUMMY()),
Trevor Wu0261e362021-10-20 15:14:27 +0800749 DAILINK_COMP_ARRAY(COMP_EMPTY()));
750
751SND_SOC_DAILINK_DEFS(ETDM2_OUT_BE,
752 DAILINK_COMP_ARRAY(COMP_CPU("ETDM2_OUT")),
753 DAILINK_COMP_ARRAY(COMP_CODEC(RT1011_DEV0_NAME,
754 RT1011_CODEC_DAI),
755 COMP_CODEC(RT1011_DEV1_NAME,
756 RT1011_CODEC_DAI)),
757 DAILINK_COMP_ARRAY(COMP_EMPTY()));
758
759SND_SOC_DAILINK_DEFS(ETDM3_OUT_BE,
760 DAILINK_COMP_ARRAY(COMP_CPU("ETDM3_OUT")),
761 DAILINK_COMP_ARRAY(COMP_DUMMY()),
762 DAILINK_COMP_ARRAY(COMP_EMPTY()));
763
764SND_SOC_DAILINK_DEFS(PCM1_BE,
765 DAILINK_COMP_ARRAY(COMP_CPU("PCM1")),
766 DAILINK_COMP_ARRAY(COMP_DUMMY()),
767 DAILINK_COMP_ARRAY(COMP_EMPTY()));
768
769SND_SOC_DAILINK_DEFS(UL_SRC1_BE,
770 DAILINK_COMP_ARRAY(COMP_CPU("UL_SRC1")),
771 DAILINK_COMP_ARRAY(COMP_CODEC("mt6359-sound",
772 "mt6359-snd-codec-aif1"),
773 COMP_CODEC("dmic-codec",
774 "dmic-hifi")),
775 DAILINK_COMP_ARRAY(COMP_EMPTY()));
776
777SND_SOC_DAILINK_DEFS(UL_SRC2_BE,
778 DAILINK_COMP_ARRAY(COMP_CPU("UL_SRC2")),
779 DAILINK_COMP_ARRAY(COMP_CODEC("mt6359-sound",
780 "mt6359-snd-codec-aif2")),
781 DAILINK_COMP_ARRAY(COMP_EMPTY()));
782
783static struct snd_soc_dai_link mt8195_mt6359_rt1011_rt5682_dai_links[] = {
784 /* FE */
785 [DAI_LINK_DL2_FE] = {
786 .name = "DL2_FE",
787 .stream_name = "DL2 Playback",
788 .trigger = {
789 SND_SOC_DPCM_TRIGGER_POST,
790 SND_SOC_DPCM_TRIGGER_POST,
791 },
792 .dynamic = 1,
793 .dpcm_playback = 1,
794 .ops = &mt8195_playback_ops,
795 SND_SOC_DAILINK_REG(DL2_FE),
796 },
797 [DAI_LINK_DL3_FE] = {
798 .name = "DL3_FE",
799 .stream_name = "DL3 Playback",
800 .trigger = {
801 SND_SOC_DPCM_TRIGGER_POST,
802 SND_SOC_DPCM_TRIGGER_POST,
803 },
804 .dynamic = 1,
805 .dpcm_playback = 1,
806 .ops = &mt8195_playback_ops,
807 SND_SOC_DAILINK_REG(DL3_FE),
808 },
809 [DAI_LINK_DL6_FE] = {
810 .name = "DL6_FE",
811 .stream_name = "DL6 Playback",
812 .trigger = {
813 SND_SOC_DPCM_TRIGGER_POST,
814 SND_SOC_DPCM_TRIGGER_POST,
815 },
816 .dynamic = 1,
817 .dpcm_playback = 1,
818 .ops = &mt8195_playback_ops,
819 SND_SOC_DAILINK_REG(DL6_FE),
820 },
821 [DAI_LINK_DL7_FE] = {
822 .name = "DL7_FE",
823 .stream_name = "DL7 Playback",
824 .trigger = {
825 SND_SOC_DPCM_TRIGGER_PRE,
826 SND_SOC_DPCM_TRIGGER_PRE,
827 },
828 .dynamic = 1,
829 .dpcm_playback = 1,
830 SND_SOC_DAILINK_REG(DL7_FE),
831 },
832 [DAI_LINK_DL8_FE] = {
833 .name = "DL8_FE",
834 .stream_name = "DL8 Playback",
835 .trigger = {
836 SND_SOC_DPCM_TRIGGER_POST,
837 SND_SOC_DPCM_TRIGGER_POST,
838 },
839 .dynamic = 1,
840 .dpcm_playback = 1,
841 .ops = &mt8195_playback_ops,
842 SND_SOC_DAILINK_REG(DL8_FE),
843 },
844 [DAI_LINK_DL10_FE] = {
845 .name = "DL10_FE",
846 .stream_name = "DL10 Playback",
847 .trigger = {
848 SND_SOC_DPCM_TRIGGER_POST,
849 SND_SOC_DPCM_TRIGGER_POST,
850 },
851 .dynamic = 1,
852 .dpcm_playback = 1,
853 .ops = &mt8195_hdmitx_dptx_playback_ops,
854 SND_SOC_DAILINK_REG(DL10_FE),
855 },
856 [DAI_LINK_DL11_FE] = {
857 .name = "DL11_FE",
858 .stream_name = "DL11 Playback",
859 .trigger = {
860 SND_SOC_DPCM_TRIGGER_POST,
861 SND_SOC_DPCM_TRIGGER_POST,
862 },
863 .dynamic = 1,
864 .dpcm_playback = 1,
865 .ops = &mt8195_playback_ops,
866 SND_SOC_DAILINK_REG(DL11_FE),
867 },
868 [DAI_LINK_UL1_FE] = {
869 .name = "UL1_FE",
870 .stream_name = "UL1 Capture",
871 .trigger = {
872 SND_SOC_DPCM_TRIGGER_PRE,
873 SND_SOC_DPCM_TRIGGER_PRE,
874 },
875 .dynamic = 1,
876 .dpcm_capture = 1,
877 SND_SOC_DAILINK_REG(UL1_FE),
878 },
879 [DAI_LINK_UL2_FE] = {
880 .name = "UL2_FE",
881 .stream_name = "UL2 Capture",
882 .trigger = {
883 SND_SOC_DPCM_TRIGGER_POST,
884 SND_SOC_DPCM_TRIGGER_POST,
885 },
886 .dynamic = 1,
887 .dpcm_capture = 1,
888 .ops = &mt8195_capture_ops,
889 SND_SOC_DAILINK_REG(UL2_FE),
890 },
891 [DAI_LINK_UL3_FE] = {
892 .name = "UL3_FE",
893 .stream_name = "UL3 Capture",
894 .trigger = {
895 SND_SOC_DPCM_TRIGGER_POST,
896 SND_SOC_DPCM_TRIGGER_POST,
897 },
898 .dynamic = 1,
899 .dpcm_capture = 1,
900 .ops = &mt8195_capture_ops,
901 SND_SOC_DAILINK_REG(UL3_FE),
902 },
903 [DAI_LINK_UL4_FE] = {
904 .name = "UL4_FE",
905 .stream_name = "UL4 Capture",
906 .trigger = {
907 SND_SOC_DPCM_TRIGGER_POST,
908 SND_SOC_DPCM_TRIGGER_POST,
909 },
910 .dynamic = 1,
911 .dpcm_capture = 1,
912 .ops = &mt8195_capture_ops,
913 SND_SOC_DAILINK_REG(UL4_FE),
914 },
915 [DAI_LINK_UL5_FE] = {
916 .name = "UL5_FE",
917 .stream_name = "UL5 Capture",
918 .trigger = {
919 SND_SOC_DPCM_TRIGGER_POST,
920 SND_SOC_DPCM_TRIGGER_POST,
921 },
922 .dynamic = 1,
923 .dpcm_capture = 1,
924 .ops = &mt8195_capture_ops,
925 SND_SOC_DAILINK_REG(UL5_FE),
926 },
927 [DAI_LINK_UL6_FE] = {
928 .name = "UL6_FE",
929 .stream_name = "UL6 Capture",
930 .trigger = {
931 SND_SOC_DPCM_TRIGGER_PRE,
932 SND_SOC_DPCM_TRIGGER_PRE,
933 },
934 .dynamic = 1,
935 .dpcm_capture = 1,
936 SND_SOC_DAILINK_REG(UL6_FE),
937 },
938 [DAI_LINK_UL8_FE] = {
939 .name = "UL8_FE",
940 .stream_name = "UL8 Capture",
941 .trigger = {
942 SND_SOC_DPCM_TRIGGER_POST,
943 SND_SOC_DPCM_TRIGGER_POST,
944 },
945 .dynamic = 1,
946 .dpcm_capture = 1,
947 .ops = &mt8195_capture_ops,
948 SND_SOC_DAILINK_REG(UL8_FE),
949 },
950 [DAI_LINK_UL9_FE] = {
951 .name = "UL9_FE",
952 .stream_name = "UL9 Capture",
953 .trigger = {
954 SND_SOC_DPCM_TRIGGER_POST,
955 SND_SOC_DPCM_TRIGGER_POST,
956 },
957 .dynamic = 1,
958 .dpcm_capture = 1,
959 .ops = &mt8195_capture_ops,
960 SND_SOC_DAILINK_REG(UL9_FE),
961 },
962 [DAI_LINK_UL10_FE] = {
963 .name = "UL10_FE",
964 .stream_name = "UL10 Capture",
965 .trigger = {
966 SND_SOC_DPCM_TRIGGER_POST,
967 SND_SOC_DPCM_TRIGGER_POST,
968 },
969 .dynamic = 1,
970 .dpcm_capture = 1,
971 .ops = &mt8195_capture_ops,
972 SND_SOC_DAILINK_REG(UL10_FE),
973 },
974 /* BE */
975 [DAI_LINK_DL_SRC_BE] = {
976 .name = "DL_SRC_BE",
977 .init = mt8195_mt6359_init,
978 .no_pcm = 1,
979 .dpcm_playback = 1,
980 SND_SOC_DAILINK_REG(DL_SRC_BE),
981 },
982 [DAI_LINK_DPTX_BE] = {
983 .name = "DPTX_BE",
984 .no_pcm = 1,
985 .dpcm_playback = 1,
986 .ops = &mt8195_dptx_ops,
987 .be_hw_params_fixup = mt8195_dptx_hw_params_fixup,
988 SND_SOC_DAILINK_REG(DPTX_BE),
989 },
990 [DAI_LINK_ETDM1_IN_BE] = {
991 .name = "ETDM1_IN_BE",
992 .no_pcm = 1,
993 .dai_fmt = SND_SOC_DAIFMT_I2S |
994 SND_SOC_DAIFMT_NB_NF |
995 SND_SOC_DAIFMT_CBS_CFS,
996 .dpcm_capture = 1,
997 SND_SOC_DAILINK_REG(ETDM1_IN_BE),
998 },
999 [DAI_LINK_ETDM2_IN_BE] = {
1000 .name = "ETDM2_IN_BE",
1001 .no_pcm = 1,
1002 .dai_fmt = SND_SOC_DAIFMT_I2S |
1003 SND_SOC_DAIFMT_NB_NF |
1004 SND_SOC_DAIFMT_CBS_CFS,
1005 .dpcm_capture = 1,
1006 .init = mt8195_rt5682_init,
1007 .ops = &mt8195_rt5682_etdm_ops,
1008 .be_hw_params_fixup = mt8195_etdm_hw_params_fixup,
1009 SND_SOC_DAILINK_REG(ETDM2_IN_BE),
1010 },
1011 [DAI_LINK_ETDM1_OUT_BE] = {
1012 .name = "ETDM1_OUT_BE",
1013 .no_pcm = 1,
1014 .dai_fmt = SND_SOC_DAIFMT_I2S |
1015 SND_SOC_DAIFMT_NB_NF |
1016 SND_SOC_DAIFMT_CBS_CFS,
1017 .dpcm_playback = 1,
1018 .ops = &mt8195_rt5682_etdm_ops,
1019 .be_hw_params_fixup = mt8195_etdm_hw_params_fixup,
1020 SND_SOC_DAILINK_REG(ETDM1_OUT_BE),
1021 },
1022 [DAI_LINK_ETDM2_OUT_BE] = {
1023 .name = "ETDM2_OUT_BE",
1024 .no_pcm = 1,
1025 .dai_fmt = SND_SOC_DAIFMT_I2S |
1026 SND_SOC_DAIFMT_NB_NF |
1027 SND_SOC_DAIFMT_CBS_CFS,
1028 .dpcm_playback = 1,
1029 .ops = &mt8195_rt1011_etdm_ops,
1030 .be_hw_params_fixup = mt8195_etdm_hw_params_fixup,
1031 SND_SOC_DAILINK_REG(ETDM2_OUT_BE),
1032 },
1033 [DAI_LINK_ETDM3_OUT_BE] = {
1034 .name = "ETDM3_OUT_BE",
1035 .no_pcm = 1,
1036 .dai_fmt = SND_SOC_DAIFMT_I2S |
1037 SND_SOC_DAIFMT_NB_NF |
1038 SND_SOC_DAIFMT_CBS_CFS,
1039 .dpcm_playback = 1,
1040 SND_SOC_DAILINK_REG(ETDM3_OUT_BE),
1041 },
1042 [DAI_LINK_PCM1_BE] = {
1043 .name = "PCM1_BE",
1044 .no_pcm = 1,
1045 .dai_fmt = SND_SOC_DAIFMT_I2S |
1046 SND_SOC_DAIFMT_NB_NF |
1047 SND_SOC_DAIFMT_CBS_CFS,
Trevor Wudb5e1c22021-12-30 16:47:31 +08001048 .dpcm_playback = 1,
Trevor Wu0261e362021-10-20 15:14:27 +08001049 .dpcm_capture = 1,
1050 SND_SOC_DAILINK_REG(PCM1_BE),
1051 },
1052 [DAI_LINK_UL_SRC1_BE] = {
1053 .name = "UL_SRC1_BE",
1054 .no_pcm = 1,
1055 .dpcm_capture = 1,
1056 SND_SOC_DAILINK_REG(UL_SRC1_BE),
1057 },
1058 [DAI_LINK_UL_SRC2_BE] = {
1059 .name = "UL_SRC2_BE",
1060 .no_pcm = 1,
1061 .dpcm_capture = 1,
1062 SND_SOC_DAILINK_REG(UL_SRC2_BE),
1063 },
1064};
1065
1066static struct snd_soc_codec_conf rt1011_amp_conf[] = {
1067 {
1068 .dlc = COMP_CODEC_CONF(RT1011_DEV0_NAME),
1069 .name_prefix = "Left",
1070 },
1071 {
1072 .dlc = COMP_CODEC_CONF(RT1011_DEV1_NAME),
1073 .name_prefix = "Right",
1074 },
1075};
1076
1077static struct snd_soc_card mt8195_mt6359_rt1011_rt5682_soc_card = {
1078 .name = "mt8195_r1011_5682",
1079 .owner = THIS_MODULE,
1080 .dai_link = mt8195_mt6359_rt1011_rt5682_dai_links,
1081 .num_links = ARRAY_SIZE(mt8195_mt6359_rt1011_rt5682_dai_links),
1082 .controls = mt8195_mt6359_rt1011_rt5682_controls,
1083 .num_controls = ARRAY_SIZE(mt8195_mt6359_rt1011_rt5682_controls),
1084 .dapm_widgets = mt8195_mt6359_rt1011_rt5682_widgets,
1085 .num_dapm_widgets = ARRAY_SIZE(mt8195_mt6359_rt1011_rt5682_widgets),
1086 .dapm_routes = mt8195_mt6359_rt1011_rt5682_routes,
1087 .num_dapm_routes = ARRAY_SIZE(mt8195_mt6359_rt1011_rt5682_routes),
1088 .codec_conf = rt1011_amp_conf,
1089 .num_configs = ARRAY_SIZE(rt1011_amp_conf),
Trevor Wuc5ab93e2021-12-28 14:48:21 +08001090 .set_bias_level_post = mt8195_set_bias_level_post,
Trevor Wu0261e362021-10-20 15:14:27 +08001091};
1092
1093static int mt8195_mt6359_rt1011_rt5682_dev_probe(struct platform_device *pdev)
1094{
1095 struct snd_soc_card *card = &mt8195_mt6359_rt1011_rt5682_soc_card;
1096 struct snd_soc_dai_link *dai_link;
1097 struct mt8195_mt6359_rt1011_rt5682_priv *priv;
Tzung-Bi Shih082482a2021-12-24 14:47:19 +08001098 struct device_node *platform_node, *dp_node, *hdmi_node;
Trevor Wuc9d57a22021-11-29 22:10:54 +08001099 int is5682s = 0;
Trevor Wu0261e362021-10-20 15:14:27 +08001100 int ret, i;
1101
1102 card->dev = &pdev->dev;
Trevor Wuc9d57a22021-11-29 22:10:54 +08001103 ret = snd_soc_of_parse_card_name(card, "model");
1104 if (ret) {
1105 dev_err(&pdev->dev, "%s new card name parsing error %d\n",
1106 __func__, ret);
1107 return ret;
1108 }
1109
1110 if (strstr(card->name, "_5682s"))
1111 is5682s = 1;
Trevor Wu0261e362021-10-20 15:14:27 +08001112
1113 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1114 if (!priv)
1115 return -ENOMEM;
1116
Tzung-Bi Shih082482a2021-12-24 14:47:19 +08001117 platform_node = of_parse_phandle(pdev->dev.of_node,
1118 "mediatek,platform", 0);
1119 if (!platform_node) {
Trevor Wu0261e362021-10-20 15:14:27 +08001120 dev_dbg(&pdev->dev, "Property 'platform' missing or invalid\n");
1121 return -EINVAL;
1122 }
1123
Tzung-Bi Shih082482a2021-12-24 14:47:19 +08001124 dp_node = of_parse_phandle(pdev->dev.of_node, "mediatek,dptx-codec", 0);
1125 hdmi_node = of_parse_phandle(pdev->dev.of_node,
1126 "mediatek,hdmi-codec", 0);
1127
Trevor Wu0261e362021-10-20 15:14:27 +08001128 for_each_card_prelinks(card, i, dai_link) {
1129 if (!dai_link->platforms->name)
Tzung-Bi Shih082482a2021-12-24 14:47:19 +08001130 dai_link->platforms->of_node = platform_node;
Trevor Wu0261e362021-10-20 15:14:27 +08001131
1132 if (strcmp(dai_link->name, "DPTX_BE") == 0) {
Tzung-Bi Shih082482a2021-12-24 14:47:19 +08001133 if (!dp_node) {
Trevor Wu0261e362021-10-20 15:14:27 +08001134 dev_dbg(&pdev->dev, "No property 'dptx-codec'\n");
1135 } else {
Tzung-Bi Shih082482a2021-12-24 14:47:19 +08001136 dai_link->codecs->of_node = dp_node;
Trevor Wu0261e362021-10-20 15:14:27 +08001137 dai_link->codecs->name = NULL;
1138 dai_link->codecs->dai_name = "i2s-hifi";
1139 dai_link->init = mt8195_dptx_codec_init;
1140 }
Trevor Wuc9d57a22021-11-29 22:10:54 +08001141 } else if (strcmp(dai_link->name, "ETDM3_OUT_BE") == 0) {
Tzung-Bi Shih082482a2021-12-24 14:47:19 +08001142 if (!hdmi_node) {
Trevor Wu0261e362021-10-20 15:14:27 +08001143 dev_dbg(&pdev->dev, "No property 'hdmi-codec'\n");
1144 } else {
Tzung-Bi Shih082482a2021-12-24 14:47:19 +08001145 dai_link->codecs->of_node = hdmi_node;
Trevor Wu0261e362021-10-20 15:14:27 +08001146 dai_link->codecs->name = NULL;
1147 dai_link->codecs->dai_name = "i2s-hifi";
1148 dai_link->init = mt8195_hdmi_codec_init;
1149 }
Trevor Wuc9d57a22021-11-29 22:10:54 +08001150 } else if (strcmp(dai_link->name, "ETDM1_OUT_BE") == 0 ||
1151 strcmp(dai_link->name, "ETDM2_IN_BE") == 0) {
1152 dai_link->codecs->name =
1153 is5682s ? RT5682S_DEV0_NAME : RT5682_DEV0_NAME;
1154 dai_link->codecs->dai_name =
1155 is5682s ? RT5682S_CODEC_DAI : RT5682_CODEC_DAI;
Trevor Wu0261e362021-10-20 15:14:27 +08001156 }
1157 }
1158
1159 snd_soc_card_set_drvdata(card, priv);
1160
1161 ret = devm_snd_soc_register_card(&pdev->dev, card);
Trevor Wu0261e362021-10-20 15:14:27 +08001162
Tzung-Bi Shih082482a2021-12-24 14:47:19 +08001163 of_node_put(platform_node);
1164 of_node_put(dp_node);
1165 of_node_put(hdmi_node);
Trevor Wu0261e362021-10-20 15:14:27 +08001166 return ret;
1167}
1168
Trevor Wu0261e362021-10-20 15:14:27 +08001169#ifdef CONFIG_OF
1170static const struct of_device_id mt8195_mt6359_rt1011_rt5682_dt_match[] = {
1171 {.compatible = "mediatek,mt8195_mt6359_rt1011_rt5682",},
1172 {}
1173};
1174#endif
1175
1176static const struct dev_pm_ops mt8195_mt6359_rt1011_rt5682_pm_ops = {
1177 .poweroff = snd_soc_poweroff,
1178 .restore = snd_soc_resume,
1179};
1180
1181static struct platform_driver mt8195_mt6359_rt1011_rt5682_driver = {
1182 .driver = {
1183 .name = "mt8195_mt6359_rt1011_rt5682",
1184#ifdef CONFIG_OF
1185 .of_match_table = mt8195_mt6359_rt1011_rt5682_dt_match,
1186#endif
1187 .pm = &mt8195_mt6359_rt1011_rt5682_pm_ops,
1188 },
1189 .probe = mt8195_mt6359_rt1011_rt5682_dev_probe,
Trevor Wu0261e362021-10-20 15:14:27 +08001190};
1191
1192module_platform_driver(mt8195_mt6359_rt1011_rt5682_driver);
1193
1194/* Module information */
1195MODULE_DESCRIPTION("MT8195-MT6359-RT1011-RT5682 ALSA SoC machine driver");
1196MODULE_AUTHOR("Trevor Wu <trevor.wu@mediatek.com>");
1197MODULE_LICENSE("GPL");
1198MODULE_ALIAS("mt8195_mt6359_rt1011_rt5682 soc card");