Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 2 | /* |
Swapnil Jakhade | 92e9ccc | 2020-02-06 07:10:52 +0100 | [diff] [blame] | 3 | * Cadence Torrent SD0801 PHY driver. |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 4 | * |
| 5 | * Copyright 2018 Cadence Design Systems, Inc. |
| 6 | * |
| 7 | */ |
| 8 | |
Swapnil Jakhade | afa4ba0 | 2020-02-06 07:11:01 +0100 | [diff] [blame] | 9 | #include <dt-bindings/phy/phy.h> |
Kishon Vijay Abraham I | fd7abc3 | 2021-03-19 18:11:23 +0530 | [diff] [blame] | 10 | #include <dt-bindings/phy/phy-cadence.h> |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 11 | #include <linux/clk.h> |
Kishon Vijay Abraham I | 2cca022 | 2021-03-10 17:38:40 +0530 | [diff] [blame] | 12 | #include <linux/clk-provider.h> |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 13 | #include <linux/delay.h> |
| 14 | #include <linux/err.h> |
| 15 | #include <linux/io.h> |
| 16 | #include <linux/iopoll.h> |
| 17 | #include <linux/kernel.h> |
| 18 | #include <linux/module.h> |
| 19 | #include <linux/of.h> |
| 20 | #include <linux/of_address.h> |
| 21 | #include <linux/of_device.h> |
| 22 | #include <linux/phy/phy.h> |
| 23 | #include <linux/platform_device.h> |
Swapnil Jakhade | afa4ba0 | 2020-02-06 07:11:01 +0100 | [diff] [blame] | 24 | #include <linux/reset.h> |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 25 | #include <linux/regmap.h> |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 26 | |
Swapnil Jakhade | e956d4f | 2021-07-28 16:54:46 +0200 | [diff] [blame] | 27 | #define REF_CLK_19_2MHZ 19200000 |
| 28 | #define REF_CLK_25MHZ 25000000 |
Swapnil Jakhade | 3b40162 | 2021-07-28 16:54:48 +0200 | [diff] [blame] | 29 | #define REF_CLK_100MHZ 100000000 |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 30 | |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 31 | #define MAX_NUM_LANES 4 |
| 32 | #define DEFAULT_MAX_BIT_RATE 8100 /* in Mbps */ |
| 33 | |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 34 | #define NUM_SSC_MODE 3 |
Swapnil Jakhade | 3b40162 | 2021-07-28 16:54:48 +0200 | [diff] [blame] | 35 | #define NUM_REF_CLK 3 |
Swapnil Jakhade | 9855d84 | 2020-09-17 09:30:44 +0200 | [diff] [blame] | 36 | #define NUM_PHY_TYPE 6 |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 37 | |
Swapnil Jakhade | 21c7914 | 2020-02-06 07:10:55 +0100 | [diff] [blame] | 38 | #define POLL_TIMEOUT_US 5000 |
Swapnil Jakhade | 8e4c95b | 2020-09-17 09:30:35 +0200 | [diff] [blame] | 39 | #define PLL_LOCK_TIMEOUT 100000 |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 40 | |
| 41 | #define TORRENT_COMMON_CDB_OFFSET 0x0 |
| 42 | |
| 43 | #define TORRENT_TX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ |
| 44 | ((0x4000 << (block_offset)) + \ |
| 45 | (((ln) << 9) << (reg_offset))) |
| 46 | |
| 47 | #define TORRENT_RX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ |
| 48 | ((0x8000 << (block_offset)) + \ |
| 49 | (((ln) << 9) << (reg_offset))) |
| 50 | |
| 51 | #define TORRENT_PHY_PCS_COMMON_OFFSET(block_offset) \ |
| 52 | (0xC000 << (block_offset)) |
| 53 | |
Swapnil Jakhade | 48ac608 | 2021-07-28 16:54:54 +0200 | [diff] [blame] | 54 | #define TORRENT_PHY_PCS_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ |
| 55 | ((0xD000 << (block_offset)) + \ |
| 56 | (((ln) << 8) << (reg_offset))) |
| 57 | |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 58 | #define TORRENT_PHY_PMA_COMMON_OFFSET(block_offset) \ |
| 59 | (0xE000 << (block_offset)) |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 60 | |
Swapnil Jakhade | cba472e | 2020-02-06 07:10:59 +0100 | [diff] [blame] | 61 | #define TORRENT_DPTX_PHY_OFFSET 0x0 |
| 62 | |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 63 | /* |
| 64 | * register offsets from DPTX PHY register block base (i.e MHDP |
| 65 | * register base + 0x30a00) |
| 66 | */ |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 67 | #define PHY_AUX_CTRL 0x04 |
| 68 | #define PHY_RESET 0x20 |
Swapnil Jakhade | 572d659 | 2020-02-06 07:10:57 +0100 | [diff] [blame] | 69 | #define PMA_TX_ELEC_IDLE_MASK 0xF0U |
| 70 | #define PMA_TX_ELEC_IDLE_SHIFT 4 |
| 71 | #define PHY_L00_RESET_N_MASK 0x01U |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 72 | #define PHY_PMA_XCVR_PLLCLK_EN 0x24 |
| 73 | #define PHY_PMA_XCVR_PLLCLK_EN_ACK 0x28 |
| 74 | #define PHY_PMA_XCVR_POWER_STATE_REQ 0x2c |
| 75 | #define PHY_POWER_STATE_LN_0 0x0000 |
| 76 | #define PHY_POWER_STATE_LN_1 0x0008 |
| 77 | #define PHY_POWER_STATE_LN_2 0x0010 |
| 78 | #define PHY_POWER_STATE_LN_3 0x0018 |
Swapnil Jakhade | 21c7914 | 2020-02-06 07:10:55 +0100 | [diff] [blame] | 79 | #define PMA_XCVR_POWER_STATE_REQ_LN_MASK 0x3FU |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 80 | #define PHY_PMA_XCVR_POWER_STATE_ACK 0x30 |
| 81 | #define PHY_PMA_CMN_READY 0x34 |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 82 | |
| 83 | /* |
| 84 | * register offsets from SD0801 PHY register block base (i.e MHDP |
| 85 | * register base + 0x500000) |
| 86 | */ |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 87 | #define CMN_SSM_BANDGAP_TMR 0x0021U |
| 88 | #define CMN_SSM_BIAS_TMR 0x0022U |
| 89 | #define CMN_PLLSM0_PLLPRE_TMR 0x002AU |
| 90 | #define CMN_PLLSM0_PLLLOCK_TMR 0x002CU |
| 91 | #define CMN_PLLSM1_PLLPRE_TMR 0x0032U |
| 92 | #define CMN_PLLSM1_PLLLOCK_TMR 0x0034U |
Swapnil Jakhade | 9855d84 | 2020-09-17 09:30:44 +0200 | [diff] [blame] | 93 | #define CMN_CDIAG_CDB_PWRI_OVRD 0x0041U |
| 94 | #define CMN_CDIAG_XCVRC_PWRI_OVRD 0x0047U |
Kishon Vijay Abraham I | 2cca022 | 2021-03-10 17:38:40 +0530 | [diff] [blame] | 95 | #define CMN_CDIAG_REFCLK_OVRD 0x004CU |
| 96 | #define CMN_CDIAG_REFCLK_DRV0_CTRL 0x0050U |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 97 | #define CMN_BGCAL_INIT_TMR 0x0064U |
| 98 | #define CMN_BGCAL_ITER_TMR 0x0065U |
| 99 | #define CMN_IBCAL_INIT_TMR 0x0074U |
| 100 | #define CMN_PLL0_VCOCAL_TCTRL 0x0082U |
| 101 | #define CMN_PLL0_VCOCAL_INIT_TMR 0x0084U |
| 102 | #define CMN_PLL0_VCOCAL_ITER_TMR 0x0085U |
| 103 | #define CMN_PLL0_VCOCAL_REFTIM_START 0x0086U |
| 104 | #define CMN_PLL0_VCOCAL_PLLCNT_START 0x0088U |
| 105 | #define CMN_PLL0_INTDIV_M0 0x0090U |
| 106 | #define CMN_PLL0_FRACDIVL_M0 0x0091U |
| 107 | #define CMN_PLL0_FRACDIVH_M0 0x0092U |
| 108 | #define CMN_PLL0_HIGH_THR_M0 0x0093U |
| 109 | #define CMN_PLL0_DSM_DIAG_M0 0x0094U |
Swapnil Jakhade | 1cc4551 | 2021-07-28 16:54:51 +0200 | [diff] [blame] | 110 | #define CMN_PLL0_DSM_FBH_OVRD_M0 0x0095U |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 111 | #define CMN_PLL0_SS_CTRL1_M0 0x0098U |
| 112 | #define CMN_PLL0_SS_CTRL2_M0 0x0099U |
| 113 | #define CMN_PLL0_SS_CTRL3_M0 0x009AU |
| 114 | #define CMN_PLL0_SS_CTRL4_M0 0x009BU |
| 115 | #define CMN_PLL0_LOCK_REFCNT_START 0x009CU |
| 116 | #define CMN_PLL0_LOCK_PLLCNT_START 0x009EU |
| 117 | #define CMN_PLL0_LOCK_PLLCNT_THR 0x009FU |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 118 | #define CMN_PLL0_INTDIV_M1 0x00A0U |
| 119 | #define CMN_PLL0_FRACDIVH_M1 0x00A2U |
| 120 | #define CMN_PLL0_HIGH_THR_M1 0x00A3U |
| 121 | #define CMN_PLL0_DSM_DIAG_M1 0x00A4U |
| 122 | #define CMN_PLL0_SS_CTRL1_M1 0x00A8U |
| 123 | #define CMN_PLL0_SS_CTRL2_M1 0x00A9U |
| 124 | #define CMN_PLL0_SS_CTRL3_M1 0x00AAU |
| 125 | #define CMN_PLL0_SS_CTRL4_M1 0x00ABU |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 126 | #define CMN_PLL1_VCOCAL_TCTRL 0x00C2U |
| 127 | #define CMN_PLL1_VCOCAL_INIT_TMR 0x00C4U |
| 128 | #define CMN_PLL1_VCOCAL_ITER_TMR 0x00C5U |
| 129 | #define CMN_PLL1_VCOCAL_REFTIM_START 0x00C6U |
| 130 | #define CMN_PLL1_VCOCAL_PLLCNT_START 0x00C8U |
| 131 | #define CMN_PLL1_INTDIV_M0 0x00D0U |
| 132 | #define CMN_PLL1_FRACDIVL_M0 0x00D1U |
| 133 | #define CMN_PLL1_FRACDIVH_M0 0x00D2U |
| 134 | #define CMN_PLL1_HIGH_THR_M0 0x00D3U |
| 135 | #define CMN_PLL1_DSM_DIAG_M0 0x00D4U |
Swapnil Jakhade | e25c9db | 2021-03-04 07:08:13 +0100 | [diff] [blame] | 136 | #define CMN_PLL1_DSM_FBH_OVRD_M0 0x00D5U |
| 137 | #define CMN_PLL1_DSM_FBL_OVRD_M0 0x00D6U |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 138 | #define CMN_PLL1_SS_CTRL1_M0 0x00D8U |
| 139 | #define CMN_PLL1_SS_CTRL2_M0 0x00D9U |
| 140 | #define CMN_PLL1_SS_CTRL3_M0 0x00DAU |
| 141 | #define CMN_PLL1_SS_CTRL4_M0 0x00DBU |
| 142 | #define CMN_PLL1_LOCK_REFCNT_START 0x00DCU |
| 143 | #define CMN_PLL1_LOCK_PLLCNT_START 0x00DEU |
| 144 | #define CMN_PLL1_LOCK_PLLCNT_THR 0x00DFU |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 145 | #define CMN_TXPUCAL_TUNE 0x0103U |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 146 | #define CMN_TXPUCAL_INIT_TMR 0x0104U |
| 147 | #define CMN_TXPUCAL_ITER_TMR 0x0105U |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 148 | #define CMN_TXPDCAL_TUNE 0x010BU |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 149 | #define CMN_TXPDCAL_INIT_TMR 0x010CU |
| 150 | #define CMN_TXPDCAL_ITER_TMR 0x010DU |
| 151 | #define CMN_RXCAL_INIT_TMR 0x0114U |
| 152 | #define CMN_RXCAL_ITER_TMR 0x0115U |
| 153 | #define CMN_SD_CAL_INIT_TMR 0x0124U |
| 154 | #define CMN_SD_CAL_ITER_TMR 0x0125U |
| 155 | #define CMN_SD_CAL_REFTIM_START 0x0126U |
| 156 | #define CMN_SD_CAL_PLLCNT_START 0x0128U |
| 157 | #define CMN_PDIAG_PLL0_CTRL_M0 0x01A0U |
| 158 | #define CMN_PDIAG_PLL0_CLK_SEL_M0 0x01A1U |
| 159 | #define CMN_PDIAG_PLL0_CP_PADJ_M0 0x01A4U |
| 160 | #define CMN_PDIAG_PLL0_CP_IADJ_M0 0x01A5U |
| 161 | #define CMN_PDIAG_PLL0_FILT_PADJ_M0 0x01A6U |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 162 | #define CMN_PDIAG_PLL0_CTRL_M1 0x01B0U |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 163 | #define CMN_PDIAG_PLL0_CLK_SEL_M1 0x01B1U |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 164 | #define CMN_PDIAG_PLL0_CP_PADJ_M1 0x01B4U |
| 165 | #define CMN_PDIAG_PLL0_CP_IADJ_M1 0x01B5U |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 166 | #define CMN_PDIAG_PLL0_FILT_PADJ_M1 0x01B6U |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 167 | #define CMN_PDIAG_PLL1_CTRL_M0 0x01C0U |
| 168 | #define CMN_PDIAG_PLL1_CLK_SEL_M0 0x01C1U |
| 169 | #define CMN_PDIAG_PLL1_CP_PADJ_M0 0x01C4U |
| 170 | #define CMN_PDIAG_PLL1_CP_IADJ_M0 0x01C5U |
| 171 | #define CMN_PDIAG_PLL1_FILT_PADJ_M0 0x01C6U |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 172 | #define CMN_DIAG_BIAS_OVRD1 0x01E1U |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 173 | |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 174 | /* PMA TX Lane registers */ |
| 175 | #define TX_TXCC_CTRL 0x0040U |
| 176 | #define TX_TXCC_CPOST_MULT_00 0x004CU |
Swapnil Jakhade | 9855d84 | 2020-09-17 09:30:44 +0200 | [diff] [blame] | 177 | #define TX_TXCC_CPOST_MULT_01 0x004DU |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 178 | #define TX_TXCC_MGNFS_MULT_000 0x0050U |
Swapnil Jakhade | e25c9db | 2021-03-04 07:08:13 +0100 | [diff] [blame] | 179 | #define TX_TXCC_MGNFS_MULT_100 0x0054U |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 180 | #define DRV_DIAG_TX_DRV 0x00C6U |
| 181 | #define XCVR_DIAG_PLLDRC_CTRL 0x00E5U |
| 182 | #define XCVR_DIAG_HSCLK_SEL 0x00E6U |
| 183 | #define XCVR_DIAG_HSCLK_DIV 0x00E7U |
Kishon Vijay Abraham I | 70901a7 | 2021-03-04 07:08:15 +0100 | [diff] [blame] | 184 | #define XCVR_DIAG_RXCLK_CTRL 0x00E9U |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 185 | #define XCVR_DIAG_BIDI_CTRL 0x00EAU |
Swapnil Jakhade | 9855d84 | 2020-09-17 09:30:44 +0200 | [diff] [blame] | 186 | #define XCVR_DIAG_PSC_OVRD 0x00EBU |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 187 | #define TX_PSC_A0 0x0100U |
Swapnil Jakhade | 9855d84 | 2020-09-17 09:30:44 +0200 | [diff] [blame] | 188 | #define TX_PSC_A1 0x0101U |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 189 | #define TX_PSC_A2 0x0102U |
| 190 | #define TX_PSC_A3 0x0103U |
| 191 | #define TX_RCVDET_ST_TMR 0x0123U |
| 192 | #define TX_DIAG_ACYA 0x01E7U |
Swapnil Jakhade | 572d659 | 2020-02-06 07:10:57 +0100 | [diff] [blame] | 193 | #define TX_DIAG_ACYA_HBDC_MASK 0x0001U |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 194 | |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 195 | /* PMA RX Lane registers */ |
| 196 | #define RX_PSC_A0 0x0000U |
Swapnil Jakhade | 9855d84 | 2020-09-17 09:30:44 +0200 | [diff] [blame] | 197 | #define RX_PSC_A1 0x0001U |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 198 | #define RX_PSC_A2 0x0002U |
| 199 | #define RX_PSC_A3 0x0003U |
| 200 | #define RX_PSC_CAL 0x0006U |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 201 | #define RX_CDRLF_CNFG 0x0080U |
Swapnil Jakhade | 9855d84 | 2020-09-17 09:30:44 +0200 | [diff] [blame] | 202 | #define RX_CDRLF_CNFG3 0x0082U |
| 203 | #define RX_SIGDET_HL_FILT_TMR 0x0090U |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 204 | #define RX_REE_GCSM1_CTRL 0x0108U |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 205 | #define RX_REE_GCSM1_EQENM_PH1 0x0109U |
| 206 | #define RX_REE_GCSM1_EQENM_PH2 0x010AU |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 207 | #define RX_REE_GCSM2_CTRL 0x0110U |
| 208 | #define RX_REE_PERGCSM_CTRL 0x0118U |
Swapnil Jakhade | 9855d84 | 2020-09-17 09:30:44 +0200 | [diff] [blame] | 209 | #define RX_REE_ATTEN_THR 0x0149U |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 210 | #define RX_REE_TAP1_CLIP 0x0171U |
| 211 | #define RX_REE_TAP2TON_CLIP 0x0172U |
Swapnil Jakhade | 9855d84 | 2020-09-17 09:30:44 +0200 | [diff] [blame] | 212 | #define RX_REE_SMGM_CTRL1 0x0177U |
| 213 | #define RX_REE_SMGM_CTRL2 0x0178U |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 214 | #define RX_DIAG_DFE_CTRL 0x01E0U |
| 215 | #define RX_DIAG_DFE_AMP_TUNE_2 0x01E2U |
| 216 | #define RX_DIAG_DFE_AMP_TUNE_3 0x01E3U |
| 217 | #define RX_DIAG_NQST_CTRL 0x01E5U |
Swapnil Jakhade | 9855d84 | 2020-09-17 09:30:44 +0200 | [diff] [blame] | 218 | #define RX_DIAG_SIGDET_TUNE 0x01E8U |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 219 | #define RX_DIAG_PI_RATE 0x01F4U |
| 220 | #define RX_DIAG_PI_CAP 0x01F5U |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 221 | #define RX_DIAG_ACYA 0x01FFU |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 222 | |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 223 | /* PHY PCS common registers */ |
Kishon Vijay Abraham I | 2cca022 | 2021-03-10 17:38:40 +0530 | [diff] [blame] | 224 | #define PHY_PIPE_CMN_CTRL1 0x0000U |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 225 | #define PHY_PLL_CFG 0x000EU |
Swapnil Jakhade | 9855d84 | 2020-09-17 09:30:44 +0200 | [diff] [blame] | 226 | #define PHY_PIPE_USB3_GEN2_PRE_CFG0 0x0020U |
| 227 | #define PHY_PIPE_USB3_GEN2_POST_CFG0 0x0022U |
| 228 | #define PHY_PIPE_USB3_GEN2_POST_CFG1 0x0023U |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 229 | |
Swapnil Jakhade | 48ac608 | 2021-07-28 16:54:54 +0200 | [diff] [blame] | 230 | /* PHY PCS lane registers */ |
| 231 | #define PHY_PCS_ISO_LINK_CTRL 0x000BU |
| 232 | |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 233 | /* PHY PMA common registers */ |
Swapnil Jakhade | 8e4c95b | 2020-09-17 09:30:35 +0200 | [diff] [blame] | 234 | #define PHY_PMA_CMN_CTRL1 0x0000U |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 235 | #define PHY_PMA_CMN_CTRL2 0x0001U |
| 236 | #define PHY_PMA_PLL_RAW_CTRL 0x0003U |
| 237 | |
Swapnil Jakhade | 785a4e6 | 2021-09-22 14:37:35 +0200 | [diff] [blame] | 238 | #define CDNS_TORRENT_OUTPUT_CLOCKS 3 |
Swapnil Jakhade | aef096d | 2021-09-22 14:37:32 +0200 | [diff] [blame] | 239 | |
Kishon Vijay Abraham I | 2cca022 | 2021-03-10 17:38:40 +0530 | [diff] [blame] | 240 | static const char * const clk_names[] = { |
| 241 | [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver", |
Swapnil Jakhade | 235bde4 | 2021-09-22 14:37:34 +0200 | [diff] [blame] | 242 | [CDNS_TORRENT_DERIVED_REFCLK] = "refclk-der", |
Swapnil Jakhade | 785a4e6 | 2021-09-22 14:37:35 +0200 | [diff] [blame] | 243 | [CDNS_TORRENT_RECEIVED_REFCLK] = "refclk-rec", |
Kishon Vijay Abraham I | 2cca022 | 2021-03-10 17:38:40 +0530 | [diff] [blame] | 244 | }; |
| 245 | |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 246 | static const struct reg_field phy_pll_cfg = |
| 247 | REG_FIELD(PHY_PLL_CFG, 0, 1); |
| 248 | |
Swapnil Jakhade | 8e4c95b | 2020-09-17 09:30:35 +0200 | [diff] [blame] | 249 | static const struct reg_field phy_pma_cmn_ctrl_1 = |
| 250 | REG_FIELD(PHY_PMA_CMN_CTRL1, 0, 0); |
| 251 | |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 252 | static const struct reg_field phy_pma_cmn_ctrl_2 = |
| 253 | REG_FIELD(PHY_PMA_CMN_CTRL2, 0, 7); |
| 254 | |
| 255 | static const struct reg_field phy_pma_pll_raw_ctrl = |
| 256 | REG_FIELD(PHY_PMA_PLL_RAW_CTRL, 0, 1); |
| 257 | |
Swapnil Jakhade | cba472e | 2020-02-06 07:10:59 +0100 | [diff] [blame] | 258 | static const struct reg_field phy_reset_ctrl = |
| 259 | REG_FIELD(PHY_RESET, 8, 8); |
| 260 | |
Swapnil Jakhade | 48ac608 | 2021-07-28 16:54:54 +0200 | [diff] [blame] | 261 | static const struct reg_field phy_pcs_iso_link_ctrl_1 = |
| 262 | REG_FIELD(PHY_PCS_ISO_LINK_CTRL, 1, 1); |
| 263 | |
Kishon Vijay Abraham I | 2cca022 | 2021-03-10 17:38:40 +0530 | [diff] [blame] | 264 | static const struct reg_field phy_pipe_cmn_ctrl1_0 = REG_FIELD(PHY_PIPE_CMN_CTRL1, 0, 0); |
| 265 | |
Swapnil Jakhade | 235bde4 | 2021-09-22 14:37:34 +0200 | [diff] [blame] | 266 | static const struct reg_field cmn_cdiag_refclk_ovrd_4 = |
| 267 | REG_FIELD(CMN_CDIAG_REFCLK_OVRD, 4, 4); |
| 268 | |
| 269 | #define REFCLK_OUT_NUM_CMN_CONFIG 4 |
Kishon Vijay Abraham I | 2cca022 | 2021-03-10 17:38:40 +0530 | [diff] [blame] | 270 | |
| 271 | enum cdns_torrent_refclk_out_cmn { |
Kishon Vijay Abraham I | 2cca022 | 2021-03-10 17:38:40 +0530 | [diff] [blame] | 272 | CMN_CDIAG_REFCLK_DRV0_CTRL_1, |
| 273 | CMN_CDIAG_REFCLK_DRV0_CTRL_4, |
| 274 | CMN_CDIAG_REFCLK_DRV0_CTRL_5, |
| 275 | CMN_CDIAG_REFCLK_DRV0_CTRL_6, |
| 276 | }; |
| 277 | |
| 278 | static const struct reg_field refclk_out_cmn_cfg[] = { |
Kishon Vijay Abraham I | 2cca022 | 2021-03-10 17:38:40 +0530 | [diff] [blame] | 279 | [CMN_CDIAG_REFCLK_DRV0_CTRL_1] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 1, 1), |
| 280 | [CMN_CDIAG_REFCLK_DRV0_CTRL_4] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 4, 4), |
| 281 | [CMN_CDIAG_REFCLK_DRV0_CTRL_5] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 5, 5), |
| 282 | [CMN_CDIAG_REFCLK_DRV0_CTRL_6] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 6, 6), |
| 283 | }; |
| 284 | |
Swapnil Jakhade | 785a4e6 | 2021-09-22 14:37:35 +0200 | [diff] [blame] | 285 | static const int refclk_driver_parent_index[] = { |
| 286 | CDNS_TORRENT_DERIVED_REFCLK, |
| 287 | CDNS_TORRENT_RECEIVED_REFCLK |
| 288 | }; |
| 289 | |
| 290 | static u32 cdns_torrent_refclk_driver_mux_table[] = { 1, 0 }; |
| 291 | |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 292 | enum cdns_torrent_phy_type { |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 293 | TYPE_NONE, |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 294 | TYPE_DP, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 295 | TYPE_PCIE, |
| 296 | TYPE_SGMII, |
| 297 | TYPE_QSGMII, |
Swapnil Jakhade | 9855d84 | 2020-09-17 09:30:44 +0200 | [diff] [blame] | 298 | TYPE_USB, |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 299 | }; |
| 300 | |
Swapnil Jakhade | 3b40162 | 2021-07-28 16:54:48 +0200 | [diff] [blame] | 301 | enum cdns_torrent_ref_clk { |
| 302 | CLK_19_2_MHZ, |
| 303 | CLK_25_MHZ, |
| 304 | CLK_100_MHZ |
| 305 | }; |
| 306 | |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 307 | enum cdns_torrent_ssc_mode { |
| 308 | NO_SSC, |
| 309 | EXTERNAL_SSC, |
| 310 | INTERNAL_SSC |
| 311 | }; |
| 312 | |
Swapnil Jakhade | afa4ba0 | 2020-02-06 07:11:01 +0100 | [diff] [blame] | 313 | struct cdns_torrent_inst { |
| 314 | struct phy *phy; |
| 315 | u32 mlane; |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 316 | enum cdns_torrent_phy_type phy_type; |
Swapnil Jakhade | afa4ba0 | 2020-02-06 07:11:01 +0100 | [diff] [blame] | 317 | u32 num_lanes; |
| 318 | struct reset_control *lnk_rst; |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 319 | enum cdns_torrent_ssc_mode ssc_mode; |
Swapnil Jakhade | afa4ba0 | 2020-02-06 07:11:01 +0100 | [diff] [blame] | 320 | }; |
| 321 | |
Swapnil Jakhade | 92e9ccc | 2020-02-06 07:10:52 +0100 | [diff] [blame] | 322 | struct cdns_torrent_phy { |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 323 | void __iomem *base; /* DPTX registers base */ |
| 324 | void __iomem *sd_base; /* SD0801 registers base */ |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 325 | u32 max_bit_rate; /* Maximum link bit rate to use (in Mbps) */ |
Swapnil Jakhade | afa4ba0 | 2020-02-06 07:11:01 +0100 | [diff] [blame] | 326 | struct reset_control *phy_rst; |
Swapnil Jakhade | 15c6a04 | 2020-09-17 09:30:36 +0200 | [diff] [blame] | 327 | struct reset_control *apb_rst; |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 328 | struct device *dev; |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 329 | struct clk *clk; |
Swapnil Jakhade | 3b40162 | 2021-07-28 16:54:48 +0200 | [diff] [blame] | 330 | enum cdns_torrent_ref_clk ref_clk_rate; |
Swapnil Jakhade | afa4ba0 | 2020-02-06 07:11:01 +0100 | [diff] [blame] | 331 | struct cdns_torrent_inst phys[MAX_NUM_LANES]; |
| 332 | int nsubnodes; |
Swapnil Jakhade | 29d1fd2 | 2020-09-16 20:28:25 +0200 | [diff] [blame] | 333 | const struct cdns_torrent_data *init_data; |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 334 | struct regmap *regmap; |
| 335 | struct regmap *regmap_common_cdb; |
| 336 | struct regmap *regmap_phy_pcs_common_cdb; |
| 337 | struct regmap *regmap_phy_pma_common_cdb; |
| 338 | struct regmap *regmap_tx_lane_cdb[MAX_NUM_LANES]; |
| 339 | struct regmap *regmap_rx_lane_cdb[MAX_NUM_LANES]; |
Swapnil Jakhade | 48ac608 | 2021-07-28 16:54:54 +0200 | [diff] [blame] | 340 | struct regmap *regmap_phy_pcs_lane_cdb[MAX_NUM_LANES]; |
Swapnil Jakhade | cba472e | 2020-02-06 07:10:59 +0100 | [diff] [blame] | 341 | struct regmap *regmap_dptx_phy_reg; |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 342 | struct regmap_field *phy_pll_cfg; |
Swapnil Jakhade | 235bde4 | 2021-09-22 14:37:34 +0200 | [diff] [blame] | 343 | struct regmap_field *phy_pipe_cmn_ctrl1_0; |
| 344 | struct regmap_field *cmn_cdiag_refclk_ovrd_4; |
Swapnil Jakhade | 8e4c95b | 2020-09-17 09:30:35 +0200 | [diff] [blame] | 345 | struct regmap_field *phy_pma_cmn_ctrl_1; |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 346 | struct regmap_field *phy_pma_cmn_ctrl_2; |
| 347 | struct regmap_field *phy_pma_pll_raw_ctrl; |
Swapnil Jakhade | cba472e | 2020-02-06 07:10:59 +0100 | [diff] [blame] | 348 | struct regmap_field *phy_reset_ctrl; |
Swapnil Jakhade | 48ac608 | 2021-07-28 16:54:54 +0200 | [diff] [blame] | 349 | struct regmap_field *phy_pcs_iso_link_ctrl_1[MAX_NUM_LANES]; |
Swapnil Jakhade | aef096d | 2021-09-22 14:37:32 +0200 | [diff] [blame] | 350 | struct clk_hw_onecell_data *clk_hw_data; |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 351 | }; |
| 352 | |
Swapnil Jakhade | 21c7914 | 2020-02-06 07:10:55 +0100 | [diff] [blame] | 353 | enum phy_powerstate { |
| 354 | POWERSTATE_A0 = 0, |
| 355 | /* Powerstate A1 is unused */ |
| 356 | POWERSTATE_A2 = 2, |
| 357 | POWERSTATE_A3 = 3, |
| 358 | }; |
| 359 | |
Swapnil Jakhade | 235bde4 | 2021-09-22 14:37:34 +0200 | [diff] [blame] | 360 | struct cdns_torrent_refclk_driver { |
| 361 | struct clk_hw hw; |
| 362 | struct regmap_field *cmn_fields[REFCLK_OUT_NUM_CMN_CONFIG]; |
| 363 | struct clk_init_data clk_data; |
| 364 | }; |
| 365 | |
| 366 | #define to_cdns_torrent_refclk_driver(_hw) \ |
| 367 | container_of(_hw, struct cdns_torrent_refclk_driver, hw) |
| 368 | |
Kishon Vijay Abraham I | 2cca022 | 2021-03-10 17:38:40 +0530 | [diff] [blame] | 369 | struct cdns_torrent_derived_refclk { |
| 370 | struct clk_hw hw; |
| 371 | struct regmap_field *phy_pipe_cmn_ctrl1_0; |
Swapnil Jakhade | 235bde4 | 2021-09-22 14:37:34 +0200 | [diff] [blame] | 372 | struct regmap_field *cmn_cdiag_refclk_ovrd_4; |
Kishon Vijay Abraham I | 2cca022 | 2021-03-10 17:38:40 +0530 | [diff] [blame] | 373 | struct clk_init_data clk_data; |
| 374 | }; |
| 375 | |
| 376 | #define to_cdns_torrent_derived_refclk(_hw) \ |
| 377 | container_of(_hw, struct cdns_torrent_derived_refclk, hw) |
| 378 | |
Swapnil Jakhade | 785a4e6 | 2021-09-22 14:37:35 +0200 | [diff] [blame] | 379 | struct cdns_torrent_received_refclk { |
| 380 | struct clk_hw hw; |
| 381 | struct regmap_field *phy_pipe_cmn_ctrl1_0; |
| 382 | struct regmap_field *cmn_cdiag_refclk_ovrd_4; |
| 383 | struct clk_init_data clk_data; |
| 384 | }; |
| 385 | |
| 386 | #define to_cdns_torrent_received_refclk(_hw) \ |
| 387 | container_of(_hw, struct cdns_torrent_received_refclk, hw) |
| 388 | |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 389 | struct cdns_reg_pairs { |
| 390 | u32 val; |
| 391 | u32 off; |
| 392 | }; |
| 393 | |
| 394 | struct cdns_torrent_vals { |
| 395 | struct cdns_reg_pairs *reg_pairs; |
| 396 | u32 num_regs; |
| 397 | }; |
| 398 | |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 399 | struct cdns_torrent_data { |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 400 | u8 block_offset_shift; |
| 401 | u8 reg_offset_shift; |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 402 | struct cdns_torrent_vals *link_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] |
| 403 | [NUM_SSC_MODE]; |
| 404 | struct cdns_torrent_vals *xcvr_diag_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] |
| 405 | [NUM_SSC_MODE]; |
Swapnil Jakhade | 9855d84 | 2020-09-17 09:30:44 +0200 | [diff] [blame] | 406 | struct cdns_torrent_vals *pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] |
| 407 | [NUM_SSC_MODE]; |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 408 | struct cdns_torrent_vals *cmn_vals[NUM_REF_CLK][NUM_PHY_TYPE] |
| 409 | [NUM_PHY_TYPE][NUM_SSC_MODE]; |
| 410 | struct cdns_torrent_vals *tx_ln_vals[NUM_REF_CLK][NUM_PHY_TYPE] |
| 411 | [NUM_PHY_TYPE][NUM_SSC_MODE]; |
| 412 | struct cdns_torrent_vals *rx_ln_vals[NUM_REF_CLK][NUM_PHY_TYPE] |
| 413 | [NUM_PHY_TYPE][NUM_SSC_MODE]; |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 414 | }; |
| 415 | |
| 416 | struct cdns_regmap_cdb_context { |
| 417 | struct device *dev; |
| 418 | void __iomem *base; |
| 419 | u8 reg_offset_shift; |
| 420 | }; |
| 421 | |
| 422 | static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val) |
| 423 | { |
| 424 | struct cdns_regmap_cdb_context *ctx = context; |
| 425 | u32 offset = reg << ctx->reg_offset_shift; |
| 426 | |
| 427 | writew(val, ctx->base + offset); |
| 428 | |
| 429 | return 0; |
| 430 | } |
| 431 | |
| 432 | static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val) |
| 433 | { |
| 434 | struct cdns_regmap_cdb_context *ctx = context; |
| 435 | u32 offset = reg << ctx->reg_offset_shift; |
| 436 | |
| 437 | *val = readw(ctx->base + offset); |
| 438 | return 0; |
| 439 | } |
| 440 | |
Swapnil Jakhade | cba472e | 2020-02-06 07:10:59 +0100 | [diff] [blame] | 441 | static int cdns_regmap_dptx_write(void *context, unsigned int reg, |
| 442 | unsigned int val) |
| 443 | { |
| 444 | struct cdns_regmap_cdb_context *ctx = context; |
| 445 | u32 offset = reg; |
| 446 | |
| 447 | writel(val, ctx->base + offset); |
| 448 | |
| 449 | return 0; |
| 450 | } |
| 451 | |
| 452 | static int cdns_regmap_dptx_read(void *context, unsigned int reg, |
| 453 | unsigned int *val) |
| 454 | { |
| 455 | struct cdns_regmap_cdb_context *ctx = context; |
| 456 | u32 offset = reg; |
| 457 | |
| 458 | *val = readl(ctx->base + offset); |
| 459 | return 0; |
| 460 | } |
| 461 | |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 462 | #define TORRENT_TX_LANE_CDB_REGMAP_CONF(n) \ |
| 463 | { \ |
| 464 | .name = "torrent_tx_lane" n "_cdb", \ |
| 465 | .reg_stride = 1, \ |
| 466 | .fast_io = true, \ |
| 467 | .reg_write = cdns_regmap_write, \ |
| 468 | .reg_read = cdns_regmap_read, \ |
| 469 | } |
| 470 | |
| 471 | #define TORRENT_RX_LANE_CDB_REGMAP_CONF(n) \ |
| 472 | { \ |
| 473 | .name = "torrent_rx_lane" n "_cdb", \ |
| 474 | .reg_stride = 1, \ |
| 475 | .fast_io = true, \ |
| 476 | .reg_write = cdns_regmap_write, \ |
| 477 | .reg_read = cdns_regmap_read, \ |
| 478 | } |
| 479 | |
Rikard Falkeborn | 57d39c7 | 2020-09-12 22:46:39 +0200 | [diff] [blame] | 480 | static const struct regmap_config cdns_torrent_tx_lane_cdb_config[] = { |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 481 | TORRENT_TX_LANE_CDB_REGMAP_CONF("0"), |
| 482 | TORRENT_TX_LANE_CDB_REGMAP_CONF("1"), |
| 483 | TORRENT_TX_LANE_CDB_REGMAP_CONF("2"), |
| 484 | TORRENT_TX_LANE_CDB_REGMAP_CONF("3"), |
| 485 | }; |
| 486 | |
Rikard Falkeborn | 57d39c7 | 2020-09-12 22:46:39 +0200 | [diff] [blame] | 487 | static const struct regmap_config cdns_torrent_rx_lane_cdb_config[] = { |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 488 | TORRENT_RX_LANE_CDB_REGMAP_CONF("0"), |
| 489 | TORRENT_RX_LANE_CDB_REGMAP_CONF("1"), |
| 490 | TORRENT_RX_LANE_CDB_REGMAP_CONF("2"), |
| 491 | TORRENT_RX_LANE_CDB_REGMAP_CONF("3"), |
| 492 | }; |
| 493 | |
Rikard Falkeborn | 57d39c7 | 2020-09-12 22:46:39 +0200 | [diff] [blame] | 494 | static const struct regmap_config cdns_torrent_common_cdb_config = { |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 495 | .name = "torrent_common_cdb", |
| 496 | .reg_stride = 1, |
| 497 | .fast_io = true, |
| 498 | .reg_write = cdns_regmap_write, |
| 499 | .reg_read = cdns_regmap_read, |
| 500 | }; |
| 501 | |
Swapnil Jakhade | 48ac608 | 2021-07-28 16:54:54 +0200 | [diff] [blame] | 502 | #define TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF(n) \ |
| 503 | { \ |
| 504 | .name = "torrent_phy_pcs_lane" n "_cdb", \ |
| 505 | .reg_stride = 1, \ |
| 506 | .fast_io = true, \ |
| 507 | .reg_write = cdns_regmap_write, \ |
| 508 | .reg_read = cdns_regmap_read, \ |
| 509 | } |
| 510 | |
| 511 | static const struct regmap_config cdns_torrent_phy_pcs_lane_cdb_config[] = { |
| 512 | TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("0"), |
| 513 | TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("1"), |
| 514 | TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("2"), |
| 515 | TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("3"), |
| 516 | }; |
| 517 | |
Rikard Falkeborn | 57d39c7 | 2020-09-12 22:46:39 +0200 | [diff] [blame] | 518 | static const struct regmap_config cdns_torrent_phy_pcs_cmn_cdb_config = { |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 519 | .name = "torrent_phy_pcs_cmn_cdb", |
| 520 | .reg_stride = 1, |
| 521 | .fast_io = true, |
| 522 | .reg_write = cdns_regmap_write, |
| 523 | .reg_read = cdns_regmap_read, |
| 524 | }; |
| 525 | |
Rikard Falkeborn | 57d39c7 | 2020-09-12 22:46:39 +0200 | [diff] [blame] | 526 | static const struct regmap_config cdns_torrent_phy_pma_cmn_cdb_config = { |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 527 | .name = "torrent_phy_pma_cmn_cdb", |
| 528 | .reg_stride = 1, |
| 529 | .fast_io = true, |
| 530 | .reg_write = cdns_regmap_write, |
| 531 | .reg_read = cdns_regmap_read, |
| 532 | }; |
| 533 | |
Rikard Falkeborn | 57d39c7 | 2020-09-12 22:46:39 +0200 | [diff] [blame] | 534 | static const struct regmap_config cdns_torrent_dptx_phy_config = { |
Swapnil Jakhade | cba472e | 2020-02-06 07:10:59 +0100 | [diff] [blame] | 535 | .name = "torrent_dptx_phy", |
| 536 | .reg_stride = 1, |
| 537 | .fast_io = true, |
| 538 | .reg_write = cdns_regmap_dptx_write, |
| 539 | .reg_read = cdns_regmap_dptx_read, |
| 540 | }; |
| 541 | |
Swapnil Jakhade | ccb1b89 | 2020-02-06 07:10:53 +0100 | [diff] [blame] | 542 | /* PHY mmr access functions */ |
| 543 | |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 544 | static void cdns_torrent_phy_write(struct regmap *regmap, u32 offset, u32 val) |
Swapnil Jakhade | ccb1b89 | 2020-02-06 07:10:53 +0100 | [diff] [blame] | 545 | { |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 546 | regmap_write(regmap, offset, val); |
Swapnil Jakhade | ccb1b89 | 2020-02-06 07:10:53 +0100 | [diff] [blame] | 547 | } |
| 548 | |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 549 | static u32 cdns_torrent_phy_read(struct regmap *regmap, u32 offset) |
Swapnil Jakhade | 572d659 | 2020-02-06 07:10:57 +0100 | [diff] [blame] | 550 | { |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 551 | unsigned int val; |
Swapnil Jakhade | 572d659 | 2020-02-06 07:10:57 +0100 | [diff] [blame] | 552 | |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 553 | regmap_read(regmap, offset, &val); |
| 554 | return val; |
| 555 | } |
Swapnil Jakhade | 572d659 | 2020-02-06 07:10:57 +0100 | [diff] [blame] | 556 | |
Swapnil Jakhade | f61b3ae | 2020-02-06 07:10:54 +0100 | [diff] [blame] | 557 | /* DPTX mmr access functions */ |
| 558 | |
Swapnil Jakhade | cba472e | 2020-02-06 07:10:59 +0100 | [diff] [blame] | 559 | static void cdns_torrent_dp_write(struct regmap *regmap, u32 offset, u32 val) |
Swapnil Jakhade | f61b3ae | 2020-02-06 07:10:54 +0100 | [diff] [blame] | 560 | { |
Swapnil Jakhade | cba472e | 2020-02-06 07:10:59 +0100 | [diff] [blame] | 561 | regmap_write(regmap, offset, val); |
Swapnil Jakhade | f61b3ae | 2020-02-06 07:10:54 +0100 | [diff] [blame] | 562 | } |
| 563 | |
Swapnil Jakhade | cba472e | 2020-02-06 07:10:59 +0100 | [diff] [blame] | 564 | static u32 cdns_torrent_dp_read(struct regmap *regmap, u32 offset) |
Swapnil Jakhade | f61b3ae | 2020-02-06 07:10:54 +0100 | [diff] [blame] | 565 | { |
Swapnil Jakhade | cba472e | 2020-02-06 07:10:59 +0100 | [diff] [blame] | 566 | u32 val; |
Swapnil Jakhade | f61b3ae | 2020-02-06 07:10:54 +0100 | [diff] [blame] | 567 | |
Swapnil Jakhade | cba472e | 2020-02-06 07:10:59 +0100 | [diff] [blame] | 568 | regmap_read(regmap, offset, &val); |
| 569 | return val; |
| 570 | } |
Swapnil Jakhade | f61b3ae | 2020-02-06 07:10:54 +0100 | [diff] [blame] | 571 | |
Swapnil Jakhade | 572d659 | 2020-02-06 07:10:57 +0100 | [diff] [blame] | 572 | /* |
| 573 | * Structure used to store values of PHY registers for voltage-related |
| 574 | * coefficients, for particular voltage swing and pre-emphasis level. Values |
| 575 | * are shared across all physical lanes. |
| 576 | */ |
| 577 | struct coefficients { |
| 578 | /* Value of DRV_DIAG_TX_DRV register to use */ |
| 579 | u16 diag_tx_drv; |
| 580 | /* Value of TX_TXCC_MGNFS_MULT_000 register to use */ |
| 581 | u16 mgnfs_mult; |
| 582 | /* Value of TX_TXCC_CPOST_MULT_00 register to use */ |
| 583 | u16 cpost_mult; |
| 584 | }; |
| 585 | |
| 586 | /* |
| 587 | * Array consists of values of voltage-related registers for sd0801 PHY. A value |
| 588 | * of 0xFFFF is a placeholder for invalid combination, and will never be used. |
| 589 | */ |
| 590 | static const struct coefficients vltg_coeff[4][4] = { |
| 591 | /* voltage swing 0, pre-emphasis 0->3 */ |
| 592 | { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x002A, |
| 593 | .cpost_mult = 0x0000}, |
| 594 | {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F, |
| 595 | .cpost_mult = 0x0014}, |
| 596 | {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0012, |
| 597 | .cpost_mult = 0x0020}, |
| 598 | {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000, |
| 599 | .cpost_mult = 0x002A} |
| 600 | }, |
| 601 | |
| 602 | /* voltage swing 1, pre-emphasis 0->3 */ |
| 603 | { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F, |
| 604 | .cpost_mult = 0x0000}, |
| 605 | {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013, |
| 606 | .cpost_mult = 0x0012}, |
| 607 | {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000, |
| 608 | .cpost_mult = 0x001F}, |
| 609 | {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, |
| 610 | .cpost_mult = 0xFFFF} |
| 611 | }, |
| 612 | |
| 613 | /* voltage swing 2, pre-emphasis 0->3 */ |
| 614 | { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013, |
| 615 | .cpost_mult = 0x0000}, |
| 616 | {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000, |
| 617 | .cpost_mult = 0x0013}, |
| 618 | {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, |
| 619 | .cpost_mult = 0xFFFF}, |
| 620 | {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, |
| 621 | .cpost_mult = 0xFFFF} |
| 622 | }, |
| 623 | |
| 624 | /* voltage swing 3, pre-emphasis 0->3 */ |
| 625 | { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000, |
| 626 | .cpost_mult = 0x0000}, |
| 627 | {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, |
| 628 | .cpost_mult = 0xFFFF}, |
| 629 | {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, |
| 630 | .cpost_mult = 0xFFFF}, |
| 631 | {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, |
| 632 | .cpost_mult = 0xFFFF} |
| 633 | } |
| 634 | }; |
| 635 | |
Swapnil Jakhade | 84f55df | 2021-07-28 16:54:53 +0200 | [diff] [blame] | 636 | static const char *cdns_torrent_get_phy_type(enum cdns_torrent_phy_type phy_type) |
| 637 | { |
| 638 | switch (phy_type) { |
| 639 | case TYPE_DP: |
| 640 | return "DisplayPort"; |
| 641 | case TYPE_PCIE: |
| 642 | return "PCIe"; |
| 643 | case TYPE_SGMII: |
| 644 | return "SGMII"; |
| 645 | case TYPE_QSGMII: |
| 646 | return "QSGMII"; |
| 647 | case TYPE_USB: |
| 648 | return "USB"; |
| 649 | default: |
| 650 | return "None"; |
| 651 | } |
| 652 | } |
| 653 | |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 654 | /* |
| 655 | * Set registers responsible for enabling and configuring SSC, with second and |
| 656 | * third register values provided by parameters. |
| 657 | */ |
| 658 | static |
| 659 | void cdns_torrent_dp_enable_ssc_19_2mhz(struct cdns_torrent_phy *cdns_phy, |
| 660 | u32 ctrl2_val, u32 ctrl3_val) |
| 661 | { |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 662 | struct regmap *regmap = cdns_phy->regmap_common_cdb; |
| 663 | |
| 664 | cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001); |
| 665 | cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val); |
| 666 | cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl3_val); |
| 667 | cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003); |
| 668 | cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001); |
| 669 | cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val); |
| 670 | cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl3_val); |
| 671 | cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003); |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 672 | } |
| 673 | |
| 674 | static |
| 675 | void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy, |
| 676 | u32 rate, bool ssc) |
| 677 | { |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 678 | struct regmap *regmap = cdns_phy->regmap_common_cdb; |
| 679 | |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 680 | /* Assumes 19.2 MHz refclock */ |
| 681 | switch (rate) { |
| 682 | /* Setting VCO for 10.8GHz */ |
| 683 | case 2700: |
| 684 | case 5400: |
Swapnil Jakhade | da055e5 | 2021-07-28 16:54:50 +0200 | [diff] [blame] | 685 | cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0119); |
| 686 | cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x4000); |
| 687 | cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); |
| 688 | cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00BC); |
| 689 | cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0012); |
| 690 | cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0119); |
| 691 | cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x4000); |
| 692 | cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); |
| 693 | cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00BC); |
| 694 | cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0012); |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 695 | if (ssc) |
Swapnil Jakhade | da055e5 | 2021-07-28 16:54:50 +0200 | [diff] [blame] | 696 | cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x033A, 0x006A); |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 697 | break; |
| 698 | /* Setting VCO for 9.72GHz */ |
| 699 | case 1620: |
| 700 | case 2430: |
| 701 | case 3240: |
Swapnil Jakhade | da055e5 | 2021-07-28 16:54:50 +0200 | [diff] [blame] | 702 | cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01FA); |
| 703 | cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x4000); |
| 704 | cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); |
| 705 | cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0152); |
| 706 | cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); |
| 707 | cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01FA); |
| 708 | cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x4000); |
| 709 | cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); |
| 710 | cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0152); |
| 711 | cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 712 | if (ssc) |
Swapnil Jakhade | da055e5 | 2021-07-28 16:54:50 +0200 | [diff] [blame] | 713 | cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x05DD, 0x0069); |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 714 | break; |
| 715 | /* Setting VCO for 8.64GHz */ |
| 716 | case 2160: |
| 717 | case 4320: |
Swapnil Jakhade | da055e5 | 2021-07-28 16:54:50 +0200 | [diff] [blame] | 718 | cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01C2); |
| 719 | cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000); |
| 720 | cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); |
| 721 | cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x012C); |
| 722 | cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); |
| 723 | cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01C2); |
| 724 | cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000); |
| 725 | cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); |
| 726 | cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x012C); |
| 727 | cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 728 | if (ssc) |
Swapnil Jakhade | da055e5 | 2021-07-28 16:54:50 +0200 | [diff] [blame] | 729 | cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x0536, 0x0069); |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 730 | break; |
| 731 | /* Setting VCO for 8.1GHz */ |
| 732 | case 8100: |
Swapnil Jakhade | da055e5 | 2021-07-28 16:54:50 +0200 | [diff] [blame] | 733 | cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01A5); |
| 734 | cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xE000); |
| 735 | cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); |
| 736 | cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x011A); |
| 737 | cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); |
| 738 | cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01A5); |
| 739 | cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xE000); |
| 740 | cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); |
| 741 | cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x011A); |
| 742 | cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 743 | if (ssc) |
Swapnil Jakhade | da055e5 | 2021-07-28 16:54:50 +0200 | [diff] [blame] | 744 | cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x04D7, 0x006A); |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 745 | break; |
| 746 | } |
| 747 | |
| 748 | if (ssc) { |
Swapnil Jakhade | da055e5 | 2021-07-28 16:54:50 +0200 | [diff] [blame] | 749 | cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_PLLCNT_START, 0x025E); |
| 750 | cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_THR, 0x0005); |
| 751 | cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_PLLCNT_START, 0x025E); |
| 752 | cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_THR, 0x0005); |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 753 | } else { |
Swapnil Jakhade | da055e5 | 2021-07-28 16:54:50 +0200 | [diff] [blame] | 754 | cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_PLLCNT_START, 0x0260); |
| 755 | cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_PLLCNT_START, 0x0260); |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 756 | /* Set reset register values to disable SSC */ |
Swapnil Jakhade | da055e5 | 2021-07-28 16:54:50 +0200 | [diff] [blame] | 757 | cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002); |
| 758 | cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000); |
| 759 | cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000); |
| 760 | cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000); |
| 761 | cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_THR, 0x0003); |
| 762 | cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002); |
| 763 | cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000); |
| 764 | cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000); |
| 765 | cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000); |
| 766 | cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_THR, 0x0003); |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 767 | } |
| 768 | |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 769 | cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x0099); |
| 770 | cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x0099); |
| 771 | cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x0099); |
| 772 | cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x0099); |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 773 | } |
| 774 | |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 775 | /* |
| 776 | * Set registers responsible for enabling and configuring SSC, with second |
| 777 | * register value provided by a parameter. |
| 778 | */ |
| 779 | static void cdns_torrent_dp_enable_ssc_25mhz(struct cdns_torrent_phy *cdns_phy, |
| 780 | u32 ctrl2_val) |
| 781 | { |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 782 | struct regmap *regmap = cdns_phy->regmap_common_cdb; |
| 783 | |
| 784 | cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001); |
| 785 | cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val); |
| 786 | cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x007F); |
| 787 | cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003); |
| 788 | cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001); |
| 789 | cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val); |
| 790 | cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x007F); |
| 791 | cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003); |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 792 | } |
| 793 | |
Swapnil Jakhade | 92e9ccc | 2020-02-06 07:10:52 +0100 | [diff] [blame] | 794 | static |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 795 | void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy, |
| 796 | u32 rate, bool ssc) |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 797 | { |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 798 | struct regmap *regmap = cdns_phy->regmap_common_cdb; |
| 799 | |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 800 | /* Assumes 25 MHz refclock */ |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 801 | switch (rate) { |
Swapnil Jakhade | ccb1b89 | 2020-02-06 07:10:53 +0100 | [diff] [blame] | 802 | /* Setting VCO for 10.8GHz */ |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 803 | case 2700: |
| 804 | case 5400: |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 805 | cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01B0); |
| 806 | cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000); |
| 807 | cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); |
| 808 | cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0120); |
| 809 | cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01B0); |
| 810 | cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000); |
| 811 | cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); |
| 812 | cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0120); |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 813 | if (ssc) |
| 814 | cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x0423); |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 815 | break; |
Swapnil Jakhade | ccb1b89 | 2020-02-06 07:10:53 +0100 | [diff] [blame] | 816 | /* Setting VCO for 9.72GHz */ |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 817 | case 1620: |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 818 | case 2430: |
| 819 | case 3240: |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 820 | cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0184); |
| 821 | cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xCCCD); |
| 822 | cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); |
| 823 | cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0104); |
| 824 | cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0184); |
| 825 | cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xCCCD); |
| 826 | cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); |
| 827 | cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0104); |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 828 | if (ssc) |
| 829 | cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x03B9); |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 830 | break; |
Swapnil Jakhade | ccb1b89 | 2020-02-06 07:10:53 +0100 | [diff] [blame] | 831 | /* Setting VCO for 8.64GHz */ |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 832 | case 2160: |
| 833 | case 4320: |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 834 | cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0159); |
| 835 | cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x999A); |
| 836 | cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); |
| 837 | cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00E7); |
| 838 | cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0159); |
| 839 | cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x999A); |
| 840 | cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); |
| 841 | cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00E7); |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 842 | if (ssc) |
| 843 | cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x034F); |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 844 | break; |
Swapnil Jakhade | ccb1b89 | 2020-02-06 07:10:53 +0100 | [diff] [blame] | 845 | /* Setting VCO for 8.1GHz */ |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 846 | case 8100: |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 847 | cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0144); |
| 848 | cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000); |
| 849 | cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); |
| 850 | cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00D8); |
| 851 | cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0144); |
| 852 | cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000); |
| 853 | cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); |
| 854 | cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00D8); |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 855 | if (ssc) |
| 856 | cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x031A); |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 857 | break; |
| 858 | } |
| 859 | |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 860 | cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); |
| 861 | cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 862 | |
| 863 | if (ssc) { |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 864 | cdns_torrent_phy_write(regmap, |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 865 | CMN_PLL0_VCOCAL_PLLCNT_START, 0x0315); |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 866 | cdns_torrent_phy_write(regmap, |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 867 | CMN_PLL0_LOCK_PLLCNT_THR, 0x0005); |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 868 | cdns_torrent_phy_write(regmap, |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 869 | CMN_PLL1_VCOCAL_PLLCNT_START, 0x0315); |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 870 | cdns_torrent_phy_write(regmap, |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 871 | CMN_PLL1_LOCK_PLLCNT_THR, 0x0005); |
| 872 | } else { |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 873 | cdns_torrent_phy_write(regmap, |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 874 | CMN_PLL0_VCOCAL_PLLCNT_START, 0x0317); |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 875 | cdns_torrent_phy_write(regmap, |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 876 | CMN_PLL1_VCOCAL_PLLCNT_START, 0x0317); |
| 877 | /* Set reset register values to disable SSC */ |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 878 | cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002); |
| 879 | cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000); |
| 880 | cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000); |
| 881 | cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000); |
| 882 | cdns_torrent_phy_write(regmap, |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 883 | CMN_PLL0_LOCK_PLLCNT_THR, 0x0003); |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 884 | cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002); |
| 885 | cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000); |
| 886 | cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000); |
| 887 | cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000); |
| 888 | cdns_torrent_phy_write(regmap, |
Swapnil Jakhade | e4b496a | 2020-02-06 07:10:56 +0100 | [diff] [blame] | 889 | CMN_PLL1_LOCK_PLLCNT_THR, 0x0003); |
| 890 | } |
| 891 | |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 892 | cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x00C7); |
| 893 | cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x00C7); |
| 894 | cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x00C7); |
| 895 | cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x00C7); |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 896 | } |
| 897 | |
Swapnil Jakhade | 1cc4551 | 2021-07-28 16:54:51 +0200 | [diff] [blame] | 898 | static |
| 899 | void cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(struct cdns_torrent_phy *cdns_phy, |
| 900 | u32 rate, bool ssc) |
| 901 | { |
| 902 | struct regmap *regmap = cdns_phy->regmap_common_cdb; |
| 903 | |
| 904 | /* Assumes 100 MHz refclock */ |
| 905 | switch (rate) { |
| 906 | /* Setting VCO for 10.8GHz */ |
| 907 | case 2700: |
| 908 | case 5400: |
| 909 | cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0028); |
| 910 | cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_FBH_OVRD_M0, 0x0022); |
| 911 | cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBH_OVRD_M0, 0x0022); |
| 912 | cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBL_OVRD_M0, 0x000C); |
| 913 | break; |
| 914 | /* Setting VCO for 9.72GHz */ |
| 915 | case 1620: |
| 916 | case 2430: |
| 917 | case 3240: |
| 918 | cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004); |
| 919 | cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004); |
| 920 | cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509); |
| 921 | cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509); |
| 922 | cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00); |
| 923 | cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00); |
| 924 | cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08); |
| 925 | cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08); |
| 926 | cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0061); |
| 927 | cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0061); |
| 928 | cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x3333); |
| 929 | cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x3333); |
| 930 | cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); |
| 931 | cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); |
| 932 | cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0042); |
| 933 | cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0042); |
| 934 | cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); |
| 935 | cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); |
| 936 | break; |
| 937 | /* Setting VCO for 8.64GHz */ |
| 938 | case 2160: |
| 939 | case 4320: |
| 940 | cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004); |
| 941 | cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004); |
| 942 | cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509); |
| 943 | cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509); |
| 944 | cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00); |
| 945 | cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00); |
| 946 | cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08); |
| 947 | cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08); |
| 948 | cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0056); |
| 949 | cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0056); |
| 950 | cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x6666); |
| 951 | cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x6666); |
| 952 | cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); |
| 953 | cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); |
| 954 | cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x003A); |
| 955 | cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x003A); |
| 956 | cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); |
| 957 | cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); |
| 958 | break; |
| 959 | /* Setting VCO for 8.1GHz */ |
| 960 | case 8100: |
| 961 | cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004); |
| 962 | cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004); |
| 963 | cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509); |
| 964 | cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509); |
| 965 | cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00); |
| 966 | cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00); |
| 967 | cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08); |
| 968 | cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08); |
| 969 | cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0051); |
| 970 | cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0051); |
| 971 | cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); |
| 972 | cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); |
| 973 | cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0036); |
| 974 | cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0036); |
| 975 | cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); |
| 976 | cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); |
| 977 | break; |
| 978 | } |
| 979 | } |
| 980 | |
Swapnil Jakhade | 5b16a79 | 2021-07-28 16:54:47 +0200 | [diff] [blame] | 981 | /* |
| 982 | * Enable or disable PLL for selected lanes. |
| 983 | */ |
| 984 | static int cdns_torrent_dp_set_pll_en(struct cdns_torrent_phy *cdns_phy, |
| 985 | struct phy_configure_opts_dp *dp, |
| 986 | bool enable) |
| 987 | { |
| 988 | u32 rd_val; |
| 989 | u32 ret; |
| 990 | struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; |
| 991 | |
| 992 | /* |
| 993 | * Used to determine, which bits to check for or enable in |
| 994 | * PHY_PMA_XCVR_PLLCLK_EN register. |
| 995 | */ |
| 996 | u32 pll_bits; |
| 997 | /* Used to enable or disable lanes. */ |
| 998 | u32 pll_val; |
| 999 | |
| 1000 | /* Select values of registers and mask, depending on enabled lane |
| 1001 | * count. |
| 1002 | */ |
| 1003 | switch (dp->lanes) { |
| 1004 | /* lane 0 */ |
| 1005 | case (1): |
| 1006 | pll_bits = 0x00000001; |
| 1007 | break; |
| 1008 | /* lanes 0-1 */ |
| 1009 | case (2): |
| 1010 | pll_bits = 0x00000003; |
| 1011 | break; |
| 1012 | /* lanes 0-3, all */ |
| 1013 | default: |
| 1014 | pll_bits = 0x0000000F; |
| 1015 | break; |
| 1016 | } |
| 1017 | |
| 1018 | if (enable) |
| 1019 | pll_val = pll_bits; |
| 1020 | else |
| 1021 | pll_val = 0x00000000; |
| 1022 | |
| 1023 | cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_val); |
| 1024 | |
| 1025 | /* Wait for acknowledgment from PHY. */ |
| 1026 | ret = regmap_read_poll_timeout(regmap, |
| 1027 | PHY_PMA_XCVR_PLLCLK_EN_ACK, |
| 1028 | rd_val, |
| 1029 | (rd_val & pll_bits) == pll_val, |
| 1030 | 0, POLL_TIMEOUT_US); |
| 1031 | ndelay(100); |
| 1032 | return ret; |
| 1033 | } |
| 1034 | |
Swapnil Jakhade | 21c7914 | 2020-02-06 07:10:55 +0100 | [diff] [blame] | 1035 | static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy, |
| 1036 | u32 num_lanes, |
| 1037 | enum phy_powerstate powerstate) |
| 1038 | { |
| 1039 | /* Register value for power state for a single byte. */ |
| 1040 | u32 value_part; |
| 1041 | u32 value; |
| 1042 | u32 mask; |
| 1043 | u32 read_val; |
| 1044 | u32 ret; |
Swapnil Jakhade | cba472e | 2020-02-06 07:10:59 +0100 | [diff] [blame] | 1045 | struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; |
Swapnil Jakhade | 21c7914 | 2020-02-06 07:10:55 +0100 | [diff] [blame] | 1046 | |
| 1047 | switch (powerstate) { |
| 1048 | case (POWERSTATE_A0): |
| 1049 | value_part = 0x01U; |
| 1050 | break; |
| 1051 | case (POWERSTATE_A2): |
| 1052 | value_part = 0x04U; |
| 1053 | break; |
| 1054 | default: |
| 1055 | /* Powerstate A3 */ |
| 1056 | value_part = 0x08U; |
| 1057 | break; |
| 1058 | } |
| 1059 | |
| 1060 | /* Select values of registers and mask, depending on enabled |
| 1061 | * lane count. |
| 1062 | */ |
| 1063 | switch (num_lanes) { |
| 1064 | /* lane 0 */ |
| 1065 | case (1): |
| 1066 | value = value_part; |
| 1067 | mask = 0x0000003FU; |
| 1068 | break; |
| 1069 | /* lanes 0-1 */ |
| 1070 | case (2): |
| 1071 | value = (value_part |
| 1072 | | (value_part << 8)); |
| 1073 | mask = 0x00003F3FU; |
| 1074 | break; |
| 1075 | /* lanes 0-3, all */ |
| 1076 | default: |
| 1077 | value = (value_part |
| 1078 | | (value_part << 8) |
| 1079 | | (value_part << 16) |
| 1080 | | (value_part << 24)); |
| 1081 | mask = 0x3F3F3F3FU; |
| 1082 | break; |
| 1083 | } |
| 1084 | |
| 1085 | /* Set power state A<n>. */ |
Swapnil Jakhade | cba472e | 2020-02-06 07:10:59 +0100 | [diff] [blame] | 1086 | cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, value); |
Swapnil Jakhade | 21c7914 | 2020-02-06 07:10:55 +0100 | [diff] [blame] | 1087 | /* Wait, until PHY acknowledges power state completion. */ |
Swapnil Jakhade | cba472e | 2020-02-06 07:10:59 +0100 | [diff] [blame] | 1088 | ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_POWER_STATE_ACK, |
| 1089 | read_val, (read_val & mask) == value, 0, |
| 1090 | POLL_TIMEOUT_US); |
| 1091 | cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, 0x00000000); |
Swapnil Jakhade | 21c7914 | 2020-02-06 07:10:55 +0100 | [diff] [blame] | 1092 | ndelay(100); |
| 1093 | |
| 1094 | return ret; |
| 1095 | } |
| 1096 | |
Swapnil Jakhade | 572d659 | 2020-02-06 07:10:57 +0100 | [diff] [blame] | 1097 | static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, u32 num_lanes) |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 1098 | { |
| 1099 | unsigned int read_val; |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 1100 | int ret; |
Swapnil Jakhade | cba472e | 2020-02-06 07:10:59 +0100 | [diff] [blame] | 1101 | struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 1102 | |
| 1103 | /* |
| 1104 | * waiting for ACK of pma_xcvr_pllclk_en_ln_*, only for the |
| 1105 | * master lane |
| 1106 | */ |
Swapnil Jakhade | cba472e | 2020-02-06 07:10:59 +0100 | [diff] [blame] | 1107 | ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_PLLCLK_EN_ACK, |
| 1108 | read_val, read_val & 1, |
| 1109 | 0, POLL_TIMEOUT_US); |
Swapnil Jakhade | 21c7914 | 2020-02-06 07:10:55 +0100 | [diff] [blame] | 1110 | if (ret == -ETIMEDOUT) { |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 1111 | dev_err(cdns_phy->dev, |
| 1112 | "timeout waiting for link PLL clock enable ack\n"); |
Swapnil Jakhade | 21c7914 | 2020-02-06 07:10:55 +0100 | [diff] [blame] | 1113 | return ret; |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 1114 | } |
| 1115 | |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 1116 | ndelay(100); |
| 1117 | |
Swapnil Jakhade | 572d659 | 2020-02-06 07:10:57 +0100 | [diff] [blame] | 1118 | ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes, |
Swapnil Jakhade | 21c7914 | 2020-02-06 07:10:55 +0100 | [diff] [blame] | 1119 | POWERSTATE_A2); |
| 1120 | if (ret) |
| 1121 | return ret; |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 1122 | |
Swapnil Jakhade | 572d659 | 2020-02-06 07:10:57 +0100 | [diff] [blame] | 1123 | ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes, |
Swapnil Jakhade | 21c7914 | 2020-02-06 07:10:55 +0100 | [diff] [blame] | 1124 | POWERSTATE_A0); |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 1125 | |
Swapnil Jakhade | 21c7914 | 2020-02-06 07:10:55 +0100 | [diff] [blame] | 1126 | return ret; |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 1127 | } |
| 1128 | |
Swapnil Jakhade | 5b16a79 | 2021-07-28 16:54:47 +0200 | [diff] [blame] | 1129 | static int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy) |
| 1130 | { |
| 1131 | unsigned int reg; |
| 1132 | int ret; |
| 1133 | struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; |
| 1134 | |
| 1135 | ret = regmap_read_poll_timeout(regmap, PHY_PMA_CMN_READY, reg, |
| 1136 | reg & 1, 0, POLL_TIMEOUT_US); |
| 1137 | if (ret == -ETIMEDOUT) { |
| 1138 | dev_err(cdns_phy->dev, |
| 1139 | "timeout waiting for PMA common ready\n"); |
| 1140 | return -ETIMEDOUT; |
| 1141 | } |
| 1142 | |
| 1143 | return 0; |
| 1144 | } |
| 1145 | |
| 1146 | static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy, |
| 1147 | u32 rate, u32 num_lanes) |
| 1148 | { |
| 1149 | unsigned int clk_sel_val = 0; |
| 1150 | unsigned int hsclk_div_val = 0; |
| 1151 | unsigned int i; |
| 1152 | |
Swapnil Jakhade | 5b16a79 | 2021-07-28 16:54:47 +0200 | [diff] [blame] | 1153 | switch (rate) { |
| 1154 | case 1620: |
| 1155 | clk_sel_val = 0x0f01; |
| 1156 | hsclk_div_val = 2; |
| 1157 | break; |
| 1158 | case 2160: |
| 1159 | case 2430: |
| 1160 | case 2700: |
| 1161 | clk_sel_val = 0x0701; |
| 1162 | hsclk_div_val = 1; |
| 1163 | break; |
| 1164 | case 3240: |
| 1165 | clk_sel_val = 0x0b00; |
| 1166 | hsclk_div_val = 2; |
| 1167 | break; |
| 1168 | case 4320: |
| 1169 | case 5400: |
| 1170 | clk_sel_val = 0x0301; |
| 1171 | hsclk_div_val = 0; |
| 1172 | break; |
| 1173 | case 8100: |
| 1174 | clk_sel_val = 0x0200; |
| 1175 | hsclk_div_val = 0; |
| 1176 | break; |
| 1177 | } |
| 1178 | |
| 1179 | cdns_torrent_phy_write(cdns_phy->regmap_common_cdb, |
| 1180 | CMN_PDIAG_PLL0_CLK_SEL_M0, clk_sel_val); |
| 1181 | cdns_torrent_phy_write(cdns_phy->regmap_common_cdb, |
| 1182 | CMN_PDIAG_PLL1_CLK_SEL_M0, clk_sel_val); |
| 1183 | |
| 1184 | /* PMA lane configuration to deal with multi-link operation */ |
| 1185 | for (i = 0; i < num_lanes; i++) |
| 1186 | cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[i], |
| 1187 | XCVR_DIAG_HSCLK_DIV, hsclk_div_val); |
| 1188 | } |
| 1189 | |
| 1190 | /* |
| 1191 | * Perform register operations related to setting link rate, once powerstate is |
| 1192 | * set and PLL disable request was processed. |
| 1193 | */ |
| 1194 | static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy, |
| 1195 | struct phy_configure_opts_dp *dp) |
| 1196 | { |
Swapnil Jakhade | da055e5 | 2021-07-28 16:54:50 +0200 | [diff] [blame] | 1197 | u32 read_val, ret; |
Swapnil Jakhade | 5b16a79 | 2021-07-28 16:54:47 +0200 | [diff] [blame] | 1198 | |
| 1199 | /* Disable the cmn_pll0_en before re-programming the new data rate. */ |
| 1200 | regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, 0x0); |
| 1201 | |
| 1202 | /* |
| 1203 | * Wait for PLL ready de-assertion. |
| 1204 | * For PLL0 - PHY_PMA_CMN_CTRL2[2] == 1 |
| 1205 | */ |
| 1206 | ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2, |
| 1207 | read_val, |
| 1208 | ((read_val >> 2) & 0x01) != 0, |
| 1209 | 0, POLL_TIMEOUT_US); |
| 1210 | if (ret) |
| 1211 | return ret; |
| 1212 | ndelay(200); |
| 1213 | |
| 1214 | /* DP Rate Change - VCO Output settings. */ |
Swapnil Jakhade | da055e5 | 2021-07-28 16:54:50 +0200 | [diff] [blame] | 1215 | if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ) |
Swapnil Jakhade | 5b16a79 | 2021-07-28 16:54:47 +0200 | [diff] [blame] | 1216 | /* PMA common configuration 19.2MHz */ |
Swapnil Jakhade | da055e5 | 2021-07-28 16:54:50 +0200 | [diff] [blame] | 1217 | cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, dp->link_rate, dp->ssc); |
| 1218 | else if (cdns_phy->ref_clk_rate == CLK_25_MHZ) |
Swapnil Jakhade | 5b16a79 | 2021-07-28 16:54:47 +0200 | [diff] [blame] | 1219 | /* PMA common configuration 25MHz */ |
Swapnil Jakhade | da055e5 | 2021-07-28 16:54:50 +0200 | [diff] [blame] | 1220 | cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate, dp->ssc); |
Swapnil Jakhade | 1cc4551 | 2021-07-28 16:54:51 +0200 | [diff] [blame] | 1221 | else if (cdns_phy->ref_clk_rate == CLK_100_MHZ) |
| 1222 | /* PMA common configuration 100MHz */ |
| 1223 | cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(cdns_phy, dp->link_rate, dp->ssc); |
| 1224 | |
Swapnil Jakhade | 5b16a79 | 2021-07-28 16:54:47 +0200 | [diff] [blame] | 1225 | cdns_torrent_dp_pma_cmn_rate(cdns_phy, dp->link_rate, dp->lanes); |
| 1226 | |
| 1227 | /* Enable the cmn_pll0_en. */ |
| 1228 | regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, 0x3); |
| 1229 | |
| 1230 | /* |
| 1231 | * Wait for PLL ready assertion. |
| 1232 | * For PLL0 - PHY_PMA_CMN_CTRL2[0] == 1 |
| 1233 | */ |
| 1234 | ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2, |
| 1235 | read_val, |
| 1236 | (read_val & 0x01) != 0, |
| 1237 | 0, POLL_TIMEOUT_US); |
| 1238 | return ret; |
| 1239 | } |
| 1240 | |
| 1241 | /* |
| 1242 | * Verify, that parameters to configure PHY with are correct. |
| 1243 | */ |
| 1244 | static int cdns_torrent_dp_verify_config(struct cdns_torrent_inst *inst, |
| 1245 | struct phy_configure_opts_dp *dp) |
| 1246 | { |
| 1247 | u8 i; |
| 1248 | |
| 1249 | /* If changing link rate was required, verify it's supported. */ |
| 1250 | if (dp->set_rate) { |
| 1251 | switch (dp->link_rate) { |
| 1252 | case 1620: |
| 1253 | case 2160: |
| 1254 | case 2430: |
| 1255 | case 2700: |
| 1256 | case 3240: |
| 1257 | case 4320: |
| 1258 | case 5400: |
| 1259 | case 8100: |
| 1260 | /* valid bit rate */ |
| 1261 | break; |
| 1262 | default: |
| 1263 | return -EINVAL; |
| 1264 | } |
| 1265 | } |
| 1266 | |
| 1267 | /* Verify lane count. */ |
| 1268 | switch (dp->lanes) { |
| 1269 | case 1: |
| 1270 | case 2: |
| 1271 | case 4: |
| 1272 | /* valid lane count. */ |
| 1273 | break; |
| 1274 | default: |
| 1275 | return -EINVAL; |
| 1276 | } |
| 1277 | |
| 1278 | /* Check against actual number of PHY's lanes. */ |
| 1279 | if (dp->lanes > inst->num_lanes) |
| 1280 | return -EINVAL; |
| 1281 | |
| 1282 | /* |
| 1283 | * If changing voltages is required, check swing and pre-emphasis |
| 1284 | * levels, per-lane. |
| 1285 | */ |
| 1286 | if (dp->set_voltages) { |
| 1287 | /* Lane count verified previously. */ |
| 1288 | for (i = 0; i < dp->lanes; i++) { |
| 1289 | if (dp->voltage[i] > 3 || dp->pre[i] > 3) |
| 1290 | return -EINVAL; |
| 1291 | |
| 1292 | /* Sum of voltage swing and pre-emphasis levels cannot |
| 1293 | * exceed 3. |
| 1294 | */ |
| 1295 | if (dp->voltage[i] + dp->pre[i] > 3) |
| 1296 | return -EINVAL; |
| 1297 | } |
| 1298 | } |
| 1299 | |
| 1300 | return 0; |
| 1301 | } |
| 1302 | |
| 1303 | /* Set power state A0 and PLL clock enable to 0 on enabled lanes. */ |
| 1304 | static void cdns_torrent_dp_set_a0_pll(struct cdns_torrent_phy *cdns_phy, |
| 1305 | u32 num_lanes) |
| 1306 | { |
| 1307 | struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; |
| 1308 | u32 pwr_state = cdns_torrent_dp_read(regmap, |
| 1309 | PHY_PMA_XCVR_POWER_STATE_REQ); |
| 1310 | u32 pll_clk_en = cdns_torrent_dp_read(regmap, |
| 1311 | PHY_PMA_XCVR_PLLCLK_EN); |
| 1312 | |
| 1313 | /* Lane 0 is always enabled. */ |
| 1314 | pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK << |
| 1315 | PHY_POWER_STATE_LN_0); |
| 1316 | pll_clk_en &= ~0x01U; |
| 1317 | |
| 1318 | if (num_lanes > 1) { |
| 1319 | /* lane 1 */ |
| 1320 | pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK << |
| 1321 | PHY_POWER_STATE_LN_1); |
| 1322 | pll_clk_en &= ~(0x01U << 1); |
| 1323 | } |
| 1324 | |
| 1325 | if (num_lanes > 2) { |
| 1326 | /* lanes 2 and 3 */ |
| 1327 | pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK << |
| 1328 | PHY_POWER_STATE_LN_2); |
| 1329 | pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK << |
| 1330 | PHY_POWER_STATE_LN_3); |
| 1331 | pll_clk_en &= ~(0x01U << 2); |
| 1332 | pll_clk_en &= ~(0x01U << 3); |
| 1333 | } |
| 1334 | |
| 1335 | cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, pwr_state); |
| 1336 | cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_clk_en); |
| 1337 | } |
| 1338 | |
| 1339 | /* Configure lane count as required. */ |
| 1340 | static int cdns_torrent_dp_set_lanes(struct cdns_torrent_phy *cdns_phy, |
| 1341 | struct phy_configure_opts_dp *dp) |
| 1342 | { |
| 1343 | u32 value; |
| 1344 | u32 ret; |
| 1345 | struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; |
| 1346 | u8 lane_mask = (1 << dp->lanes) - 1; |
| 1347 | |
| 1348 | value = cdns_torrent_dp_read(regmap, PHY_RESET); |
| 1349 | /* clear pma_tx_elec_idle_ln_* bits. */ |
| 1350 | value &= ~PMA_TX_ELEC_IDLE_MASK; |
| 1351 | /* Assert pma_tx_elec_idle_ln_* for disabled lanes. */ |
| 1352 | value |= ((~lane_mask) << PMA_TX_ELEC_IDLE_SHIFT) & |
| 1353 | PMA_TX_ELEC_IDLE_MASK; |
| 1354 | cdns_torrent_dp_write(regmap, PHY_RESET, value); |
| 1355 | |
| 1356 | /* reset the link by asserting phy_l00_reset_n low */ |
| 1357 | cdns_torrent_dp_write(regmap, PHY_RESET, |
| 1358 | value & (~PHY_L00_RESET_N_MASK)); |
| 1359 | |
| 1360 | /* |
| 1361 | * Assert lane reset on unused lanes and lane 0 so they remain in reset |
| 1362 | * and powered down when re-enabling the link |
| 1363 | */ |
| 1364 | value = (value & 0x0000FFF0) | (0x0000000E & lane_mask); |
| 1365 | cdns_torrent_dp_write(regmap, PHY_RESET, value); |
| 1366 | |
| 1367 | cdns_torrent_dp_set_a0_pll(cdns_phy, dp->lanes); |
| 1368 | |
| 1369 | /* release phy_l0*_reset_n based on used laneCount */ |
| 1370 | value = (value & 0x0000FFF0) | (0x0000000F & lane_mask); |
| 1371 | cdns_torrent_dp_write(regmap, PHY_RESET, value); |
| 1372 | |
| 1373 | /* Wait, until PHY gets ready after releasing PHY reset signal. */ |
| 1374 | ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy); |
| 1375 | if (ret) |
| 1376 | return ret; |
| 1377 | |
| 1378 | ndelay(100); |
| 1379 | |
| 1380 | /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */ |
| 1381 | cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, 0x0001); |
| 1382 | |
| 1383 | ret = cdns_torrent_dp_run(cdns_phy, dp->lanes); |
| 1384 | |
| 1385 | return ret; |
| 1386 | } |
| 1387 | |
| 1388 | /* Configure link rate as required. */ |
| 1389 | static int cdns_torrent_dp_set_rate(struct cdns_torrent_phy *cdns_phy, |
| 1390 | struct phy_configure_opts_dp *dp) |
| 1391 | { |
| 1392 | u32 ret; |
| 1393 | |
| 1394 | ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes, |
| 1395 | POWERSTATE_A3); |
| 1396 | if (ret) |
| 1397 | return ret; |
| 1398 | ret = cdns_torrent_dp_set_pll_en(cdns_phy, dp, false); |
| 1399 | if (ret) |
| 1400 | return ret; |
| 1401 | ndelay(200); |
| 1402 | |
| 1403 | ret = cdns_torrent_dp_configure_rate(cdns_phy, dp); |
| 1404 | if (ret) |
| 1405 | return ret; |
| 1406 | ndelay(200); |
| 1407 | |
| 1408 | ret = cdns_torrent_dp_set_pll_en(cdns_phy, dp, true); |
| 1409 | if (ret) |
| 1410 | return ret; |
| 1411 | ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes, |
| 1412 | POWERSTATE_A2); |
| 1413 | if (ret) |
| 1414 | return ret; |
| 1415 | ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes, |
| 1416 | POWERSTATE_A0); |
| 1417 | if (ret) |
| 1418 | return ret; |
| 1419 | ndelay(900); |
| 1420 | |
| 1421 | return ret; |
| 1422 | } |
| 1423 | |
| 1424 | /* Configure voltage swing and pre-emphasis for all enabled lanes. */ |
| 1425 | static void cdns_torrent_dp_set_voltages(struct cdns_torrent_phy *cdns_phy, |
| 1426 | struct phy_configure_opts_dp *dp) |
| 1427 | { |
| 1428 | u8 lane; |
| 1429 | u16 val; |
| 1430 | |
| 1431 | for (lane = 0; lane < dp->lanes; lane++) { |
| 1432 | val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[lane], |
| 1433 | TX_DIAG_ACYA); |
| 1434 | /* |
| 1435 | * Write 1 to register bit TX_DIAG_ACYA[0] to freeze the |
| 1436 | * current state of the analog TX driver. |
| 1437 | */ |
| 1438 | val |= TX_DIAG_ACYA_HBDC_MASK; |
| 1439 | cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], |
| 1440 | TX_DIAG_ACYA, val); |
| 1441 | |
| 1442 | cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], |
| 1443 | TX_TXCC_CTRL, 0x08A4); |
| 1444 | val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].diag_tx_drv; |
| 1445 | cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], |
| 1446 | DRV_DIAG_TX_DRV, val); |
| 1447 | val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].mgnfs_mult; |
| 1448 | cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], |
| 1449 | TX_TXCC_MGNFS_MULT_000, |
| 1450 | val); |
| 1451 | val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].cpost_mult; |
| 1452 | cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], |
| 1453 | TX_TXCC_CPOST_MULT_00, |
| 1454 | val); |
| 1455 | |
| 1456 | val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[lane], |
| 1457 | TX_DIAG_ACYA); |
| 1458 | /* |
| 1459 | * Write 0 to register bit TX_DIAG_ACYA[0] to allow the state of |
| 1460 | * analog TX driver to reflect the new programmed one. |
| 1461 | */ |
| 1462 | val &= ~TX_DIAG_ACYA_HBDC_MASK; |
| 1463 | cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], |
| 1464 | TX_DIAG_ACYA, val); |
| 1465 | } |
| 1466 | }; |
| 1467 | |
| 1468 | static int cdns_torrent_dp_configure(struct phy *phy, |
| 1469 | union phy_configure_opts *opts) |
| 1470 | { |
| 1471 | struct cdns_torrent_inst *inst = phy_get_drvdata(phy); |
| 1472 | struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); |
| 1473 | int ret; |
| 1474 | |
| 1475 | ret = cdns_torrent_dp_verify_config(inst, &opts->dp); |
| 1476 | if (ret) { |
| 1477 | dev_err(&phy->dev, "invalid params for phy configure\n"); |
| 1478 | return ret; |
| 1479 | } |
| 1480 | |
| 1481 | if (opts->dp.set_lanes) { |
| 1482 | ret = cdns_torrent_dp_set_lanes(cdns_phy, &opts->dp); |
| 1483 | if (ret) { |
| 1484 | dev_err(&phy->dev, "cdns_torrent_dp_set_lanes failed\n"); |
| 1485 | return ret; |
| 1486 | } |
| 1487 | } |
| 1488 | |
| 1489 | if (opts->dp.set_rate) { |
| 1490 | ret = cdns_torrent_dp_set_rate(cdns_phy, &opts->dp); |
| 1491 | if (ret) { |
| 1492 | dev_err(&phy->dev, "cdns_torrent_dp_set_rate failed\n"); |
| 1493 | return ret; |
| 1494 | } |
| 1495 | } |
| 1496 | |
| 1497 | if (opts->dp.set_voltages) |
| 1498 | cdns_torrent_dp_set_voltages(cdns_phy, &opts->dp); |
| 1499 | |
| 1500 | return ret; |
| 1501 | } |
| 1502 | |
| 1503 | static int cdns_torrent_phy_on(struct phy *phy) |
| 1504 | { |
| 1505 | struct cdns_torrent_inst *inst = phy_get_drvdata(phy); |
| 1506 | struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); |
| 1507 | u32 read_val; |
| 1508 | int ret; |
| 1509 | |
| 1510 | if (cdns_phy->nsubnodes == 1) { |
| 1511 | /* Take the PHY lane group out of reset */ |
| 1512 | reset_control_deassert(inst->lnk_rst); |
| 1513 | |
| 1514 | /* Take the PHY out of reset */ |
| 1515 | ret = reset_control_deassert(cdns_phy->phy_rst); |
| 1516 | if (ret) |
| 1517 | return ret; |
| 1518 | } |
| 1519 | |
| 1520 | /* |
| 1521 | * Wait for cmn_ready assertion |
| 1522 | * PHY_PMA_CMN_CTRL1[0] == 1 |
| 1523 | */ |
| 1524 | ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_1, |
| 1525 | read_val, read_val, 1000, |
| 1526 | PLL_LOCK_TIMEOUT); |
| 1527 | if (ret) { |
| 1528 | dev_err(cdns_phy->dev, "Timeout waiting for CMN ready\n"); |
| 1529 | return ret; |
| 1530 | } |
| 1531 | |
Swapnil Jakhade | 48ac608 | 2021-07-28 16:54:54 +0200 | [diff] [blame] | 1532 | if (inst->phy_type == TYPE_PCIE || inst->phy_type == TYPE_USB) { |
| 1533 | ret = regmap_field_read_poll_timeout(cdns_phy->phy_pcs_iso_link_ctrl_1[inst->mlane], |
| 1534 | read_val, !read_val, 1000, |
| 1535 | PLL_LOCK_TIMEOUT); |
| 1536 | if (ret == -ETIMEDOUT) { |
| 1537 | dev_err(cdns_phy->dev, "Timeout waiting for PHY status ready\n"); |
| 1538 | return ret; |
| 1539 | } |
| 1540 | } |
Swapnil Jakhade | 5b16a79 | 2021-07-28 16:54:47 +0200 | [diff] [blame] | 1541 | |
| 1542 | return 0; |
| 1543 | } |
| 1544 | |
| 1545 | static int cdns_torrent_phy_off(struct phy *phy) |
| 1546 | { |
| 1547 | struct cdns_torrent_inst *inst = phy_get_drvdata(phy); |
| 1548 | struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); |
| 1549 | int ret; |
| 1550 | |
| 1551 | if (cdns_phy->nsubnodes != 1) |
| 1552 | return 0; |
| 1553 | |
| 1554 | ret = reset_control_assert(cdns_phy->phy_rst); |
| 1555 | if (ret) |
| 1556 | return ret; |
| 1557 | |
| 1558 | return reset_control_assert(inst->lnk_rst); |
| 1559 | } |
| 1560 | |
Swapnil Jakhade | 8f3ced2 | 2021-07-28 16:54:52 +0200 | [diff] [blame] | 1561 | static void cdns_torrent_dp_common_init(struct cdns_torrent_phy *cdns_phy, |
| 1562 | struct cdns_torrent_inst *inst) |
Swapnil Jakhade | 5b16a79 | 2021-07-28 16:54:47 +0200 | [diff] [blame] | 1563 | { |
Swapnil Jakhade | 5b16a79 | 2021-07-28 16:54:47 +0200 | [diff] [blame] | 1564 | struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; |
Swapnil Jakhade | 8f3ced2 | 2021-07-28 16:54:52 +0200 | [diff] [blame] | 1565 | unsigned char lane_bits; |
Swapnil Jakhade | 5b16a79 | 2021-07-28 16:54:47 +0200 | [diff] [blame] | 1566 | |
| 1567 | cdns_torrent_dp_write(regmap, PHY_AUX_CTRL, 0x0003); /* enable AUX */ |
| 1568 | |
Swapnil Jakhade | 5b16a79 | 2021-07-28 16:54:47 +0200 | [diff] [blame] | 1569 | /* |
| 1570 | * Set lines power state to A0 |
| 1571 | * Set lines pll clk enable to 0 |
| 1572 | */ |
| 1573 | cdns_torrent_dp_set_a0_pll(cdns_phy, inst->num_lanes); |
| 1574 | |
| 1575 | /* |
| 1576 | * release phy_l0*_reset_n and pma_tx_elec_idle_ln_* based on |
| 1577 | * used lanes |
| 1578 | */ |
| 1579 | lane_bits = (1 << inst->num_lanes) - 1; |
| 1580 | cdns_torrent_dp_write(regmap, PHY_RESET, |
| 1581 | ((0xF & ~lane_bits) << 4) | (0xF & lane_bits)); |
| 1582 | |
| 1583 | /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */ |
| 1584 | cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, 0x0001); |
| 1585 | |
Swapnil Jakhade | 8f3ced2 | 2021-07-28 16:54:52 +0200 | [diff] [blame] | 1586 | /* |
| 1587 | * PHY PMA registers configuration functions |
| 1588 | * Initialize PHY with max supported link rate, without SSC. |
| 1589 | */ |
Swapnil Jakhade | 3b40162 | 2021-07-28 16:54:48 +0200 | [diff] [blame] | 1590 | if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ) |
Swapnil Jakhade | 5b16a79 | 2021-07-28 16:54:47 +0200 | [diff] [blame] | 1591 | cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, |
| 1592 | cdns_phy->max_bit_rate, |
| 1593 | false); |
Swapnil Jakhade | 3b40162 | 2021-07-28 16:54:48 +0200 | [diff] [blame] | 1594 | else if (cdns_phy->ref_clk_rate == CLK_25_MHZ) |
Swapnil Jakhade | 5b16a79 | 2021-07-28 16:54:47 +0200 | [diff] [blame] | 1595 | cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, |
| 1596 | cdns_phy->max_bit_rate, |
| 1597 | false); |
Swapnil Jakhade | 1cc4551 | 2021-07-28 16:54:51 +0200 | [diff] [blame] | 1598 | else if (cdns_phy->ref_clk_rate == CLK_100_MHZ) |
| 1599 | cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(cdns_phy, |
| 1600 | cdns_phy->max_bit_rate, |
| 1601 | false); |
| 1602 | |
Swapnil Jakhade | 5b16a79 | 2021-07-28 16:54:47 +0200 | [diff] [blame] | 1603 | cdns_torrent_dp_pma_cmn_rate(cdns_phy, cdns_phy->max_bit_rate, |
| 1604 | inst->num_lanes); |
| 1605 | |
| 1606 | /* take out of reset */ |
| 1607 | regmap_field_write(cdns_phy->phy_reset_ctrl, 0x1); |
Swapnil Jakhade | 8f3ced2 | 2021-07-28 16:54:52 +0200 | [diff] [blame] | 1608 | } |
| 1609 | |
| 1610 | static int cdns_torrent_dp_start(struct cdns_torrent_phy *cdns_phy, |
| 1611 | struct cdns_torrent_inst *inst, |
| 1612 | struct phy *phy) |
| 1613 | { |
| 1614 | int ret; |
Swapnil Jakhade | 5b16a79 | 2021-07-28 16:54:47 +0200 | [diff] [blame] | 1615 | |
| 1616 | cdns_torrent_phy_on(phy); |
| 1617 | |
| 1618 | ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy); |
| 1619 | if (ret) |
| 1620 | return ret; |
| 1621 | |
| 1622 | ret = cdns_torrent_dp_run(cdns_phy, inst->num_lanes); |
| 1623 | |
| 1624 | return ret; |
| 1625 | } |
| 1626 | |
Swapnil Jakhade | 8f3ced2 | 2021-07-28 16:54:52 +0200 | [diff] [blame] | 1627 | static int cdns_torrent_dp_init(struct phy *phy) |
| 1628 | { |
| 1629 | struct cdns_torrent_inst *inst = phy_get_drvdata(phy); |
| 1630 | struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); |
| 1631 | |
| 1632 | switch (cdns_phy->ref_clk_rate) { |
| 1633 | case CLK_19_2_MHZ: |
| 1634 | case CLK_25_MHZ: |
| 1635 | case CLK_100_MHZ: |
| 1636 | /* Valid Ref Clock Rate */ |
| 1637 | break; |
| 1638 | default: |
| 1639 | dev_err(cdns_phy->dev, "Unsupported Ref Clock Rate\n"); |
| 1640 | return -EINVAL; |
| 1641 | } |
| 1642 | |
| 1643 | cdns_torrent_dp_common_init(cdns_phy, inst); |
| 1644 | |
| 1645 | return cdns_torrent_dp_start(cdns_phy, inst, phy); |
| 1646 | } |
| 1647 | |
Kishon Vijay Abraham I | 2cca022 | 2021-03-10 17:38:40 +0530 | [diff] [blame] | 1648 | static int cdns_torrent_derived_refclk_enable(struct clk_hw *hw) |
| 1649 | { |
| 1650 | struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw); |
| 1651 | |
Swapnil Jakhade | 235bde4 | 2021-09-22 14:37:34 +0200 | [diff] [blame] | 1652 | regmap_field_write(derived_refclk->cmn_cdiag_refclk_ovrd_4, 1); |
Kishon Vijay Abraham I | 2cca022 | 2021-03-10 17:38:40 +0530 | [diff] [blame] | 1653 | regmap_field_write(derived_refclk->phy_pipe_cmn_ctrl1_0, 1); |
| 1654 | |
| 1655 | return 0; |
| 1656 | } |
| 1657 | |
| 1658 | static void cdns_torrent_derived_refclk_disable(struct clk_hw *hw) |
| 1659 | { |
| 1660 | struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw); |
| 1661 | |
| 1662 | regmap_field_write(derived_refclk->phy_pipe_cmn_ctrl1_0, 0); |
Swapnil Jakhade | 235bde4 | 2021-09-22 14:37:34 +0200 | [diff] [blame] | 1663 | regmap_field_write(derived_refclk->cmn_cdiag_refclk_ovrd_4, 0); |
Kishon Vijay Abraham I | 2cca022 | 2021-03-10 17:38:40 +0530 | [diff] [blame] | 1664 | } |
| 1665 | |
| 1666 | static int cdns_torrent_derived_refclk_is_enabled(struct clk_hw *hw) |
| 1667 | { |
| 1668 | struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw); |
| 1669 | int val; |
| 1670 | |
Swapnil Jakhade | 235bde4 | 2021-09-22 14:37:34 +0200 | [diff] [blame] | 1671 | regmap_field_read(derived_refclk->cmn_cdiag_refclk_ovrd_4, &val); |
Kishon Vijay Abraham I | 2cca022 | 2021-03-10 17:38:40 +0530 | [diff] [blame] | 1672 | |
| 1673 | return !!val; |
| 1674 | } |
| 1675 | |
| 1676 | static const struct clk_ops cdns_torrent_derived_refclk_ops = { |
| 1677 | .enable = cdns_torrent_derived_refclk_enable, |
| 1678 | .disable = cdns_torrent_derived_refclk_disable, |
| 1679 | .is_enabled = cdns_torrent_derived_refclk_is_enabled, |
| 1680 | }; |
| 1681 | |
| 1682 | static int cdns_torrent_derived_refclk_register(struct cdns_torrent_phy *cdns_phy) |
| 1683 | { |
| 1684 | struct cdns_torrent_derived_refclk *derived_refclk; |
| 1685 | struct device *dev = cdns_phy->dev; |
Kishon Vijay Abraham I | 2cca022 | 2021-03-10 17:38:40 +0530 | [diff] [blame] | 1686 | struct clk_init_data *init; |
| 1687 | const char *parent_name; |
Kishon Vijay Abraham I | 2cca022 | 2021-03-10 17:38:40 +0530 | [diff] [blame] | 1688 | char clk_name[100]; |
Swapnil Jakhade | aef096d | 2021-09-22 14:37:32 +0200 | [diff] [blame] | 1689 | struct clk_hw *hw; |
Kishon Vijay Abraham I | 2cca022 | 2021-03-10 17:38:40 +0530 | [diff] [blame] | 1690 | struct clk *clk; |
Swapnil Jakhade | 235bde4 | 2021-09-22 14:37:34 +0200 | [diff] [blame] | 1691 | int ret; |
Kishon Vijay Abraham I | 2cca022 | 2021-03-10 17:38:40 +0530 | [diff] [blame] | 1692 | |
| 1693 | derived_refclk = devm_kzalloc(dev, sizeof(*derived_refclk), GFP_KERNEL); |
| 1694 | if (!derived_refclk) |
| 1695 | return -ENOMEM; |
| 1696 | |
| 1697 | snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), |
Swapnil Jakhade | 235bde4 | 2021-09-22 14:37:34 +0200 | [diff] [blame] | 1698 | clk_names[CDNS_TORRENT_DERIVED_REFCLK]); |
Kishon Vijay Abraham I | 2cca022 | 2021-03-10 17:38:40 +0530 | [diff] [blame] | 1699 | |
| 1700 | clk = devm_clk_get_optional(dev, "phy_en_refclk"); |
| 1701 | if (IS_ERR(clk)) { |
| 1702 | dev_err(dev, "No parent clock for derived_refclk\n"); |
| 1703 | return PTR_ERR(clk); |
| 1704 | } |
| 1705 | |
| 1706 | init = &derived_refclk->clk_data; |
| 1707 | |
| 1708 | if (clk) { |
| 1709 | parent_name = __clk_get_name(clk); |
| 1710 | init->parent_names = &parent_name; |
| 1711 | init->num_parents = 1; |
| 1712 | } |
| 1713 | init->ops = &cdns_torrent_derived_refclk_ops; |
| 1714 | init->flags = 0; |
| 1715 | init->name = clk_name; |
| 1716 | |
Swapnil Jakhade | 235bde4 | 2021-09-22 14:37:34 +0200 | [diff] [blame] | 1717 | derived_refclk->phy_pipe_cmn_ctrl1_0 = cdns_phy->phy_pipe_cmn_ctrl1_0; |
| 1718 | derived_refclk->cmn_cdiag_refclk_ovrd_4 = cdns_phy->cmn_cdiag_refclk_ovrd_4; |
Kishon Vijay Abraham I | 2cca022 | 2021-03-10 17:38:40 +0530 | [diff] [blame] | 1719 | |
| 1720 | derived_refclk->hw.init = init; |
| 1721 | |
Swapnil Jakhade | aef096d | 2021-09-22 14:37:32 +0200 | [diff] [blame] | 1722 | hw = &derived_refclk->hw; |
| 1723 | ret = devm_clk_hw_register(dev, hw); |
| 1724 | if (ret) |
| 1725 | return ret; |
Kishon Vijay Abraham I | 2cca022 | 2021-03-10 17:38:40 +0530 | [diff] [blame] | 1726 | |
Swapnil Jakhade | 235bde4 | 2021-09-22 14:37:34 +0200 | [diff] [blame] | 1727 | cdns_phy->clk_hw_data->hws[CDNS_TORRENT_DERIVED_REFCLK] = hw; |
| 1728 | |
| 1729 | return 0; |
| 1730 | } |
| 1731 | |
Swapnil Jakhade | 785a4e6 | 2021-09-22 14:37:35 +0200 | [diff] [blame] | 1732 | static int cdns_torrent_received_refclk_enable(struct clk_hw *hw) |
| 1733 | { |
| 1734 | struct cdns_torrent_received_refclk *received_refclk = to_cdns_torrent_received_refclk(hw); |
| 1735 | |
| 1736 | regmap_field_write(received_refclk->phy_pipe_cmn_ctrl1_0, 1); |
| 1737 | |
| 1738 | return 0; |
| 1739 | } |
| 1740 | |
| 1741 | static void cdns_torrent_received_refclk_disable(struct clk_hw *hw) |
| 1742 | { |
| 1743 | struct cdns_torrent_received_refclk *received_refclk = to_cdns_torrent_received_refclk(hw); |
| 1744 | |
| 1745 | regmap_field_write(received_refclk->phy_pipe_cmn_ctrl1_0, 0); |
| 1746 | } |
| 1747 | |
| 1748 | static int cdns_torrent_received_refclk_is_enabled(struct clk_hw *hw) |
| 1749 | { |
| 1750 | struct cdns_torrent_received_refclk *received_refclk = to_cdns_torrent_received_refclk(hw); |
| 1751 | int val, cmn_val; |
| 1752 | |
| 1753 | regmap_field_read(received_refclk->phy_pipe_cmn_ctrl1_0, &val); |
| 1754 | regmap_field_read(received_refclk->cmn_cdiag_refclk_ovrd_4, &cmn_val); |
| 1755 | |
| 1756 | return val && !cmn_val; |
| 1757 | } |
| 1758 | |
| 1759 | static const struct clk_ops cdns_torrent_received_refclk_ops = { |
| 1760 | .enable = cdns_torrent_received_refclk_enable, |
| 1761 | .disable = cdns_torrent_received_refclk_disable, |
| 1762 | .is_enabled = cdns_torrent_received_refclk_is_enabled, |
| 1763 | }; |
| 1764 | |
| 1765 | static int cdns_torrent_received_refclk_register(struct cdns_torrent_phy *cdns_phy) |
| 1766 | { |
| 1767 | struct cdns_torrent_received_refclk *received_refclk; |
| 1768 | struct device *dev = cdns_phy->dev; |
| 1769 | struct clk_init_data *init; |
| 1770 | const char *parent_name; |
| 1771 | char clk_name[100]; |
| 1772 | struct clk_hw *hw; |
| 1773 | struct clk *clk; |
| 1774 | int ret; |
| 1775 | |
| 1776 | received_refclk = devm_kzalloc(dev, sizeof(*received_refclk), GFP_KERNEL); |
| 1777 | if (!received_refclk) |
| 1778 | return -ENOMEM; |
| 1779 | |
| 1780 | snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), |
| 1781 | clk_names[CDNS_TORRENT_RECEIVED_REFCLK]); |
| 1782 | |
| 1783 | clk = devm_clk_get_optional(dev, "phy_en_refclk"); |
| 1784 | if (IS_ERR(clk)) { |
| 1785 | dev_err(dev, "No parent clock for received_refclk\n"); |
| 1786 | return PTR_ERR(clk); |
| 1787 | } |
| 1788 | |
| 1789 | init = &received_refclk->clk_data; |
| 1790 | |
| 1791 | if (clk) { |
| 1792 | parent_name = __clk_get_name(clk); |
| 1793 | init->parent_names = &parent_name; |
| 1794 | init->num_parents = 1; |
| 1795 | } |
| 1796 | init->ops = &cdns_torrent_received_refclk_ops; |
| 1797 | init->flags = 0; |
| 1798 | init->name = clk_name; |
| 1799 | |
| 1800 | received_refclk->phy_pipe_cmn_ctrl1_0 = cdns_phy->phy_pipe_cmn_ctrl1_0; |
| 1801 | received_refclk->cmn_cdiag_refclk_ovrd_4 = cdns_phy->cmn_cdiag_refclk_ovrd_4; |
| 1802 | |
| 1803 | received_refclk->hw.init = init; |
| 1804 | |
| 1805 | hw = &received_refclk->hw; |
| 1806 | ret = devm_clk_hw_register(dev, hw); |
| 1807 | if (ret) |
| 1808 | return ret; |
| 1809 | |
| 1810 | cdns_phy->clk_hw_data->hws[CDNS_TORRENT_RECEIVED_REFCLK] = hw; |
| 1811 | |
| 1812 | return 0; |
| 1813 | } |
| 1814 | |
Swapnil Jakhade | 235bde4 | 2021-09-22 14:37:34 +0200 | [diff] [blame] | 1815 | static int cdns_torrent_refclk_driver_enable(struct clk_hw *hw) |
| 1816 | { |
| 1817 | struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw); |
| 1818 | |
| 1819 | regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_6], 0); |
Swapnil Jakhade | 235bde4 | 2021-09-22 14:37:34 +0200 | [diff] [blame] | 1820 | regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_5], 1); |
| 1821 | regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], 0); |
| 1822 | |
| 1823 | return 0; |
| 1824 | } |
| 1825 | |
| 1826 | static void cdns_torrent_refclk_driver_disable(struct clk_hw *hw) |
| 1827 | { |
| 1828 | struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw); |
| 1829 | |
| 1830 | regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], 1); |
| 1831 | } |
| 1832 | |
| 1833 | static int cdns_torrent_refclk_driver_is_enabled(struct clk_hw *hw) |
| 1834 | { |
| 1835 | struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw); |
| 1836 | int val; |
| 1837 | |
| 1838 | regmap_field_read(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], &val); |
| 1839 | |
| 1840 | return !val; |
| 1841 | } |
| 1842 | |
Swapnil Jakhade | 785a4e6 | 2021-09-22 14:37:35 +0200 | [diff] [blame] | 1843 | static u8 cdns_torrent_refclk_driver_get_parent(struct clk_hw *hw) |
| 1844 | { |
| 1845 | struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw); |
| 1846 | unsigned int val; |
| 1847 | |
| 1848 | regmap_field_read(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], &val); |
| 1849 | return clk_mux_val_to_index(hw, cdns_torrent_refclk_driver_mux_table, 0, val); |
| 1850 | } |
| 1851 | |
| 1852 | static int cdns_torrent_refclk_driver_set_parent(struct clk_hw *hw, u8 index) |
| 1853 | { |
| 1854 | struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw); |
| 1855 | unsigned int val; |
| 1856 | |
| 1857 | val = cdns_torrent_refclk_driver_mux_table[index]; |
| 1858 | return regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], val); |
| 1859 | } |
| 1860 | |
Swapnil Jakhade | 235bde4 | 2021-09-22 14:37:34 +0200 | [diff] [blame] | 1861 | static const struct clk_ops cdns_torrent_refclk_driver_ops = { |
| 1862 | .enable = cdns_torrent_refclk_driver_enable, |
| 1863 | .disable = cdns_torrent_refclk_driver_disable, |
| 1864 | .is_enabled = cdns_torrent_refclk_driver_is_enabled, |
Swapnil Jakhade | 785a4e6 | 2021-09-22 14:37:35 +0200 | [diff] [blame] | 1865 | .set_parent = cdns_torrent_refclk_driver_set_parent, |
| 1866 | .get_parent = cdns_torrent_refclk_driver_get_parent, |
Swapnil Jakhade | 235bde4 | 2021-09-22 14:37:34 +0200 | [diff] [blame] | 1867 | }; |
| 1868 | |
| 1869 | static int cdns_torrent_refclk_driver_register(struct cdns_torrent_phy *cdns_phy) |
| 1870 | { |
| 1871 | struct cdns_torrent_refclk_driver *refclk_driver; |
| 1872 | struct device *dev = cdns_phy->dev; |
| 1873 | struct regmap_field *field; |
| 1874 | struct clk_init_data *init; |
Swapnil Jakhade | 785a4e6 | 2021-09-22 14:37:35 +0200 | [diff] [blame] | 1875 | const char **parent_names; |
| 1876 | unsigned int num_parents; |
Swapnil Jakhade | 235bde4 | 2021-09-22 14:37:34 +0200 | [diff] [blame] | 1877 | struct regmap *regmap; |
| 1878 | char clk_name[100]; |
| 1879 | struct clk_hw *hw; |
| 1880 | int i, ret; |
| 1881 | |
| 1882 | refclk_driver = devm_kzalloc(dev, sizeof(*refclk_driver), GFP_KERNEL); |
| 1883 | if (!refclk_driver) |
| 1884 | return -ENOMEM; |
| 1885 | |
Swapnil Jakhade | 785a4e6 | 2021-09-22 14:37:35 +0200 | [diff] [blame] | 1886 | num_parents = ARRAY_SIZE(refclk_driver_parent_index); |
| 1887 | parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), GFP_KERNEL); |
| 1888 | if (!parent_names) |
| 1889 | return -ENOMEM; |
| 1890 | |
| 1891 | for (i = 0; i < num_parents; i++) { |
| 1892 | hw = cdns_phy->clk_hw_data->hws[refclk_driver_parent_index[i]]; |
| 1893 | if (IS_ERR_OR_NULL(hw)) { |
| 1894 | dev_err(dev, "No parent clock for refclk driver clock\n"); |
| 1895 | return IS_ERR(hw) ? PTR_ERR(hw) : -ENOENT; |
| 1896 | } |
| 1897 | parent_names[i] = clk_hw_get_name(hw); |
Swapnil Jakhade | 235bde4 | 2021-09-22 14:37:34 +0200 | [diff] [blame] | 1898 | } |
Swapnil Jakhade | 235bde4 | 2021-09-22 14:37:34 +0200 | [diff] [blame] | 1899 | |
| 1900 | snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), |
| 1901 | clk_names[CDNS_TORRENT_REFCLK_DRIVER]); |
| 1902 | |
| 1903 | init = &refclk_driver->clk_data; |
| 1904 | |
| 1905 | init->ops = &cdns_torrent_refclk_driver_ops; |
Swapnil Jakhade | 785a4e6 | 2021-09-22 14:37:35 +0200 | [diff] [blame] | 1906 | init->flags = CLK_SET_RATE_NO_REPARENT; |
| 1907 | init->parent_names = parent_names; |
| 1908 | init->num_parents = num_parents; |
Swapnil Jakhade | 235bde4 | 2021-09-22 14:37:34 +0200 | [diff] [blame] | 1909 | init->name = clk_name; |
| 1910 | |
| 1911 | regmap = cdns_phy->regmap_common_cdb; |
| 1912 | |
| 1913 | for (i = 0; i < REFCLK_OUT_NUM_CMN_CONFIG; i++) { |
| 1914 | field = devm_regmap_field_alloc(dev, regmap, refclk_out_cmn_cfg[i]); |
| 1915 | if (IS_ERR(field)) { |
| 1916 | dev_err(dev, "Refclk driver CMN reg field init failed\n"); |
| 1917 | return PTR_ERR(field); |
| 1918 | } |
| 1919 | refclk_driver->cmn_fields[i] = field; |
| 1920 | } |
| 1921 | |
Swapnil Jakhade | 785a4e6 | 2021-09-22 14:37:35 +0200 | [diff] [blame] | 1922 | /* Enable Derived reference clock as default */ |
| 1923 | regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], 1); |
| 1924 | |
Swapnil Jakhade | 235bde4 | 2021-09-22 14:37:34 +0200 | [diff] [blame] | 1925 | refclk_driver->hw.init = init; |
| 1926 | |
| 1927 | hw = &refclk_driver->hw; |
| 1928 | ret = devm_clk_hw_register(dev, hw); |
| 1929 | if (ret) |
| 1930 | return ret; |
| 1931 | |
Swapnil Jakhade | aef096d | 2021-09-22 14:37:32 +0200 | [diff] [blame] | 1932 | cdns_phy->clk_hw_data->hws[CDNS_TORRENT_REFCLK_DRIVER] = hw; |
Kishon Vijay Abraham I | 2cca022 | 2021-03-10 17:38:40 +0530 | [diff] [blame] | 1933 | |
| 1934 | return 0; |
| 1935 | } |
| 1936 | |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 1937 | static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base, |
| 1938 | u32 block_offset, |
| 1939 | u8 reg_offset_shift, |
| 1940 | const struct regmap_config *config) |
| 1941 | { |
| 1942 | struct cdns_regmap_cdb_context *ctx; |
| 1943 | |
| 1944 | ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); |
| 1945 | if (!ctx) |
| 1946 | return ERR_PTR(-ENOMEM); |
| 1947 | |
| 1948 | ctx->dev = dev; |
| 1949 | ctx->base = base + block_offset; |
| 1950 | ctx->reg_offset_shift = reg_offset_shift; |
| 1951 | |
| 1952 | return devm_regmap_init(dev, NULL, ctx, config); |
| 1953 | } |
| 1954 | |
Swapnil Jakhade | 2e70c84 | 2020-09-16 20:28:28 +0200 | [diff] [blame] | 1955 | static int cdns_torrent_dp_regfield_init(struct cdns_torrent_phy *cdns_phy) |
| 1956 | { |
| 1957 | struct device *dev = cdns_phy->dev; |
| 1958 | struct regmap_field *field; |
| 1959 | struct regmap *regmap; |
| 1960 | |
| 1961 | regmap = cdns_phy->regmap_dptx_phy_reg; |
| 1962 | field = devm_regmap_field_alloc(dev, regmap, phy_reset_ctrl); |
| 1963 | if (IS_ERR(field)) { |
| 1964 | dev_err(dev, "PHY_RESET reg field init failed\n"); |
| 1965 | return PTR_ERR(field); |
| 1966 | } |
| 1967 | cdns_phy->phy_reset_ctrl = field; |
| 1968 | |
| 1969 | return 0; |
| 1970 | } |
| 1971 | |
| 1972 | static int cdns_torrent_regfield_init(struct cdns_torrent_phy *cdns_phy) |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 1973 | { |
| 1974 | struct device *dev = cdns_phy->dev; |
| 1975 | struct regmap_field *field; |
| 1976 | struct regmap *regmap; |
Swapnil Jakhade | 48ac608 | 2021-07-28 16:54:54 +0200 | [diff] [blame] | 1977 | int i; |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 1978 | |
| 1979 | regmap = cdns_phy->regmap_phy_pcs_common_cdb; |
| 1980 | field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg); |
| 1981 | if (IS_ERR(field)) { |
| 1982 | dev_err(dev, "PHY_PLL_CFG reg field init failed\n"); |
| 1983 | return PTR_ERR(field); |
| 1984 | } |
| 1985 | cdns_phy->phy_pll_cfg = field; |
| 1986 | |
Swapnil Jakhade | 235bde4 | 2021-09-22 14:37:34 +0200 | [diff] [blame] | 1987 | regmap = cdns_phy->regmap_phy_pcs_common_cdb; |
| 1988 | field = devm_regmap_field_alloc(dev, regmap, phy_pipe_cmn_ctrl1_0); |
| 1989 | if (IS_ERR(field)) { |
| 1990 | dev_err(dev, "phy_pipe_cmn_ctrl1_0 reg field init failed\n"); |
| 1991 | return PTR_ERR(field); |
| 1992 | } |
| 1993 | cdns_phy->phy_pipe_cmn_ctrl1_0 = field; |
| 1994 | |
| 1995 | regmap = cdns_phy->regmap_common_cdb; |
| 1996 | field = devm_regmap_field_alloc(dev, regmap, cmn_cdiag_refclk_ovrd_4); |
| 1997 | if (IS_ERR(field)) { |
| 1998 | dev_err(dev, "cmn_cdiag_refclk_ovrd_4 reg field init failed\n"); |
| 1999 | return PTR_ERR(field); |
| 2000 | } |
| 2001 | cdns_phy->cmn_cdiag_refclk_ovrd_4 = field; |
| 2002 | |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 2003 | regmap = cdns_phy->regmap_phy_pma_common_cdb; |
Swapnil Jakhade | 8e4c95b | 2020-09-17 09:30:35 +0200 | [diff] [blame] | 2004 | field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_1); |
| 2005 | if (IS_ERR(field)) { |
| 2006 | dev_err(dev, "PHY_PMA_CMN_CTRL1 reg field init failed\n"); |
| 2007 | return PTR_ERR(field); |
| 2008 | } |
| 2009 | cdns_phy->phy_pma_cmn_ctrl_1 = field; |
| 2010 | |
| 2011 | regmap = cdns_phy->regmap_phy_pma_common_cdb; |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 2012 | field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_2); |
| 2013 | if (IS_ERR(field)) { |
| 2014 | dev_err(dev, "PHY_PMA_CMN_CTRL2 reg field init failed\n"); |
| 2015 | return PTR_ERR(field); |
| 2016 | } |
| 2017 | cdns_phy->phy_pma_cmn_ctrl_2 = field; |
| 2018 | |
| 2019 | regmap = cdns_phy->regmap_phy_pma_common_cdb; |
| 2020 | field = devm_regmap_field_alloc(dev, regmap, phy_pma_pll_raw_ctrl); |
| 2021 | if (IS_ERR(field)) { |
| 2022 | dev_err(dev, "PHY_PMA_PLL_RAW_CTRL reg field init failed\n"); |
| 2023 | return PTR_ERR(field); |
| 2024 | } |
| 2025 | cdns_phy->phy_pma_pll_raw_ctrl = field; |
| 2026 | |
Swapnil Jakhade | 48ac608 | 2021-07-28 16:54:54 +0200 | [diff] [blame] | 2027 | for (i = 0; i < MAX_NUM_LANES; i++) { |
| 2028 | regmap = cdns_phy->regmap_phy_pcs_lane_cdb[i]; |
| 2029 | field = devm_regmap_field_alloc(dev, regmap, phy_pcs_iso_link_ctrl_1); |
| 2030 | if (IS_ERR(field)) { |
| 2031 | dev_err(dev, "PHY_PCS_ISO_LINK_CTRL reg field init for ln %d failed\n", i); |
| 2032 | return PTR_ERR(field); |
| 2033 | } |
| 2034 | cdns_phy->phy_pcs_iso_link_ctrl_1[i] = field; |
| 2035 | } |
| 2036 | |
Swapnil Jakhade | 2e70c84 | 2020-09-16 20:28:28 +0200 | [diff] [blame] | 2037 | return 0; |
| 2038 | } |
| 2039 | |
| 2040 | static int cdns_torrent_dp_regmap_init(struct cdns_torrent_phy *cdns_phy) |
| 2041 | { |
| 2042 | void __iomem *base = cdns_phy->base; |
| 2043 | struct device *dev = cdns_phy->dev; |
| 2044 | struct regmap *regmap; |
| 2045 | u8 reg_offset_shift; |
| 2046 | u32 block_offset; |
| 2047 | |
| 2048 | reg_offset_shift = cdns_phy->init_data->reg_offset_shift; |
| 2049 | |
| 2050 | block_offset = TORRENT_DPTX_PHY_OFFSET; |
| 2051 | regmap = cdns_regmap_init(dev, base, block_offset, |
| 2052 | reg_offset_shift, |
| 2053 | &cdns_torrent_dptx_phy_config); |
| 2054 | if (IS_ERR(regmap)) { |
| 2055 | dev_err(dev, "Failed to init DPTX PHY regmap\n"); |
| 2056 | return PTR_ERR(regmap); |
Swapnil Jakhade | cba472e | 2020-02-06 07:10:59 +0100 | [diff] [blame] | 2057 | } |
Swapnil Jakhade | 2e70c84 | 2020-09-16 20:28:28 +0200 | [diff] [blame] | 2058 | cdns_phy->regmap_dptx_phy_reg = regmap; |
Swapnil Jakhade | cba472e | 2020-02-06 07:10:59 +0100 | [diff] [blame] | 2059 | |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 2060 | return 0; |
| 2061 | } |
| 2062 | |
Swapnil Jakhade | 2e70c84 | 2020-09-16 20:28:28 +0200 | [diff] [blame] | 2063 | static int cdns_torrent_regmap_init(struct cdns_torrent_phy *cdns_phy) |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 2064 | { |
Swapnil Jakhade | 2e70c84 | 2020-09-16 20:28:28 +0200 | [diff] [blame] | 2065 | void __iomem *sd_base = cdns_phy->sd_base; |
| 2066 | u8 block_offset_shift, reg_offset_shift; |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 2067 | struct device *dev = cdns_phy->dev; |
| 2068 | struct regmap *regmap; |
| 2069 | u32 block_offset; |
| 2070 | int i; |
| 2071 | |
Swapnil Jakhade | 2e70c84 | 2020-09-16 20:28:28 +0200 | [diff] [blame] | 2072 | block_offset_shift = cdns_phy->init_data->block_offset_shift; |
| 2073 | reg_offset_shift = cdns_phy->init_data->reg_offset_shift; |
| 2074 | |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 2075 | for (i = 0; i < MAX_NUM_LANES; i++) { |
| 2076 | block_offset = TORRENT_TX_LANE_CDB_OFFSET(i, block_offset_shift, |
| 2077 | reg_offset_shift); |
| 2078 | regmap = cdns_regmap_init(dev, sd_base, block_offset, |
| 2079 | reg_offset_shift, |
| 2080 | &cdns_torrent_tx_lane_cdb_config[i]); |
| 2081 | if (IS_ERR(regmap)) { |
| 2082 | dev_err(dev, "Failed to init tx lane CDB regmap\n"); |
| 2083 | return PTR_ERR(regmap); |
| 2084 | } |
| 2085 | cdns_phy->regmap_tx_lane_cdb[i] = regmap; |
| 2086 | |
| 2087 | block_offset = TORRENT_RX_LANE_CDB_OFFSET(i, block_offset_shift, |
| 2088 | reg_offset_shift); |
| 2089 | regmap = cdns_regmap_init(dev, sd_base, block_offset, |
| 2090 | reg_offset_shift, |
| 2091 | &cdns_torrent_rx_lane_cdb_config[i]); |
| 2092 | if (IS_ERR(regmap)) { |
| 2093 | dev_err(dev, "Failed to init rx lane CDB regmap\n"); |
| 2094 | return PTR_ERR(regmap); |
| 2095 | } |
| 2096 | cdns_phy->regmap_rx_lane_cdb[i] = regmap; |
Swapnil Jakhade | 48ac608 | 2021-07-28 16:54:54 +0200 | [diff] [blame] | 2097 | |
| 2098 | block_offset = TORRENT_PHY_PCS_LANE_CDB_OFFSET(i, block_offset_shift, |
| 2099 | reg_offset_shift); |
| 2100 | regmap = cdns_regmap_init(dev, sd_base, block_offset, |
| 2101 | reg_offset_shift, |
| 2102 | &cdns_torrent_phy_pcs_lane_cdb_config[i]); |
| 2103 | if (IS_ERR(regmap)) { |
| 2104 | dev_err(dev, "Failed to init PHY PCS lane CDB regmap\n"); |
| 2105 | return PTR_ERR(regmap); |
| 2106 | } |
| 2107 | cdns_phy->regmap_phy_pcs_lane_cdb[i] = regmap; |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 2108 | } |
| 2109 | |
| 2110 | block_offset = TORRENT_COMMON_CDB_OFFSET; |
| 2111 | regmap = cdns_regmap_init(dev, sd_base, block_offset, |
| 2112 | reg_offset_shift, |
| 2113 | &cdns_torrent_common_cdb_config); |
| 2114 | if (IS_ERR(regmap)) { |
| 2115 | dev_err(dev, "Failed to init common CDB regmap\n"); |
| 2116 | return PTR_ERR(regmap); |
| 2117 | } |
| 2118 | cdns_phy->regmap_common_cdb = regmap; |
| 2119 | |
| 2120 | block_offset = TORRENT_PHY_PCS_COMMON_OFFSET(block_offset_shift); |
| 2121 | regmap = cdns_regmap_init(dev, sd_base, block_offset, |
| 2122 | reg_offset_shift, |
| 2123 | &cdns_torrent_phy_pcs_cmn_cdb_config); |
| 2124 | if (IS_ERR(regmap)) { |
| 2125 | dev_err(dev, "Failed to init PHY PCS common CDB regmap\n"); |
| 2126 | return PTR_ERR(regmap); |
| 2127 | } |
| 2128 | cdns_phy->regmap_phy_pcs_common_cdb = regmap; |
| 2129 | |
| 2130 | block_offset = TORRENT_PHY_PMA_COMMON_OFFSET(block_offset_shift); |
| 2131 | regmap = cdns_regmap_init(dev, sd_base, block_offset, |
| 2132 | reg_offset_shift, |
| 2133 | &cdns_torrent_phy_pma_cmn_cdb_config); |
| 2134 | if (IS_ERR(regmap)) { |
| 2135 | dev_err(dev, "Failed to init PHY PMA common CDB regmap\n"); |
| 2136 | return PTR_ERR(regmap); |
| 2137 | } |
| 2138 | cdns_phy->regmap_phy_pma_common_cdb = regmap; |
| 2139 | |
| 2140 | return 0; |
| 2141 | } |
| 2142 | |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 2143 | static int cdns_torrent_phy_init(struct phy *phy) |
| 2144 | { |
| 2145 | struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 2146 | const struct cdns_torrent_data *init_data = cdns_phy->init_data; |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 2147 | struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals; |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 2148 | enum cdns_torrent_ref_clk ref_clk = cdns_phy->ref_clk_rate; |
Swapnil Jakhade | cd9aa94 | 2020-09-17 09:30:41 +0200 | [diff] [blame] | 2149 | struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals; |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 2150 | struct cdns_torrent_inst *inst = phy_get_drvdata(phy); |
| 2151 | enum cdns_torrent_phy_type phy_type = inst->phy_type; |
| 2152 | enum cdns_torrent_ssc_mode ssc = inst->ssc_mode; |
Swapnil Jakhade | 9855d84 | 2020-09-17 09:30:44 +0200 | [diff] [blame] | 2153 | struct cdns_torrent_vals *pcs_cmn_vals; |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 2154 | struct cdns_reg_pairs *reg_pairs; |
| 2155 | struct regmap *regmap; |
| 2156 | u32 num_regs; |
Swapnil Jakhade | 07084c9 | 2020-09-17 09:30:40 +0200 | [diff] [blame] | 2157 | int i, j; |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 2158 | |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 2159 | if (cdns_phy->nsubnodes > 1) |
| 2160 | return 0; |
| 2161 | |
Swapnil Jakhade | 9f33b76 | 2020-09-17 09:30:43 +0200 | [diff] [blame] | 2162 | /** |
| 2163 | * Spread spectrum generation is not required or supported |
| 2164 | * for SGMII/QSGMII |
| 2165 | */ |
| 2166 | if (phy_type == TYPE_SGMII || phy_type == TYPE_QSGMII) |
| 2167 | ssc = NO_SSC; |
| 2168 | |
Swapnil Jakhade | cd9aa94 | 2020-09-17 09:30:41 +0200 | [diff] [blame] | 2169 | /* PHY configuration specific registers for single link */ |
| 2170 | link_cmn_vals = init_data->link_cmn_vals[phy_type][TYPE_NONE][ssc]; |
| 2171 | if (link_cmn_vals) { |
| 2172 | reg_pairs = link_cmn_vals->reg_pairs; |
| 2173 | num_regs = link_cmn_vals->num_regs; |
| 2174 | regmap = cdns_phy->regmap_common_cdb; |
Swapnil Jakhade | d66a636 | 2020-09-17 09:30:42 +0200 | [diff] [blame] | 2175 | |
| 2176 | /** |
| 2177 | * First array value in link_cmn_vals must be of |
| 2178 | * PHY_PLL_CFG register |
| 2179 | */ |
| 2180 | regmap_field_write(cdns_phy->phy_pll_cfg, reg_pairs[0].val); |
| 2181 | |
| 2182 | for (i = 1; i < num_regs; i++) |
Swapnil Jakhade | cd9aa94 | 2020-09-17 09:30:41 +0200 | [diff] [blame] | 2183 | regmap_write(regmap, reg_pairs[i].off, |
| 2184 | reg_pairs[i].val); |
| 2185 | } |
| 2186 | |
| 2187 | xcvr_diag_vals = init_data->xcvr_diag_vals[phy_type][TYPE_NONE][ssc]; |
| 2188 | if (xcvr_diag_vals) { |
| 2189 | reg_pairs = xcvr_diag_vals->reg_pairs; |
| 2190 | num_regs = xcvr_diag_vals->num_regs; |
| 2191 | for (i = 0; i < inst->num_lanes; i++) { |
| 2192 | regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane]; |
| 2193 | for (j = 0; j < num_regs; j++) |
| 2194 | regmap_write(regmap, reg_pairs[j].off, |
| 2195 | reg_pairs[j].val); |
| 2196 | } |
| 2197 | } |
| 2198 | |
Swapnil Jakhade | 9855d84 | 2020-09-17 09:30:44 +0200 | [diff] [blame] | 2199 | /* PHY PCS common registers configurations */ |
| 2200 | pcs_cmn_vals = init_data->pcs_cmn_vals[phy_type][TYPE_NONE][ssc]; |
| 2201 | if (pcs_cmn_vals) { |
| 2202 | reg_pairs = pcs_cmn_vals->reg_pairs; |
| 2203 | num_regs = pcs_cmn_vals->num_regs; |
| 2204 | regmap = cdns_phy->regmap_phy_pcs_common_cdb; |
| 2205 | for (i = 0; i < num_regs; i++) |
| 2206 | regmap_write(regmap, reg_pairs[i].off, |
| 2207 | reg_pairs[i].val); |
| 2208 | } |
| 2209 | |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 2210 | /* PMA common registers configurations */ |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 2211 | cmn_vals = init_data->cmn_vals[ref_clk][phy_type][TYPE_NONE][ssc]; |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 2212 | if (cmn_vals) { |
| 2213 | reg_pairs = cmn_vals->reg_pairs; |
| 2214 | num_regs = cmn_vals->num_regs; |
| 2215 | regmap = cdns_phy->regmap_common_cdb; |
| 2216 | for (i = 0; i < num_regs; i++) |
| 2217 | regmap_write(regmap, reg_pairs[i].off, |
| 2218 | reg_pairs[i].val); |
| 2219 | } |
| 2220 | |
| 2221 | /* PMA TX lane registers configurations */ |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 2222 | tx_ln_vals = init_data->tx_ln_vals[ref_clk][phy_type][TYPE_NONE][ssc]; |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 2223 | if (tx_ln_vals) { |
| 2224 | reg_pairs = tx_ln_vals->reg_pairs; |
| 2225 | num_regs = tx_ln_vals->num_regs; |
| 2226 | for (i = 0; i < inst->num_lanes; i++) { |
| 2227 | regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane]; |
| 2228 | for (j = 0; j < num_regs; j++) |
| 2229 | regmap_write(regmap, reg_pairs[j].off, |
| 2230 | reg_pairs[j].val); |
| 2231 | } |
| 2232 | } |
| 2233 | |
| 2234 | /* PMA RX lane registers configurations */ |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 2235 | rx_ln_vals = init_data->rx_ln_vals[ref_clk][phy_type][TYPE_NONE][ssc]; |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 2236 | if (rx_ln_vals) { |
| 2237 | reg_pairs = rx_ln_vals->reg_pairs; |
| 2238 | num_regs = rx_ln_vals->num_regs; |
| 2239 | for (i = 0; i < inst->num_lanes; i++) { |
| 2240 | regmap = cdns_phy->regmap_rx_lane_cdb[i + inst->mlane]; |
| 2241 | for (j = 0; j < num_regs; j++) |
| 2242 | regmap_write(regmap, reg_pairs[j].off, |
| 2243 | reg_pairs[j].val); |
| 2244 | } |
| 2245 | } |
| 2246 | |
Swapnil Jakhade | da055e5 | 2021-07-28 16:54:50 +0200 | [diff] [blame] | 2247 | if (phy_type == TYPE_DP) |
| 2248 | return cdns_torrent_dp_init(phy); |
| 2249 | |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 2250 | return 0; |
| 2251 | } |
| 2252 | |
Swapnil Jakhade | 5b16a79 | 2021-07-28 16:54:47 +0200 | [diff] [blame] | 2253 | static const struct phy_ops cdns_torrent_phy_ops = { |
| 2254 | .init = cdns_torrent_phy_init, |
| 2255 | .configure = cdns_torrent_dp_configure, |
| 2256 | .power_on = cdns_torrent_phy_on, |
| 2257 | .power_off = cdns_torrent_phy_off, |
| 2258 | .owner = THIS_MODULE, |
| 2259 | }; |
| 2260 | |
| 2261 | static int cdns_torrent_noop_phy_on(struct phy *phy) |
| 2262 | { |
| 2263 | /* Give 5ms to 10ms delay for the PIPE clock to be stable */ |
| 2264 | usleep_range(5000, 10000); |
| 2265 | |
| 2266 | return 0; |
| 2267 | } |
| 2268 | |
| 2269 | static const struct phy_ops noop_ops = { |
| 2270 | .power_on = cdns_torrent_noop_phy_on, |
| 2271 | .owner = THIS_MODULE, |
| 2272 | }; |
| 2273 | |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 2274 | static |
| 2275 | int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy) |
| 2276 | { |
| 2277 | const struct cdns_torrent_data *init_data = cdns_phy->init_data; |
| 2278 | struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals; |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 2279 | enum cdns_torrent_ref_clk ref_clk = cdns_phy->ref_clk_rate; |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 2280 | struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals; |
Yang Guang | a463462 | 2021-11-04 14:52:33 +0800 | [diff] [blame] | 2281 | enum cdns_torrent_phy_type phy_t1, phy_t2; |
Swapnil Jakhade | 4acea47 | 2020-09-17 09:30:45 +0200 | [diff] [blame] | 2282 | struct cdns_torrent_vals *pcs_cmn_vals; |
Swapnil Jakhade | f0f1fa0 | 2020-09-17 09:30:39 +0200 | [diff] [blame] | 2283 | int i, j, node, mlane, num_lanes, ret; |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 2284 | struct cdns_reg_pairs *reg_pairs; |
| 2285 | enum cdns_torrent_ssc_mode ssc; |
| 2286 | struct regmap *regmap; |
| 2287 | u32 num_regs; |
| 2288 | |
| 2289 | /* Maximum 2 links (subnodes) are supported */ |
| 2290 | if (cdns_phy->nsubnodes != 2) |
| 2291 | return -EINVAL; |
| 2292 | |
| 2293 | phy_t1 = cdns_phy->phys[0].phy_type; |
| 2294 | phy_t2 = cdns_phy->phys[1].phy_type; |
| 2295 | |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 2296 | /** |
| 2297 | * First configure the PHY for first link with phy_t1. Get the array |
| 2298 | * values as [phy_t1][phy_t2][ssc]. |
| 2299 | */ |
| 2300 | for (node = 0; node < cdns_phy->nsubnodes; node++) { |
| 2301 | if (node == 1) { |
| 2302 | /** |
| 2303 | * If first link with phy_t1 is configured, then |
| 2304 | * configure the PHY for second link with phy_t2. |
| 2305 | * Get the array values as [phy_t2][phy_t1][ssc]. |
| 2306 | */ |
Yang Guang | a463462 | 2021-11-04 14:52:33 +0800 | [diff] [blame] | 2307 | swap(phy_t1, phy_t2); |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 2308 | } |
| 2309 | |
| 2310 | mlane = cdns_phy->phys[node].mlane; |
| 2311 | ssc = cdns_phy->phys[node].ssc_mode; |
| 2312 | num_lanes = cdns_phy->phys[node].num_lanes; |
| 2313 | |
| 2314 | /** |
| 2315 | * PHY configuration specific registers: |
| 2316 | * link_cmn_vals depend on combination of PHY types being |
| 2317 | * configured and are common for both PHY types, so array |
| 2318 | * values should be same for [phy_t1][phy_t2][ssc] and |
| 2319 | * [phy_t2][phy_t1][ssc]. |
| 2320 | * xcvr_diag_vals also depend on combination of PHY types |
| 2321 | * being configured, but these can be different for particular |
| 2322 | * PHY type and are per lane. |
| 2323 | */ |
| 2324 | link_cmn_vals = init_data->link_cmn_vals[phy_t1][phy_t2][ssc]; |
| 2325 | if (link_cmn_vals) { |
| 2326 | reg_pairs = link_cmn_vals->reg_pairs; |
| 2327 | num_regs = link_cmn_vals->num_regs; |
| 2328 | regmap = cdns_phy->regmap_common_cdb; |
Swapnil Jakhade | d66a636 | 2020-09-17 09:30:42 +0200 | [diff] [blame] | 2329 | |
| 2330 | /** |
| 2331 | * First array value in link_cmn_vals must be of |
| 2332 | * PHY_PLL_CFG register |
| 2333 | */ |
| 2334 | regmap_field_write(cdns_phy->phy_pll_cfg, |
| 2335 | reg_pairs[0].val); |
| 2336 | |
| 2337 | for (i = 1; i < num_regs; i++) |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 2338 | regmap_write(regmap, reg_pairs[i].off, |
| 2339 | reg_pairs[i].val); |
| 2340 | } |
| 2341 | |
| 2342 | xcvr_diag_vals = init_data->xcvr_diag_vals[phy_t1][phy_t2][ssc]; |
| 2343 | if (xcvr_diag_vals) { |
| 2344 | reg_pairs = xcvr_diag_vals->reg_pairs; |
| 2345 | num_regs = xcvr_diag_vals->num_regs; |
| 2346 | for (i = 0; i < num_lanes; i++) { |
| 2347 | regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane]; |
| 2348 | for (j = 0; j < num_regs; j++) |
| 2349 | regmap_write(regmap, reg_pairs[j].off, |
| 2350 | reg_pairs[j].val); |
| 2351 | } |
| 2352 | } |
| 2353 | |
Swapnil Jakhade | 4acea47 | 2020-09-17 09:30:45 +0200 | [diff] [blame] | 2354 | /* PHY PCS common registers configurations */ |
| 2355 | pcs_cmn_vals = init_data->pcs_cmn_vals[phy_t1][phy_t2][ssc]; |
| 2356 | if (pcs_cmn_vals) { |
| 2357 | reg_pairs = pcs_cmn_vals->reg_pairs; |
| 2358 | num_regs = pcs_cmn_vals->num_regs; |
| 2359 | regmap = cdns_phy->regmap_phy_pcs_common_cdb; |
| 2360 | for (i = 0; i < num_regs; i++) |
| 2361 | regmap_write(regmap, reg_pairs[i].off, |
| 2362 | reg_pairs[i].val); |
| 2363 | } |
| 2364 | |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 2365 | /* PMA common registers configurations */ |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 2366 | cmn_vals = init_data->cmn_vals[ref_clk][phy_t1][phy_t2][ssc]; |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 2367 | if (cmn_vals) { |
| 2368 | reg_pairs = cmn_vals->reg_pairs; |
| 2369 | num_regs = cmn_vals->num_regs; |
| 2370 | regmap = cdns_phy->regmap_common_cdb; |
| 2371 | for (i = 0; i < num_regs; i++) |
| 2372 | regmap_write(regmap, reg_pairs[i].off, |
| 2373 | reg_pairs[i].val); |
| 2374 | } |
| 2375 | |
| 2376 | /* PMA TX lane registers configurations */ |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 2377 | tx_ln_vals = init_data->tx_ln_vals[ref_clk][phy_t1][phy_t2][ssc]; |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 2378 | if (tx_ln_vals) { |
| 2379 | reg_pairs = tx_ln_vals->reg_pairs; |
| 2380 | num_regs = tx_ln_vals->num_regs; |
| 2381 | for (i = 0; i < num_lanes; i++) { |
| 2382 | regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane]; |
| 2383 | for (j = 0; j < num_regs; j++) |
| 2384 | regmap_write(regmap, reg_pairs[j].off, |
| 2385 | reg_pairs[j].val); |
| 2386 | } |
| 2387 | } |
| 2388 | |
| 2389 | /* PMA RX lane registers configurations */ |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 2390 | rx_ln_vals = init_data->rx_ln_vals[ref_clk][phy_t1][phy_t2][ssc]; |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 2391 | if (rx_ln_vals) { |
| 2392 | reg_pairs = rx_ln_vals->reg_pairs; |
| 2393 | num_regs = rx_ln_vals->num_regs; |
| 2394 | for (i = 0; i < num_lanes; i++) { |
| 2395 | regmap = cdns_phy->regmap_rx_lane_cdb[i + mlane]; |
| 2396 | for (j = 0; j < num_regs; j++) |
| 2397 | regmap_write(regmap, reg_pairs[j].off, |
| 2398 | reg_pairs[j].val); |
| 2399 | } |
| 2400 | } |
Swapnil Jakhade | f0f1fa0 | 2020-09-17 09:30:39 +0200 | [diff] [blame] | 2401 | |
| 2402 | reset_control_deassert(cdns_phy->phys[node].lnk_rst); |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 2403 | } |
| 2404 | |
Swapnil Jakhade | f0f1fa0 | 2020-09-17 09:30:39 +0200 | [diff] [blame] | 2405 | /* Take the PHY out of reset */ |
| 2406 | ret = reset_control_deassert(cdns_phy->phy_rst); |
| 2407 | if (ret) |
| 2408 | return ret; |
| 2409 | |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 2410 | return 0; |
| 2411 | } |
| 2412 | |
Kishon Vijay Abraham I | 2cca022 | 2021-03-10 17:38:40 +0530 | [diff] [blame] | 2413 | static void cdns_torrent_clk_cleanup(struct cdns_torrent_phy *cdns_phy) |
| 2414 | { |
| 2415 | struct device *dev = cdns_phy->dev; |
| 2416 | |
| 2417 | of_clk_del_provider(dev->of_node); |
| 2418 | } |
| 2419 | |
| 2420 | static int cdns_torrent_clk_register(struct cdns_torrent_phy *cdns_phy) |
| 2421 | { |
| 2422 | struct device *dev = cdns_phy->dev; |
| 2423 | struct device_node *node = dev->of_node; |
Swapnil Jakhade | aef096d | 2021-09-22 14:37:32 +0200 | [diff] [blame] | 2424 | struct clk_hw_onecell_data *data; |
Kishon Vijay Abraham I | 2cca022 | 2021-03-10 17:38:40 +0530 | [diff] [blame] | 2425 | int ret; |
| 2426 | |
Swapnil Jakhade | aef096d | 2021-09-22 14:37:32 +0200 | [diff] [blame] | 2427 | data = devm_kzalloc(dev, struct_size(data, hws, CDNS_TORRENT_OUTPUT_CLOCKS), GFP_KERNEL); |
| 2428 | if (!data) |
| 2429 | return -ENOMEM; |
| 2430 | |
| 2431 | data->num = CDNS_TORRENT_OUTPUT_CLOCKS; |
| 2432 | cdns_phy->clk_hw_data = data; |
| 2433 | |
Kishon Vijay Abraham I | 2cca022 | 2021-03-10 17:38:40 +0530 | [diff] [blame] | 2434 | ret = cdns_torrent_derived_refclk_register(cdns_phy); |
| 2435 | if (ret) { |
| 2436 | dev_err(dev, "failed to register derived refclk\n"); |
| 2437 | return ret; |
| 2438 | } |
| 2439 | |
Swapnil Jakhade | 785a4e6 | 2021-09-22 14:37:35 +0200 | [diff] [blame] | 2440 | ret = cdns_torrent_received_refclk_register(cdns_phy); |
| 2441 | if (ret) { |
| 2442 | dev_err(dev, "failed to register received refclk\n"); |
| 2443 | return ret; |
| 2444 | } |
| 2445 | |
Swapnil Jakhade | 235bde4 | 2021-09-22 14:37:34 +0200 | [diff] [blame] | 2446 | ret = cdns_torrent_refclk_driver_register(cdns_phy); |
| 2447 | if (ret) { |
| 2448 | dev_err(dev, "failed to register refclk driver\n"); |
| 2449 | return ret; |
| 2450 | } |
| 2451 | |
Swapnil Jakhade | aef096d | 2021-09-22 14:37:32 +0200 | [diff] [blame] | 2452 | ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, data); |
Kishon Vijay Abraham I | 2cca022 | 2021-03-10 17:38:40 +0530 | [diff] [blame] | 2453 | if (ret) { |
| 2454 | dev_err(dev, "Failed to add clock provider: %s\n", node->name); |
| 2455 | return ret; |
| 2456 | } |
| 2457 | |
| 2458 | return 0; |
| 2459 | } |
| 2460 | |
Kishon Vijay Abraham I | d44b4bf | 2021-03-30 16:31:35 +0530 | [diff] [blame] | 2461 | static int cdns_torrent_reset(struct cdns_torrent_phy *cdns_phy) |
| 2462 | { |
| 2463 | struct device *dev = cdns_phy->dev; |
| 2464 | |
| 2465 | cdns_phy->phy_rst = devm_reset_control_get_exclusive_by_index(dev, 0); |
| 2466 | if (IS_ERR(cdns_phy->phy_rst)) { |
| 2467 | dev_err(dev, "%s: failed to get reset\n", |
| 2468 | dev->of_node->full_name); |
| 2469 | return PTR_ERR(cdns_phy->phy_rst); |
| 2470 | } |
| 2471 | |
Kishon Vijay Abraham I | e0611d6 | 2021-03-30 16:31:37 +0530 | [diff] [blame] | 2472 | cdns_phy->apb_rst = devm_reset_control_get_optional_exclusive(dev, "torrent_apb"); |
Kishon Vijay Abraham I | d44b4bf | 2021-03-30 16:31:35 +0530 | [diff] [blame] | 2473 | if (IS_ERR(cdns_phy->apb_rst)) { |
| 2474 | dev_err(dev, "%s: failed to get apb reset\n", |
| 2475 | dev->of_node->full_name); |
| 2476 | return PTR_ERR(cdns_phy->apb_rst); |
| 2477 | } |
| 2478 | |
| 2479 | return 0; |
| 2480 | } |
| 2481 | |
| 2482 | static int cdns_torrent_clk(struct cdns_torrent_phy *cdns_phy) |
| 2483 | { |
| 2484 | struct device *dev = cdns_phy->dev; |
Swapnil Jakhade | 3b40162 | 2021-07-28 16:54:48 +0200 | [diff] [blame] | 2485 | unsigned long ref_clk_rate; |
Kishon Vijay Abraham I | d44b4bf | 2021-03-30 16:31:35 +0530 | [diff] [blame] | 2486 | int ret; |
| 2487 | |
| 2488 | cdns_phy->clk = devm_clk_get(dev, "refclk"); |
| 2489 | if (IS_ERR(cdns_phy->clk)) { |
| 2490 | dev_err(dev, "phy ref clock not found\n"); |
| 2491 | return PTR_ERR(cdns_phy->clk); |
| 2492 | } |
| 2493 | |
| 2494 | ret = clk_prepare_enable(cdns_phy->clk); |
| 2495 | if (ret) { |
| 2496 | dev_err(cdns_phy->dev, "Failed to prepare ref clock\n"); |
| 2497 | return ret; |
| 2498 | } |
| 2499 | |
Swapnil Jakhade | 3b40162 | 2021-07-28 16:54:48 +0200 | [diff] [blame] | 2500 | ref_clk_rate = clk_get_rate(cdns_phy->clk); |
| 2501 | if (!ref_clk_rate) { |
Kishon Vijay Abraham I | d44b4bf | 2021-03-30 16:31:35 +0530 | [diff] [blame] | 2502 | dev_err(cdns_phy->dev, "Failed to get ref clock rate\n"); |
| 2503 | clk_disable_unprepare(cdns_phy->clk); |
| 2504 | return -EINVAL; |
| 2505 | } |
| 2506 | |
Swapnil Jakhade | 3b40162 | 2021-07-28 16:54:48 +0200 | [diff] [blame] | 2507 | switch (ref_clk_rate) { |
| 2508 | case REF_CLK_19_2MHZ: |
| 2509 | cdns_phy->ref_clk_rate = CLK_19_2_MHZ; |
| 2510 | break; |
| 2511 | case REF_CLK_25MHZ: |
| 2512 | cdns_phy->ref_clk_rate = CLK_25_MHZ; |
| 2513 | break; |
| 2514 | case REF_CLK_100MHZ: |
| 2515 | cdns_phy->ref_clk_rate = CLK_100_MHZ; |
| 2516 | break; |
| 2517 | default: |
| 2518 | dev_err(cdns_phy->dev, "Invalid Ref Clock Rate\n"); |
| 2519 | clk_disable_unprepare(cdns_phy->clk); |
| 2520 | return -EINVAL; |
| 2521 | } |
| 2522 | |
Kishon Vijay Abraham I | d44b4bf | 2021-03-30 16:31:35 +0530 | [diff] [blame] | 2523 | return 0; |
| 2524 | } |
| 2525 | |
Swapnil Jakhade | 92e9ccc | 2020-02-06 07:10:52 +0100 | [diff] [blame] | 2526 | static int cdns_torrent_phy_probe(struct platform_device *pdev) |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 2527 | { |
Swapnil Jakhade | 92e9ccc | 2020-02-06 07:10:52 +0100 | [diff] [blame] | 2528 | struct cdns_torrent_phy *cdns_phy; |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 2529 | struct device *dev = &pdev->dev; |
| 2530 | struct phy_provider *phy_provider; |
Swapnil Jakhade | 29d1fd2 | 2020-09-16 20:28:25 +0200 | [diff] [blame] | 2531 | const struct cdns_torrent_data *data; |
Swapnil Jakhade | afa4ba0 | 2020-02-06 07:11:01 +0100 | [diff] [blame] | 2532 | struct device_node *child; |
| 2533 | int ret, subnodes, node = 0, i; |
Swapnil Jakhade | d09945e | 2020-09-16 20:28:29 +0200 | [diff] [blame] | 2534 | u32 total_num_lanes = 0; |
Kishon Vijay Abraham I | b69d39f | 2021-03-30 16:31:36 +0530 | [diff] [blame] | 2535 | int already_configured; |
Swapnil Jakhade | 2e70c84 | 2020-09-16 20:28:28 +0200 | [diff] [blame] | 2536 | u8 init_dp_regmap = 0; |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 2537 | u32 phy_type; |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 2538 | |
| 2539 | /* Get init data for this PHY */ |
Swapnil Jakhade | 29d1fd2 | 2020-09-16 20:28:25 +0200 | [diff] [blame] | 2540 | data = of_device_get_match_data(dev); |
| 2541 | if (!data) |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 2542 | return -EINVAL; |
| 2543 | |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 2544 | cdns_phy = devm_kzalloc(dev, sizeof(*cdns_phy), GFP_KERNEL); |
| 2545 | if (!cdns_phy) |
| 2546 | return -ENOMEM; |
| 2547 | |
Swapnil Jakhade | afa4ba0 | 2020-02-06 07:11:01 +0100 | [diff] [blame] | 2548 | dev_set_drvdata(dev, cdns_phy); |
| 2549 | cdns_phy->dev = dev; |
Swapnil Jakhade | 29d1fd2 | 2020-09-16 20:28:25 +0200 | [diff] [blame] | 2550 | cdns_phy->init_data = data; |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 2551 | |
Swapnil Jakhade | 46d205a | 2020-09-16 20:28:26 +0200 | [diff] [blame] | 2552 | cdns_phy->sd_base = devm_platform_ioremap_resource(pdev, 0); |
Swapnil Jakhade | afa4ba0 | 2020-02-06 07:11:01 +0100 | [diff] [blame] | 2553 | if (IS_ERR(cdns_phy->sd_base)) |
| 2554 | return PTR_ERR(cdns_phy->sd_base); |
| 2555 | |
| 2556 | subnodes = of_get_available_child_count(dev->of_node); |
| 2557 | if (subnodes == 0) { |
| 2558 | dev_err(dev, "No available link subnodes found\n"); |
| 2559 | return -EINVAL; |
Swapnil Jakhade | afa4ba0 | 2020-02-06 07:11:01 +0100 | [diff] [blame] | 2560 | } |
| 2561 | |
Swapnil Jakhade | 2e70c84 | 2020-09-16 20:28:28 +0200 | [diff] [blame] | 2562 | ret = cdns_torrent_regmap_init(cdns_phy); |
| 2563 | if (ret) |
| 2564 | return ret; |
| 2565 | |
| 2566 | ret = cdns_torrent_regfield_init(cdns_phy); |
| 2567 | if (ret) |
| 2568 | return ret; |
| 2569 | |
Kishon Vijay Abraham I | 2cca022 | 2021-03-10 17:38:40 +0530 | [diff] [blame] | 2570 | ret = cdns_torrent_clk_register(cdns_phy); |
| 2571 | if (ret) |
| 2572 | return ret; |
| 2573 | |
Kishon Vijay Abraham I | b69d39f | 2021-03-30 16:31:36 +0530 | [diff] [blame] | 2574 | regmap_field_read(cdns_phy->phy_pma_cmn_ctrl_1, &already_configured); |
Swapnil Jakhade | 07084c9 | 2020-09-17 09:30:40 +0200 | [diff] [blame] | 2575 | |
Kishon Vijay Abraham I | b69d39f | 2021-03-30 16:31:36 +0530 | [diff] [blame] | 2576 | if (!already_configured) { |
| 2577 | ret = cdns_torrent_reset(cdns_phy); |
| 2578 | if (ret) |
| 2579 | goto clk_cleanup; |
Swapnil Jakhade | 07084c9 | 2020-09-17 09:30:40 +0200 | [diff] [blame] | 2580 | |
Kishon Vijay Abraham I | b69d39f | 2021-03-30 16:31:36 +0530 | [diff] [blame] | 2581 | ret = cdns_torrent_clk(cdns_phy); |
| 2582 | if (ret) |
| 2583 | goto clk_cleanup; |
| 2584 | |
| 2585 | /* Enable APB */ |
| 2586 | reset_control_deassert(cdns_phy->apb_rst); |
| 2587 | } |
Swapnil Jakhade | 15c6a04 | 2020-09-17 09:30:36 +0200 | [diff] [blame] | 2588 | |
Swapnil Jakhade | afa4ba0 | 2020-02-06 07:11:01 +0100 | [diff] [blame] | 2589 | for_each_available_child_of_node(dev->of_node, child) { |
| 2590 | struct phy *gphy; |
| 2591 | |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 2592 | /* PHY subnode name must be 'phy'. */ |
| 2593 | if (!(of_node_name_eq(child, "phy"))) |
| 2594 | continue; |
| 2595 | |
Swapnil Jakhade | afa4ba0 | 2020-02-06 07:11:01 +0100 | [diff] [blame] | 2596 | cdns_phy->phys[node].lnk_rst = |
| 2597 | of_reset_control_array_get_exclusive(child); |
| 2598 | if (IS_ERR(cdns_phy->phys[node].lnk_rst)) { |
| 2599 | dev_err(dev, "%s: failed to get reset\n", |
| 2600 | child->full_name); |
| 2601 | ret = PTR_ERR(cdns_phy->phys[node].lnk_rst); |
| 2602 | goto put_lnk_rst; |
| 2603 | } |
| 2604 | |
| 2605 | if (of_property_read_u32(child, "reg", |
| 2606 | &cdns_phy->phys[node].mlane)) { |
| 2607 | dev_err(dev, "%s: No \"reg\"-property.\n", |
| 2608 | child->full_name); |
| 2609 | ret = -EINVAL; |
| 2610 | goto put_child; |
| 2611 | } |
| 2612 | |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 2613 | if (of_property_read_u32(child, "cdns,phy-type", &phy_type)) { |
Swapnil Jakhade | afa4ba0 | 2020-02-06 07:11:01 +0100 | [diff] [blame] | 2614 | dev_err(dev, "%s: No \"cdns,phy-type\"-property.\n", |
| 2615 | child->full_name); |
| 2616 | ret = -EINVAL; |
| 2617 | goto put_child; |
| 2618 | } |
| 2619 | |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 2620 | switch (phy_type) { |
| 2621 | case PHY_TYPE_PCIE: |
| 2622 | cdns_phy->phys[node].phy_type = TYPE_PCIE; |
| 2623 | break; |
| 2624 | case PHY_TYPE_DP: |
| 2625 | cdns_phy->phys[node].phy_type = TYPE_DP; |
| 2626 | break; |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 2627 | case PHY_TYPE_SGMII: |
| 2628 | cdns_phy->phys[node].phy_type = TYPE_SGMII; |
| 2629 | break; |
| 2630 | case PHY_TYPE_QSGMII: |
| 2631 | cdns_phy->phys[node].phy_type = TYPE_QSGMII; |
| 2632 | break; |
Swapnil Jakhade | 9855d84 | 2020-09-17 09:30:44 +0200 | [diff] [blame] | 2633 | case PHY_TYPE_USB3: |
| 2634 | cdns_phy->phys[node].phy_type = TYPE_USB; |
| 2635 | break; |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 2636 | default: |
| 2637 | dev_err(dev, "Unsupported protocol\n"); |
| 2638 | ret = -EINVAL; |
| 2639 | goto put_child; |
| 2640 | } |
| 2641 | |
Swapnil Jakhade | d09945e | 2020-09-16 20:28:29 +0200 | [diff] [blame] | 2642 | if (of_property_read_u32(child, "cdns,num-lanes", |
| 2643 | &cdns_phy->phys[node].num_lanes)) { |
| 2644 | dev_err(dev, "%s: No \"cdns,num-lanes\"-property.\n", |
| 2645 | child->full_name); |
| 2646 | ret = -EINVAL; |
| 2647 | goto put_child; |
| 2648 | } |
| 2649 | |
| 2650 | total_num_lanes += cdns_phy->phys[node].num_lanes; |
Swapnil Jakhade | afa4ba0 | 2020-02-06 07:11:01 +0100 | [diff] [blame] | 2651 | |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 2652 | /* Get SSC mode */ |
| 2653 | cdns_phy->phys[node].ssc_mode = NO_SSC; |
| 2654 | of_property_read_u32(child, "cdns,ssc-mode", |
| 2655 | &cdns_phy->phys[node].ssc_mode); |
| 2656 | |
Kishon Vijay Abraham I | b69d39f | 2021-03-30 16:31:36 +0530 | [diff] [blame] | 2657 | if (!already_configured) |
| 2658 | gphy = devm_phy_create(dev, child, &cdns_torrent_phy_ops); |
| 2659 | else |
| 2660 | gphy = devm_phy_create(dev, child, &noop_ops); |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 2661 | if (IS_ERR(gphy)) { |
| 2662 | ret = PTR_ERR(gphy); |
| 2663 | goto put_child; |
| 2664 | } |
| 2665 | |
| 2666 | if (cdns_phy->phys[node].phy_type == TYPE_DP) { |
Swapnil Jakhade | afa4ba0 | 2020-02-06 07:11:01 +0100 | [diff] [blame] | 2667 | switch (cdns_phy->phys[node].num_lanes) { |
| 2668 | case 1: |
| 2669 | case 2: |
| 2670 | case 4: |
| 2671 | /* valid number of lanes */ |
| 2672 | break; |
| 2673 | default: |
| 2674 | dev_err(dev, "unsupported number of lanes: %d\n", |
| 2675 | cdns_phy->phys[node].num_lanes); |
| 2676 | ret = -EINVAL; |
| 2677 | goto put_child; |
| 2678 | } |
| 2679 | |
| 2680 | cdns_phy->max_bit_rate = DEFAULT_MAX_BIT_RATE; |
| 2681 | of_property_read_u32(child, "cdns,max-bit-rate", |
| 2682 | &cdns_phy->max_bit_rate); |
| 2683 | |
| 2684 | switch (cdns_phy->max_bit_rate) { |
| 2685 | case 1620: |
| 2686 | case 2160: |
| 2687 | case 2430: |
| 2688 | case 2700: |
| 2689 | case 3240: |
| 2690 | case 4320: |
| 2691 | case 5400: |
| 2692 | case 8100: |
| 2693 | /* valid bit rate */ |
| 2694 | break; |
| 2695 | default: |
| 2696 | dev_err(dev, "unsupported max bit rate: %dMbps\n", |
| 2697 | cdns_phy->max_bit_rate); |
| 2698 | ret = -EINVAL; |
| 2699 | goto put_child; |
| 2700 | } |
| 2701 | |
| 2702 | /* DPTX registers */ |
Swapnil Jakhade | 46d205a | 2020-09-16 20:28:26 +0200 | [diff] [blame] | 2703 | cdns_phy->base = devm_platform_ioremap_resource(pdev, 1); |
Swapnil Jakhade | afa4ba0 | 2020-02-06 07:11:01 +0100 | [diff] [blame] | 2704 | if (IS_ERR(cdns_phy->base)) { |
| 2705 | ret = PTR_ERR(cdns_phy->base); |
| 2706 | goto put_child; |
| 2707 | } |
| 2708 | |
Swapnil Jakhade | 2e70c84 | 2020-09-16 20:28:28 +0200 | [diff] [blame] | 2709 | if (!init_dp_regmap) { |
| 2710 | ret = cdns_torrent_dp_regmap_init(cdns_phy); |
| 2711 | if (ret) |
| 2712 | goto put_child; |
| 2713 | |
| 2714 | ret = cdns_torrent_dp_regfield_init(cdns_phy); |
| 2715 | if (ret) |
| 2716 | goto put_child; |
| 2717 | |
| 2718 | init_dp_regmap++; |
| 2719 | } |
| 2720 | |
Swapnil Jakhade | 84f55df | 2021-07-28 16:54:53 +0200 | [diff] [blame] | 2721 | dev_dbg(dev, "DP max bit rate %d.%03d Gbps\n", |
| 2722 | cdns_phy->max_bit_rate / 1000, |
| 2723 | cdns_phy->max_bit_rate % 1000); |
Swapnil Jakhade | 0ffcc37 | 2020-09-11 08:18:34 +0200 | [diff] [blame] | 2724 | |
| 2725 | gphy->attrs.bus_width = cdns_phy->phys[node].num_lanes; |
| 2726 | gphy->attrs.max_link_rate = cdns_phy->max_bit_rate; |
| 2727 | gphy->attrs.mode = PHY_MODE_DP; |
Swapnil Jakhade | afa4ba0 | 2020-02-06 07:11:01 +0100 | [diff] [blame] | 2728 | } |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 2729 | |
Swapnil Jakhade | afa4ba0 | 2020-02-06 07:11:01 +0100 | [diff] [blame] | 2730 | cdns_phy->phys[node].phy = gphy; |
| 2731 | phy_set_drvdata(gphy, &cdns_phy->phys[node]); |
| 2732 | |
| 2733 | node++; |
| 2734 | } |
| 2735 | cdns_phy->nsubnodes = node; |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 2736 | |
Swapnil Jakhade | d09945e | 2020-09-16 20:28:29 +0200 | [diff] [blame] | 2737 | if (total_num_lanes > MAX_NUM_LANES) { |
| 2738 | dev_err(dev, "Invalid lane configuration\n"); |
Dan Carpenter | 266df28 | 2020-12-17 14:04:59 +0300 | [diff] [blame] | 2739 | ret = -EINVAL; |
Swapnil Jakhade | d09945e | 2020-09-16 20:28:29 +0200 | [diff] [blame] | 2740 | goto put_lnk_rst; |
| 2741 | } |
| 2742 | |
Kishon Vijay Abraham I | b69d39f | 2021-03-30 16:31:36 +0530 | [diff] [blame] | 2743 | if (cdns_phy->nsubnodes > 1 && !already_configured) { |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 2744 | ret = cdns_torrent_phy_configure_multilink(cdns_phy); |
| 2745 | if (ret) |
| 2746 | goto put_lnk_rst; |
| 2747 | } |
| 2748 | |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 2749 | phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); |
Swapnil Jakhade | afa4ba0 | 2020-02-06 07:11:01 +0100 | [diff] [blame] | 2750 | if (IS_ERR(phy_provider)) { |
| 2751 | ret = PTR_ERR(phy_provider); |
| 2752 | goto put_lnk_rst; |
| 2753 | } |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 2754 | |
Swapnil Jakhade | 84f55df | 2021-07-28 16:54:53 +0200 | [diff] [blame] | 2755 | if (cdns_phy->nsubnodes > 1) |
| 2756 | dev_dbg(dev, "Multi-link: %s (%d lanes) & %s (%d lanes)", |
| 2757 | cdns_torrent_get_phy_type(cdns_phy->phys[0].phy_type), |
| 2758 | cdns_phy->phys[0].num_lanes, |
| 2759 | cdns_torrent_get_phy_type(cdns_phy->phys[1].phy_type), |
| 2760 | cdns_phy->phys[1].num_lanes); |
| 2761 | else |
| 2762 | dev_dbg(dev, "Single link: %s (%d lanes)", |
| 2763 | cdns_torrent_get_phy_type(cdns_phy->phys[0].phy_type), |
| 2764 | cdns_phy->phys[0].num_lanes); |
| 2765 | |
Swapnil Jakhade | afa4ba0 | 2020-02-06 07:11:01 +0100 | [diff] [blame] | 2766 | return 0; |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 2767 | |
Swapnil Jakhade | afa4ba0 | 2020-02-06 07:11:01 +0100 | [diff] [blame] | 2768 | put_child: |
| 2769 | node++; |
| 2770 | put_lnk_rst: |
| 2771 | for (i = 0; i < node; i++) |
| 2772 | reset_control_put(cdns_phy->phys[i].lnk_rst); |
| 2773 | of_node_put(child); |
Swapnil Jakhade | 15c6a04 | 2020-09-17 09:30:36 +0200 | [diff] [blame] | 2774 | reset_control_assert(cdns_phy->apb_rst); |
Swapnil Jakhade | 07084c9 | 2020-09-17 09:30:40 +0200 | [diff] [blame] | 2775 | clk_disable_unprepare(cdns_phy->clk); |
Kishon Vijay Abraham I | 2cca022 | 2021-03-10 17:38:40 +0530 | [diff] [blame] | 2776 | clk_cleanup: |
| 2777 | cdns_torrent_clk_cleanup(cdns_phy); |
Swapnil Jakhade | afa4ba0 | 2020-02-06 07:11:01 +0100 | [diff] [blame] | 2778 | return ret; |
| 2779 | } |
| 2780 | |
| 2781 | static int cdns_torrent_phy_remove(struct platform_device *pdev) |
| 2782 | { |
| 2783 | struct cdns_torrent_phy *cdns_phy = platform_get_drvdata(pdev); |
| 2784 | int i; |
| 2785 | |
| 2786 | reset_control_assert(cdns_phy->phy_rst); |
Swapnil Jakhade | 15c6a04 | 2020-09-17 09:30:36 +0200 | [diff] [blame] | 2787 | reset_control_assert(cdns_phy->apb_rst); |
Swapnil Jakhade | afa4ba0 | 2020-02-06 07:11:01 +0100 | [diff] [blame] | 2788 | for (i = 0; i < cdns_phy->nsubnodes; i++) { |
| 2789 | reset_control_assert(cdns_phy->phys[i].lnk_rst); |
| 2790 | reset_control_put(cdns_phy->phys[i].lnk_rst); |
| 2791 | } |
| 2792 | |
Swapnil Jakhade | 07084c9 | 2020-09-17 09:30:40 +0200 | [diff] [blame] | 2793 | clk_disable_unprepare(cdns_phy->clk); |
Kishon Vijay Abraham I | 2cca022 | 2021-03-10 17:38:40 +0530 | [diff] [blame] | 2794 | cdns_torrent_clk_cleanup(cdns_phy); |
Swapnil Jakhade | 07084c9 | 2020-09-17 09:30:40 +0200 | [diff] [blame] | 2795 | |
Swapnil Jakhade | afa4ba0 | 2020-02-06 07:11:01 +0100 | [diff] [blame] | 2796 | return 0; |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 2797 | } |
| 2798 | |
Swapnil Jakhade | da055e5 | 2021-07-28 16:54:50 +0200 | [diff] [blame] | 2799 | /* Single DisplayPort(DP) link configuration */ |
| 2800 | static struct cdns_reg_pairs sl_dp_link_cmn_regs[] = { |
| 2801 | {0x0000, PHY_PLL_CFG}, |
| 2802 | }; |
| 2803 | |
| 2804 | static struct cdns_reg_pairs sl_dp_xcvr_diag_ln_regs[] = { |
| 2805 | {0x0000, XCVR_DIAG_HSCLK_SEL}, |
| 2806 | {0x0001, XCVR_DIAG_PLLDRC_CTRL} |
| 2807 | }; |
| 2808 | |
| 2809 | static struct cdns_torrent_vals sl_dp_link_cmn_vals = { |
| 2810 | .reg_pairs = sl_dp_link_cmn_regs, |
| 2811 | .num_regs = ARRAY_SIZE(sl_dp_link_cmn_regs), |
| 2812 | }; |
| 2813 | |
| 2814 | static struct cdns_torrent_vals sl_dp_xcvr_diag_ln_vals = { |
| 2815 | .reg_pairs = sl_dp_xcvr_diag_ln_regs, |
| 2816 | .num_regs = ARRAY_SIZE(sl_dp_xcvr_diag_ln_regs), |
| 2817 | }; |
| 2818 | |
| 2819 | /* Single DP, 19.2 MHz Ref clk, no SSC */ |
| 2820 | static struct cdns_reg_pairs sl_dp_19_2_no_ssc_cmn_regs[] = { |
| 2821 | {0x0014, CMN_SSM_BIAS_TMR}, |
| 2822 | {0x0027, CMN_PLLSM0_PLLPRE_TMR}, |
| 2823 | {0x00A1, CMN_PLLSM0_PLLLOCK_TMR}, |
| 2824 | {0x0027, CMN_PLLSM1_PLLPRE_TMR}, |
| 2825 | {0x00A1, CMN_PLLSM1_PLLLOCK_TMR}, |
| 2826 | {0x0060, CMN_BGCAL_INIT_TMR}, |
| 2827 | {0x0060, CMN_BGCAL_ITER_TMR}, |
| 2828 | {0x0014, CMN_IBCAL_INIT_TMR}, |
| 2829 | {0x0018, CMN_TXPUCAL_INIT_TMR}, |
| 2830 | {0x0005, CMN_TXPUCAL_ITER_TMR}, |
| 2831 | {0x0018, CMN_TXPDCAL_INIT_TMR}, |
| 2832 | {0x0005, CMN_TXPDCAL_ITER_TMR}, |
| 2833 | {0x0240, CMN_RXCAL_INIT_TMR}, |
| 2834 | {0x0005, CMN_RXCAL_ITER_TMR}, |
| 2835 | {0x0002, CMN_SD_CAL_INIT_TMR}, |
| 2836 | {0x0002, CMN_SD_CAL_ITER_TMR}, |
| 2837 | {0x000B, CMN_SD_CAL_REFTIM_START}, |
| 2838 | {0x0137, CMN_SD_CAL_PLLCNT_START}, |
| 2839 | {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, |
| 2840 | {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, |
| 2841 | {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, |
| 2842 | {0x0004, CMN_PLL0_DSM_DIAG_M0}, |
| 2843 | {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, |
| 2844 | {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, |
| 2845 | {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, |
| 2846 | {0x0004, CMN_PLL1_DSM_DIAG_M0}, |
| 2847 | {0x00C0, CMN_PLL0_VCOCAL_INIT_TMR}, |
| 2848 | {0x0004, CMN_PLL0_VCOCAL_ITER_TMR}, |
| 2849 | {0x00C0, CMN_PLL1_VCOCAL_INIT_TMR}, |
| 2850 | {0x0004, CMN_PLL1_VCOCAL_ITER_TMR}, |
| 2851 | {0x0260, CMN_PLL0_VCOCAL_REFTIM_START}, |
| 2852 | {0x0003, CMN_PLL0_VCOCAL_TCTRL}, |
| 2853 | {0x0260, CMN_PLL1_VCOCAL_REFTIM_START}, |
| 2854 | {0x0003, CMN_PLL1_VCOCAL_TCTRL} |
| 2855 | }; |
| 2856 | |
| 2857 | static struct cdns_reg_pairs sl_dp_19_2_no_ssc_tx_ln_regs[] = { |
| 2858 | {0x0780, TX_RCVDET_ST_TMR}, |
| 2859 | {0x00FB, TX_PSC_A0}, |
| 2860 | {0x04AA, TX_PSC_A2}, |
| 2861 | {0x04AA, TX_PSC_A3}, |
| 2862 | {0x000F, XCVR_DIAG_BIDI_CTRL} |
| 2863 | }; |
| 2864 | |
| 2865 | static struct cdns_reg_pairs sl_dp_19_2_no_ssc_rx_ln_regs[] = { |
| 2866 | {0x0000, RX_PSC_A0}, |
| 2867 | {0x0000, RX_PSC_A2}, |
| 2868 | {0x0000, RX_PSC_A3}, |
| 2869 | {0x0000, RX_PSC_CAL}, |
| 2870 | {0x0000, RX_REE_GCSM1_CTRL}, |
| 2871 | {0x0000, RX_REE_GCSM2_CTRL}, |
| 2872 | {0x0000, RX_REE_PERGCSM_CTRL} |
| 2873 | }; |
| 2874 | |
| 2875 | static struct cdns_torrent_vals sl_dp_19_2_no_ssc_cmn_vals = { |
| 2876 | .reg_pairs = sl_dp_19_2_no_ssc_cmn_regs, |
| 2877 | .num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_cmn_regs), |
| 2878 | }; |
| 2879 | |
| 2880 | static struct cdns_torrent_vals sl_dp_19_2_no_ssc_tx_ln_vals = { |
| 2881 | .reg_pairs = sl_dp_19_2_no_ssc_tx_ln_regs, |
| 2882 | .num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_tx_ln_regs), |
| 2883 | }; |
| 2884 | |
| 2885 | static struct cdns_torrent_vals sl_dp_19_2_no_ssc_rx_ln_vals = { |
| 2886 | .reg_pairs = sl_dp_19_2_no_ssc_rx_ln_regs, |
| 2887 | .num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_rx_ln_regs), |
| 2888 | }; |
| 2889 | |
| 2890 | /* Single DP, 25 MHz Ref clk, no SSC */ |
| 2891 | static struct cdns_reg_pairs sl_dp_25_no_ssc_cmn_regs[] = { |
| 2892 | {0x0019, CMN_SSM_BIAS_TMR}, |
| 2893 | {0x0032, CMN_PLLSM0_PLLPRE_TMR}, |
| 2894 | {0x00D1, CMN_PLLSM0_PLLLOCK_TMR}, |
| 2895 | {0x0032, CMN_PLLSM1_PLLPRE_TMR}, |
| 2896 | {0x00D1, CMN_PLLSM1_PLLLOCK_TMR}, |
| 2897 | {0x007D, CMN_BGCAL_INIT_TMR}, |
| 2898 | {0x007D, CMN_BGCAL_ITER_TMR}, |
| 2899 | {0x0019, CMN_IBCAL_INIT_TMR}, |
| 2900 | {0x001E, CMN_TXPUCAL_INIT_TMR}, |
| 2901 | {0x0006, CMN_TXPUCAL_ITER_TMR}, |
| 2902 | {0x001E, CMN_TXPDCAL_INIT_TMR}, |
| 2903 | {0x0006, CMN_TXPDCAL_ITER_TMR}, |
| 2904 | {0x02EE, CMN_RXCAL_INIT_TMR}, |
| 2905 | {0x0006, CMN_RXCAL_ITER_TMR}, |
| 2906 | {0x0002, CMN_SD_CAL_INIT_TMR}, |
| 2907 | {0x0002, CMN_SD_CAL_ITER_TMR}, |
| 2908 | {0x000E, CMN_SD_CAL_REFTIM_START}, |
| 2909 | {0x012B, CMN_SD_CAL_PLLCNT_START}, |
| 2910 | {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, |
| 2911 | {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, |
| 2912 | {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, |
| 2913 | {0x0004, CMN_PLL0_DSM_DIAG_M0}, |
| 2914 | {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, |
| 2915 | {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, |
| 2916 | {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, |
| 2917 | {0x0004, CMN_PLL1_DSM_DIAG_M0}, |
| 2918 | {0x00FA, CMN_PLL0_VCOCAL_INIT_TMR}, |
| 2919 | {0x0004, CMN_PLL0_VCOCAL_ITER_TMR}, |
| 2920 | {0x00FA, CMN_PLL1_VCOCAL_INIT_TMR}, |
| 2921 | {0x0004, CMN_PLL1_VCOCAL_ITER_TMR}, |
| 2922 | {0x0317, CMN_PLL0_VCOCAL_REFTIM_START}, |
| 2923 | {0x0003, CMN_PLL0_VCOCAL_TCTRL}, |
| 2924 | {0x0317, CMN_PLL1_VCOCAL_REFTIM_START}, |
| 2925 | {0x0003, CMN_PLL1_VCOCAL_TCTRL} |
| 2926 | }; |
| 2927 | |
| 2928 | static struct cdns_reg_pairs sl_dp_25_no_ssc_tx_ln_regs[] = { |
| 2929 | {0x09C4, TX_RCVDET_ST_TMR}, |
| 2930 | {0x00FB, TX_PSC_A0}, |
| 2931 | {0x04AA, TX_PSC_A2}, |
| 2932 | {0x04AA, TX_PSC_A3}, |
| 2933 | {0x000F, XCVR_DIAG_BIDI_CTRL} |
| 2934 | }; |
| 2935 | |
| 2936 | static struct cdns_reg_pairs sl_dp_25_no_ssc_rx_ln_regs[] = { |
| 2937 | {0x0000, RX_PSC_A0}, |
| 2938 | {0x0000, RX_PSC_A2}, |
| 2939 | {0x0000, RX_PSC_A3}, |
| 2940 | {0x0000, RX_PSC_CAL}, |
| 2941 | {0x0000, RX_REE_GCSM1_CTRL}, |
| 2942 | {0x0000, RX_REE_GCSM2_CTRL}, |
| 2943 | {0x0000, RX_REE_PERGCSM_CTRL} |
| 2944 | }; |
| 2945 | |
| 2946 | static struct cdns_torrent_vals sl_dp_25_no_ssc_cmn_vals = { |
| 2947 | .reg_pairs = sl_dp_25_no_ssc_cmn_regs, |
| 2948 | .num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_cmn_regs), |
| 2949 | }; |
| 2950 | |
| 2951 | static struct cdns_torrent_vals sl_dp_25_no_ssc_tx_ln_vals = { |
| 2952 | .reg_pairs = sl_dp_25_no_ssc_tx_ln_regs, |
| 2953 | .num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_tx_ln_regs), |
| 2954 | }; |
| 2955 | |
| 2956 | static struct cdns_torrent_vals sl_dp_25_no_ssc_rx_ln_vals = { |
| 2957 | .reg_pairs = sl_dp_25_no_ssc_rx_ln_regs, |
| 2958 | .num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_rx_ln_regs), |
| 2959 | }; |
| 2960 | |
Swapnil Jakhade | 1cc4551 | 2021-07-28 16:54:51 +0200 | [diff] [blame] | 2961 | /* Single DP, 100 MHz Ref clk, no SSC */ |
| 2962 | static struct cdns_reg_pairs sl_dp_100_no_ssc_cmn_regs[] = { |
| 2963 | {0x0003, CMN_PLL0_VCOCAL_TCTRL}, |
| 2964 | {0x0003, CMN_PLL1_VCOCAL_TCTRL} |
| 2965 | }; |
| 2966 | |
| 2967 | static struct cdns_reg_pairs sl_dp_100_no_ssc_tx_ln_regs[] = { |
| 2968 | {0x00FB, TX_PSC_A0}, |
| 2969 | {0x04AA, TX_PSC_A2}, |
| 2970 | {0x04AA, TX_PSC_A3}, |
| 2971 | {0x000F, XCVR_DIAG_BIDI_CTRL} |
| 2972 | }; |
| 2973 | |
| 2974 | static struct cdns_reg_pairs sl_dp_100_no_ssc_rx_ln_regs[] = { |
| 2975 | {0x0000, RX_PSC_A0}, |
| 2976 | {0x0000, RX_PSC_A2}, |
| 2977 | {0x0000, RX_PSC_A3}, |
| 2978 | {0x0000, RX_PSC_CAL}, |
| 2979 | {0x0000, RX_REE_GCSM1_CTRL}, |
| 2980 | {0x0000, RX_REE_GCSM2_CTRL}, |
| 2981 | {0x0000, RX_REE_PERGCSM_CTRL} |
| 2982 | }; |
| 2983 | |
| 2984 | static struct cdns_torrent_vals sl_dp_100_no_ssc_cmn_vals = { |
| 2985 | .reg_pairs = sl_dp_100_no_ssc_cmn_regs, |
| 2986 | .num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_cmn_regs), |
| 2987 | }; |
| 2988 | |
| 2989 | static struct cdns_torrent_vals sl_dp_100_no_ssc_tx_ln_vals = { |
| 2990 | .reg_pairs = sl_dp_100_no_ssc_tx_ln_regs, |
| 2991 | .num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_tx_ln_regs), |
| 2992 | }; |
| 2993 | |
| 2994 | static struct cdns_torrent_vals sl_dp_100_no_ssc_rx_ln_vals = { |
| 2995 | .reg_pairs = sl_dp_100_no_ssc_rx_ln_regs, |
| 2996 | .num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_rx_ln_regs), |
| 2997 | }; |
| 2998 | |
Swapnil Jakhade | 6fd428f | 2020-09-17 09:30:46 +0200 | [diff] [blame] | 2999 | /* USB and SGMII/QSGMII link configuration */ |
| 3000 | static struct cdns_reg_pairs usb_sgmii_link_cmn_regs[] = { |
| 3001 | {0x0002, PHY_PLL_CFG}, |
| 3002 | {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0}, |
| 3003 | {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0} |
| 3004 | }; |
| 3005 | |
| 3006 | static struct cdns_reg_pairs usb_sgmii_xcvr_diag_ln_regs[] = { |
| 3007 | {0x0000, XCVR_DIAG_HSCLK_SEL}, |
| 3008 | {0x0001, XCVR_DIAG_HSCLK_DIV}, |
| 3009 | {0x0041, XCVR_DIAG_PLLDRC_CTRL} |
| 3010 | }; |
| 3011 | |
| 3012 | static struct cdns_reg_pairs sgmii_usb_xcvr_diag_ln_regs[] = { |
| 3013 | {0x0011, XCVR_DIAG_HSCLK_SEL}, |
| 3014 | {0x0003, XCVR_DIAG_HSCLK_DIV}, |
| 3015 | {0x009B, XCVR_DIAG_PLLDRC_CTRL} |
| 3016 | }; |
| 3017 | |
| 3018 | static struct cdns_torrent_vals usb_sgmii_link_cmn_vals = { |
| 3019 | .reg_pairs = usb_sgmii_link_cmn_regs, |
| 3020 | .num_regs = ARRAY_SIZE(usb_sgmii_link_cmn_regs), |
| 3021 | }; |
| 3022 | |
| 3023 | static struct cdns_torrent_vals usb_sgmii_xcvr_diag_ln_vals = { |
| 3024 | .reg_pairs = usb_sgmii_xcvr_diag_ln_regs, |
| 3025 | .num_regs = ARRAY_SIZE(usb_sgmii_xcvr_diag_ln_regs), |
| 3026 | }; |
| 3027 | |
| 3028 | static struct cdns_torrent_vals sgmii_usb_xcvr_diag_ln_vals = { |
| 3029 | .reg_pairs = sgmii_usb_xcvr_diag_ln_regs, |
| 3030 | .num_regs = ARRAY_SIZE(sgmii_usb_xcvr_diag_ln_regs), |
| 3031 | }; |
| 3032 | |
Swapnil Jakhade | 4acea47 | 2020-09-17 09:30:45 +0200 | [diff] [blame] | 3033 | /* PCIe and USB Unique SSC link configuration */ |
| 3034 | static struct cdns_reg_pairs pcie_usb_link_cmn_regs[] = { |
| 3035 | {0x0003, PHY_PLL_CFG}, |
| 3036 | {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}, |
| 3037 | {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1}, |
| 3038 | {0x8600, CMN_PDIAG_PLL1_CLK_SEL_M0} |
| 3039 | }; |
| 3040 | |
| 3041 | static struct cdns_reg_pairs pcie_usb_xcvr_diag_ln_regs[] = { |
| 3042 | {0x0000, XCVR_DIAG_HSCLK_SEL}, |
| 3043 | {0x0001, XCVR_DIAG_HSCLK_DIV}, |
| 3044 | {0x0012, XCVR_DIAG_PLLDRC_CTRL} |
| 3045 | }; |
| 3046 | |
| 3047 | static struct cdns_reg_pairs usb_pcie_xcvr_diag_ln_regs[] = { |
| 3048 | {0x0011, XCVR_DIAG_HSCLK_SEL}, |
| 3049 | {0x0001, XCVR_DIAG_HSCLK_DIV}, |
| 3050 | {0x00C9, XCVR_DIAG_PLLDRC_CTRL} |
| 3051 | }; |
| 3052 | |
| 3053 | static struct cdns_torrent_vals pcie_usb_link_cmn_vals = { |
| 3054 | .reg_pairs = pcie_usb_link_cmn_regs, |
| 3055 | .num_regs = ARRAY_SIZE(pcie_usb_link_cmn_regs), |
| 3056 | }; |
| 3057 | |
| 3058 | static struct cdns_torrent_vals pcie_usb_xcvr_diag_ln_vals = { |
| 3059 | .reg_pairs = pcie_usb_xcvr_diag_ln_regs, |
| 3060 | .num_regs = ARRAY_SIZE(pcie_usb_xcvr_diag_ln_regs), |
| 3061 | }; |
| 3062 | |
| 3063 | static struct cdns_torrent_vals usb_pcie_xcvr_diag_ln_vals = { |
| 3064 | .reg_pairs = usb_pcie_xcvr_diag_ln_regs, |
| 3065 | .num_regs = ARRAY_SIZE(usb_pcie_xcvr_diag_ln_regs), |
| 3066 | }; |
| 3067 | |
| 3068 | /* USB 100 MHz Ref clk, internal SSC */ |
| 3069 | static struct cdns_reg_pairs usb_100_int_ssc_cmn_regs[] = { |
| 3070 | {0x0004, CMN_PLL0_DSM_DIAG_M0}, |
| 3071 | {0x0004, CMN_PLL0_DSM_DIAG_M1}, |
| 3072 | {0x0004, CMN_PLL1_DSM_DIAG_M0}, |
| 3073 | {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, |
| 3074 | {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1}, |
| 3075 | {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, |
| 3076 | {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, |
| 3077 | {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1}, |
| 3078 | {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, |
| 3079 | {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, |
| 3080 | {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1}, |
| 3081 | {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, |
| 3082 | {0x0064, CMN_PLL0_INTDIV_M0}, |
| 3083 | {0x0050, CMN_PLL0_INTDIV_M1}, |
| 3084 | {0x0064, CMN_PLL1_INTDIV_M0}, |
| 3085 | {0x0002, CMN_PLL0_FRACDIVH_M0}, |
| 3086 | {0x0002, CMN_PLL0_FRACDIVH_M1}, |
| 3087 | {0x0002, CMN_PLL1_FRACDIVH_M0}, |
| 3088 | {0x0044, CMN_PLL0_HIGH_THR_M0}, |
| 3089 | {0x0036, CMN_PLL0_HIGH_THR_M1}, |
| 3090 | {0x0044, CMN_PLL1_HIGH_THR_M0}, |
| 3091 | {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, |
| 3092 | {0x0002, CMN_PDIAG_PLL0_CTRL_M1}, |
| 3093 | {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, |
| 3094 | {0x0001, CMN_PLL0_SS_CTRL1_M0}, |
| 3095 | {0x0001, CMN_PLL0_SS_CTRL1_M1}, |
| 3096 | {0x0001, CMN_PLL1_SS_CTRL1_M0}, |
| 3097 | {0x011B, CMN_PLL0_SS_CTRL2_M0}, |
| 3098 | {0x011B, CMN_PLL0_SS_CTRL2_M1}, |
| 3099 | {0x011B, CMN_PLL1_SS_CTRL2_M0}, |
| 3100 | {0x006E, CMN_PLL0_SS_CTRL3_M0}, |
| 3101 | {0x0058, CMN_PLL0_SS_CTRL3_M1}, |
| 3102 | {0x006E, CMN_PLL1_SS_CTRL3_M0}, |
| 3103 | {0x000E, CMN_PLL0_SS_CTRL4_M0}, |
| 3104 | {0x0012, CMN_PLL0_SS_CTRL4_M1}, |
| 3105 | {0x000E, CMN_PLL1_SS_CTRL4_M0}, |
| 3106 | {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, |
| 3107 | {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, |
| 3108 | {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, |
| 3109 | {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, |
Swapnil Jakhade | 4acea47 | 2020-09-17 09:30:45 +0200 | [diff] [blame] | 3110 | {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, |
| 3111 | {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, |
| 3112 | {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, |
| 3113 | {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, |
| 3114 | {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, |
| 3115 | {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}, |
| 3116 | {0x8200, CMN_CDIAG_CDB_PWRI_OVRD}, |
Swapnil Jakhade | ed9e07f | 2021-03-04 07:08:16 +0100 | [diff] [blame] | 3117 | {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}, |
| 3118 | {0x007F, CMN_TXPUCAL_TUNE}, |
| 3119 | {0x007F, CMN_TXPDCAL_TUNE} |
Swapnil Jakhade | 4acea47 | 2020-09-17 09:30:45 +0200 | [diff] [blame] | 3120 | }; |
| 3121 | |
| 3122 | static struct cdns_torrent_vals usb_100_int_ssc_cmn_vals = { |
| 3123 | .reg_pairs = usb_100_int_ssc_cmn_regs, |
| 3124 | .num_regs = ARRAY_SIZE(usb_100_int_ssc_cmn_regs), |
| 3125 | }; |
| 3126 | |
Swapnil Jakhade | 9855d84 | 2020-09-17 09:30:44 +0200 | [diff] [blame] | 3127 | /* Single USB link configuration */ |
| 3128 | static struct cdns_reg_pairs sl_usb_link_cmn_regs[] = { |
| 3129 | {0x0000, PHY_PLL_CFG}, |
| 3130 | {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0} |
| 3131 | }; |
| 3132 | |
| 3133 | static struct cdns_reg_pairs sl_usb_xcvr_diag_ln_regs[] = { |
| 3134 | {0x0000, XCVR_DIAG_HSCLK_SEL}, |
| 3135 | {0x0001, XCVR_DIAG_HSCLK_DIV}, |
| 3136 | {0x0041, XCVR_DIAG_PLLDRC_CTRL} |
| 3137 | }; |
| 3138 | |
| 3139 | static struct cdns_torrent_vals sl_usb_link_cmn_vals = { |
| 3140 | .reg_pairs = sl_usb_link_cmn_regs, |
| 3141 | .num_regs = ARRAY_SIZE(sl_usb_link_cmn_regs), |
| 3142 | }; |
| 3143 | |
| 3144 | static struct cdns_torrent_vals sl_usb_xcvr_diag_ln_vals = { |
| 3145 | .reg_pairs = sl_usb_xcvr_diag_ln_regs, |
| 3146 | .num_regs = ARRAY_SIZE(sl_usb_xcvr_diag_ln_regs), |
| 3147 | }; |
| 3148 | |
| 3149 | /* USB PHY PCS common configuration */ |
| 3150 | static struct cdns_reg_pairs usb_phy_pcs_cmn_regs[] = { |
| 3151 | {0x0A0A, PHY_PIPE_USB3_GEN2_PRE_CFG0}, |
| 3152 | {0x1000, PHY_PIPE_USB3_GEN2_POST_CFG0}, |
| 3153 | {0x0010, PHY_PIPE_USB3_GEN2_POST_CFG1} |
| 3154 | }; |
| 3155 | |
| 3156 | static struct cdns_torrent_vals usb_phy_pcs_cmn_vals = { |
| 3157 | .reg_pairs = usb_phy_pcs_cmn_regs, |
| 3158 | .num_regs = ARRAY_SIZE(usb_phy_pcs_cmn_regs), |
| 3159 | }; |
| 3160 | |
| 3161 | /* USB 100 MHz Ref clk, no SSC */ |
Swapnil Jakhade | ed9e07f | 2021-03-04 07:08:16 +0100 | [diff] [blame] | 3162 | static struct cdns_reg_pairs sl_usb_100_no_ssc_cmn_regs[] = { |
| 3163 | {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, |
| 3164 | {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0}, |
| 3165 | {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0}, |
Swapnil Jakhade | 9855d84 | 2020-09-17 09:30:44 +0200 | [diff] [blame] | 3166 | {0x0003, CMN_PLL0_VCOCAL_TCTRL}, |
| 3167 | {0x0003, CMN_PLL1_VCOCAL_TCTRL}, |
| 3168 | {0x8200, CMN_CDIAG_CDB_PWRI_OVRD}, |
| 3169 | {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD} |
| 3170 | }; |
| 3171 | |
Swapnil Jakhade | ed9e07f | 2021-03-04 07:08:16 +0100 | [diff] [blame] | 3172 | static struct cdns_torrent_vals sl_usb_100_no_ssc_cmn_vals = { |
| 3173 | .reg_pairs = sl_usb_100_no_ssc_cmn_regs, |
| 3174 | .num_regs = ARRAY_SIZE(sl_usb_100_no_ssc_cmn_regs), |
| 3175 | }; |
| 3176 | |
| 3177 | static struct cdns_reg_pairs usb_100_no_ssc_cmn_regs[] = { |
| 3178 | {0x8200, CMN_CDIAG_CDB_PWRI_OVRD}, |
| 3179 | {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}, |
| 3180 | {0x007F, CMN_TXPUCAL_TUNE}, |
| 3181 | {0x007F, CMN_TXPDCAL_TUNE} |
| 3182 | }; |
| 3183 | |
Swapnil Jakhade | 9855d84 | 2020-09-17 09:30:44 +0200 | [diff] [blame] | 3184 | static struct cdns_reg_pairs usb_100_no_ssc_tx_ln_regs[] = { |
| 3185 | {0x02FF, TX_PSC_A0}, |
| 3186 | {0x06AF, TX_PSC_A1}, |
| 3187 | {0x06AE, TX_PSC_A2}, |
| 3188 | {0x06AE, TX_PSC_A3}, |
| 3189 | {0x2A82, TX_TXCC_CTRL}, |
| 3190 | {0x0014, TX_TXCC_CPOST_MULT_01}, |
| 3191 | {0x0003, XCVR_DIAG_PSC_OVRD} |
| 3192 | }; |
| 3193 | |
| 3194 | static struct cdns_reg_pairs usb_100_no_ssc_rx_ln_regs[] = { |
| 3195 | {0x0D1D, RX_PSC_A0}, |
| 3196 | {0x0D1D, RX_PSC_A1}, |
| 3197 | {0x0D00, RX_PSC_A2}, |
| 3198 | {0x0500, RX_PSC_A3}, |
| 3199 | {0x0013, RX_SIGDET_HL_FILT_TMR}, |
| 3200 | {0x0000, RX_REE_GCSM1_CTRL}, |
| 3201 | {0x0C02, RX_REE_ATTEN_THR}, |
| 3202 | {0x0330, RX_REE_SMGM_CTRL1}, |
| 3203 | {0x0300, RX_REE_SMGM_CTRL2}, |
| 3204 | {0x0019, RX_REE_TAP1_CLIP}, |
| 3205 | {0x0019, RX_REE_TAP2TON_CLIP}, |
| 3206 | {0x1004, RX_DIAG_SIGDET_TUNE}, |
| 3207 | {0x00F9, RX_DIAG_NQST_CTRL}, |
| 3208 | {0x0C01, RX_DIAG_DFE_AMP_TUNE_2}, |
| 3209 | {0x0002, RX_DIAG_DFE_AMP_TUNE_3}, |
| 3210 | {0x0000, RX_DIAG_PI_CAP}, |
| 3211 | {0x0031, RX_DIAG_PI_RATE}, |
| 3212 | {0x0001, RX_DIAG_ACYA}, |
| 3213 | {0x018C, RX_CDRLF_CNFG}, |
| 3214 | {0x0003, RX_CDRLF_CNFG3} |
| 3215 | }; |
| 3216 | |
| 3217 | static struct cdns_torrent_vals usb_100_no_ssc_cmn_vals = { |
| 3218 | .reg_pairs = usb_100_no_ssc_cmn_regs, |
| 3219 | .num_regs = ARRAY_SIZE(usb_100_no_ssc_cmn_regs), |
| 3220 | }; |
| 3221 | |
| 3222 | static struct cdns_torrent_vals usb_100_no_ssc_tx_ln_vals = { |
| 3223 | .reg_pairs = usb_100_no_ssc_tx_ln_regs, |
| 3224 | .num_regs = ARRAY_SIZE(usb_100_no_ssc_tx_ln_regs), |
| 3225 | }; |
| 3226 | |
| 3227 | static struct cdns_torrent_vals usb_100_no_ssc_rx_ln_vals = { |
| 3228 | .reg_pairs = usb_100_no_ssc_rx_ln_regs, |
| 3229 | .num_regs = ARRAY_SIZE(usb_100_no_ssc_rx_ln_regs), |
| 3230 | }; |
| 3231 | |
| 3232 | /* Single link USB, 100 MHz Ref clk, internal SSC */ |
| 3233 | static struct cdns_reg_pairs sl_usb_100_int_ssc_cmn_regs[] = { |
| 3234 | {0x0004, CMN_PLL0_DSM_DIAG_M0}, |
| 3235 | {0x0004, CMN_PLL1_DSM_DIAG_M0}, |
| 3236 | {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, |
| 3237 | {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, |
| 3238 | {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, |
| 3239 | {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, |
| 3240 | {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, |
| 3241 | {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, |
| 3242 | {0x0064, CMN_PLL0_INTDIV_M0}, |
| 3243 | {0x0064, CMN_PLL1_INTDIV_M0}, |
| 3244 | {0x0002, CMN_PLL0_FRACDIVH_M0}, |
| 3245 | {0x0002, CMN_PLL1_FRACDIVH_M0}, |
| 3246 | {0x0044, CMN_PLL0_HIGH_THR_M0}, |
| 3247 | {0x0044, CMN_PLL1_HIGH_THR_M0}, |
| 3248 | {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, |
| 3249 | {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, |
| 3250 | {0x0001, CMN_PLL0_SS_CTRL1_M0}, |
| 3251 | {0x0001, CMN_PLL1_SS_CTRL1_M0}, |
| 3252 | {0x011B, CMN_PLL0_SS_CTRL2_M0}, |
| 3253 | {0x011B, CMN_PLL1_SS_CTRL2_M0}, |
| 3254 | {0x006E, CMN_PLL0_SS_CTRL3_M0}, |
| 3255 | {0x006E, CMN_PLL1_SS_CTRL3_M0}, |
| 3256 | {0x000E, CMN_PLL0_SS_CTRL4_M0}, |
| 3257 | {0x000E, CMN_PLL1_SS_CTRL4_M0}, |
| 3258 | {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, |
| 3259 | {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, |
| 3260 | {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, |
| 3261 | {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, |
| 3262 | {0x0003, CMN_PLL0_VCOCAL_TCTRL}, |
| 3263 | {0x0003, CMN_PLL1_VCOCAL_TCTRL}, |
| 3264 | {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, |
| 3265 | {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, |
| 3266 | {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, |
| 3267 | {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, |
| 3268 | {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, |
| 3269 | {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}, |
| 3270 | {0x8200, CMN_CDIAG_CDB_PWRI_OVRD}, |
| 3271 | {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD} |
| 3272 | }; |
| 3273 | |
| 3274 | static struct cdns_torrent_vals sl_usb_100_int_ssc_cmn_vals = { |
| 3275 | .reg_pairs = sl_usb_100_int_ssc_cmn_regs, |
| 3276 | .num_regs = ARRAY_SIZE(sl_usb_100_int_ssc_cmn_regs), |
| 3277 | }; |
| 3278 | |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3279 | /* PCIe and SGMII/QSGMII Unique SSC link configuration */ |
| 3280 | static struct cdns_reg_pairs pcie_sgmii_link_cmn_regs[] = { |
Swapnil Jakhade | d66a636 | 2020-09-17 09:30:42 +0200 | [diff] [blame] | 3281 | {0x0003, PHY_PLL_CFG}, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3282 | {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}, |
| 3283 | {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1}, |
| 3284 | {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0} |
| 3285 | }; |
| 3286 | |
| 3287 | static struct cdns_reg_pairs pcie_sgmii_xcvr_diag_ln_regs[] = { |
| 3288 | {0x0000, XCVR_DIAG_HSCLK_SEL}, |
| 3289 | {0x0001, XCVR_DIAG_HSCLK_DIV}, |
| 3290 | {0x0012, XCVR_DIAG_PLLDRC_CTRL} |
| 3291 | }; |
| 3292 | |
| 3293 | static struct cdns_reg_pairs sgmii_pcie_xcvr_diag_ln_regs[] = { |
| 3294 | {0x0011, XCVR_DIAG_HSCLK_SEL}, |
| 3295 | {0x0003, XCVR_DIAG_HSCLK_DIV}, |
| 3296 | {0x009B, XCVR_DIAG_PLLDRC_CTRL} |
| 3297 | }; |
| 3298 | |
| 3299 | static struct cdns_torrent_vals pcie_sgmii_link_cmn_vals = { |
| 3300 | .reg_pairs = pcie_sgmii_link_cmn_regs, |
| 3301 | .num_regs = ARRAY_SIZE(pcie_sgmii_link_cmn_regs), |
| 3302 | }; |
| 3303 | |
| 3304 | static struct cdns_torrent_vals pcie_sgmii_xcvr_diag_ln_vals = { |
| 3305 | .reg_pairs = pcie_sgmii_xcvr_diag_ln_regs, |
| 3306 | .num_regs = ARRAY_SIZE(pcie_sgmii_xcvr_diag_ln_regs), |
| 3307 | }; |
| 3308 | |
| 3309 | static struct cdns_torrent_vals sgmii_pcie_xcvr_diag_ln_vals = { |
| 3310 | .reg_pairs = sgmii_pcie_xcvr_diag_ln_regs, |
| 3311 | .num_regs = ARRAY_SIZE(sgmii_pcie_xcvr_diag_ln_regs), |
| 3312 | }; |
| 3313 | |
| 3314 | /* SGMII 100 MHz Ref clk, no SSC */ |
Swapnil Jakhade | e25c9db | 2021-03-04 07:08:13 +0100 | [diff] [blame] | 3315 | static struct cdns_reg_pairs sl_sgmii_100_no_ssc_cmn_regs[] = { |
| 3316 | {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, |
| 3317 | {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0}, |
| 3318 | {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0}, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3319 | {0x0003, CMN_PLL0_VCOCAL_TCTRL}, |
Swapnil Jakhade | e25c9db | 2021-03-04 07:08:13 +0100 | [diff] [blame] | 3320 | {0x0003, CMN_PLL1_VCOCAL_TCTRL} |
| 3321 | }; |
| 3322 | |
| 3323 | static struct cdns_torrent_vals sl_sgmii_100_no_ssc_cmn_vals = { |
| 3324 | .reg_pairs = sl_sgmii_100_no_ssc_cmn_regs, |
| 3325 | .num_regs = ARRAY_SIZE(sl_sgmii_100_no_ssc_cmn_regs), |
| 3326 | }; |
| 3327 | |
| 3328 | static struct cdns_reg_pairs sgmii_100_no_ssc_cmn_regs[] = { |
| 3329 | {0x007F, CMN_TXPUCAL_TUNE}, |
| 3330 | {0x007F, CMN_TXPDCAL_TUNE} |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3331 | }; |
| 3332 | |
| 3333 | static struct cdns_reg_pairs sgmii_100_no_ssc_tx_ln_regs[] = { |
| 3334 | {0x00F3, TX_PSC_A0}, |
| 3335 | {0x04A2, TX_PSC_A2}, |
| 3336 | {0x04A2, TX_PSC_A3}, |
| 3337 | {0x0000, TX_TXCC_CPOST_MULT_00}, |
| 3338 | {0x00B3, DRV_DIAG_TX_DRV} |
| 3339 | }; |
| 3340 | |
Kishon Vijay Abraham I | 70901a7 | 2021-03-04 07:08:15 +0100 | [diff] [blame] | 3341 | static struct cdns_reg_pairs ti_sgmii_100_no_ssc_tx_ln_regs[] = { |
| 3342 | {0x00F3, TX_PSC_A0}, |
| 3343 | {0x04A2, TX_PSC_A2}, |
| 3344 | {0x04A2, TX_PSC_A3}, |
| 3345 | {0x0000, TX_TXCC_CPOST_MULT_00}, |
| 3346 | {0x00B3, DRV_DIAG_TX_DRV}, |
| 3347 | {0x4000, XCVR_DIAG_RXCLK_CTRL}, |
| 3348 | }; |
| 3349 | |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3350 | static struct cdns_reg_pairs sgmii_100_no_ssc_rx_ln_regs[] = { |
| 3351 | {0x091D, RX_PSC_A0}, |
| 3352 | {0x0900, RX_PSC_A2}, |
| 3353 | {0x0100, RX_PSC_A3}, |
| 3354 | {0x03C7, RX_REE_GCSM1_EQENM_PH1}, |
| 3355 | {0x01C7, RX_REE_GCSM1_EQENM_PH2}, |
| 3356 | {0x0000, RX_DIAG_DFE_CTRL}, |
| 3357 | {0x0019, RX_REE_TAP1_CLIP}, |
| 3358 | {0x0019, RX_REE_TAP2TON_CLIP}, |
| 3359 | {0x0098, RX_DIAG_NQST_CTRL}, |
| 3360 | {0x0C01, RX_DIAG_DFE_AMP_TUNE_2}, |
| 3361 | {0x0000, RX_DIAG_DFE_AMP_TUNE_3}, |
| 3362 | {0x0000, RX_DIAG_PI_CAP}, |
| 3363 | {0x0010, RX_DIAG_PI_RATE}, |
| 3364 | {0x0001, RX_DIAG_ACYA}, |
| 3365 | {0x018C, RX_CDRLF_CNFG}, |
| 3366 | }; |
| 3367 | |
| 3368 | static struct cdns_torrent_vals sgmii_100_no_ssc_cmn_vals = { |
| 3369 | .reg_pairs = sgmii_100_no_ssc_cmn_regs, |
| 3370 | .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_cmn_regs), |
| 3371 | }; |
| 3372 | |
| 3373 | static struct cdns_torrent_vals sgmii_100_no_ssc_tx_ln_vals = { |
| 3374 | .reg_pairs = sgmii_100_no_ssc_tx_ln_regs, |
| 3375 | .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_tx_ln_regs), |
| 3376 | }; |
| 3377 | |
Kishon Vijay Abraham I | 70901a7 | 2021-03-04 07:08:15 +0100 | [diff] [blame] | 3378 | static struct cdns_torrent_vals ti_sgmii_100_no_ssc_tx_ln_vals = { |
| 3379 | .reg_pairs = ti_sgmii_100_no_ssc_tx_ln_regs, |
| 3380 | .num_regs = ARRAY_SIZE(ti_sgmii_100_no_ssc_tx_ln_regs), |
| 3381 | }; |
| 3382 | |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3383 | static struct cdns_torrent_vals sgmii_100_no_ssc_rx_ln_vals = { |
| 3384 | .reg_pairs = sgmii_100_no_ssc_rx_ln_regs, |
| 3385 | .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_rx_ln_regs), |
| 3386 | }; |
| 3387 | |
| 3388 | /* SGMII 100 MHz Ref clk, internal SSC */ |
| 3389 | static struct cdns_reg_pairs sgmii_100_int_ssc_cmn_regs[] = { |
| 3390 | {0x0004, CMN_PLL0_DSM_DIAG_M0}, |
| 3391 | {0x0004, CMN_PLL0_DSM_DIAG_M1}, |
| 3392 | {0x0004, CMN_PLL1_DSM_DIAG_M0}, |
| 3393 | {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, |
| 3394 | {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1}, |
| 3395 | {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, |
| 3396 | {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, |
| 3397 | {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1}, |
| 3398 | {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, |
| 3399 | {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, |
| 3400 | {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1}, |
| 3401 | {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, |
| 3402 | {0x0064, CMN_PLL0_INTDIV_M0}, |
| 3403 | {0x0050, CMN_PLL0_INTDIV_M1}, |
| 3404 | {0x0064, CMN_PLL1_INTDIV_M0}, |
| 3405 | {0x0002, CMN_PLL0_FRACDIVH_M0}, |
| 3406 | {0x0002, CMN_PLL0_FRACDIVH_M1}, |
| 3407 | {0x0002, CMN_PLL1_FRACDIVH_M0}, |
| 3408 | {0x0044, CMN_PLL0_HIGH_THR_M0}, |
| 3409 | {0x0036, CMN_PLL0_HIGH_THR_M1}, |
| 3410 | {0x0044, CMN_PLL1_HIGH_THR_M0}, |
| 3411 | {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, |
| 3412 | {0x0002, CMN_PDIAG_PLL0_CTRL_M1}, |
| 3413 | {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, |
| 3414 | {0x0001, CMN_PLL0_SS_CTRL1_M0}, |
| 3415 | {0x0001, CMN_PLL0_SS_CTRL1_M1}, |
| 3416 | {0x0001, CMN_PLL1_SS_CTRL1_M0}, |
| 3417 | {0x011B, CMN_PLL0_SS_CTRL2_M0}, |
| 3418 | {0x011B, CMN_PLL0_SS_CTRL2_M1}, |
| 3419 | {0x011B, CMN_PLL1_SS_CTRL2_M0}, |
| 3420 | {0x006E, CMN_PLL0_SS_CTRL3_M0}, |
| 3421 | {0x0058, CMN_PLL0_SS_CTRL3_M1}, |
| 3422 | {0x006E, CMN_PLL1_SS_CTRL3_M0}, |
| 3423 | {0x000E, CMN_PLL0_SS_CTRL4_M0}, |
| 3424 | {0x0012, CMN_PLL0_SS_CTRL4_M1}, |
| 3425 | {0x000E, CMN_PLL1_SS_CTRL4_M0}, |
| 3426 | {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, |
| 3427 | {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, |
| 3428 | {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, |
| 3429 | {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3430 | {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, |
| 3431 | {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, |
| 3432 | {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, |
| 3433 | {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, |
| 3434 | {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, |
| 3435 | {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}, |
Swapnil Jakhade | e25c9db | 2021-03-04 07:08:13 +0100 | [diff] [blame] | 3436 | {0x007F, CMN_TXPUCAL_TUNE}, |
| 3437 | {0x007F, CMN_TXPDCAL_TUNE} |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3438 | }; |
| 3439 | |
| 3440 | static struct cdns_torrent_vals sgmii_100_int_ssc_cmn_vals = { |
| 3441 | .reg_pairs = sgmii_100_int_ssc_cmn_regs, |
| 3442 | .num_regs = ARRAY_SIZE(sgmii_100_int_ssc_cmn_regs), |
| 3443 | }; |
| 3444 | |
| 3445 | /* QSGMII 100 MHz Ref clk, no SSC */ |
Swapnil Jakhade | e25c9db | 2021-03-04 07:08:13 +0100 | [diff] [blame] | 3446 | static struct cdns_reg_pairs sl_qsgmii_100_no_ssc_cmn_regs[] = { |
| 3447 | {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, |
| 3448 | {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0}, |
| 3449 | {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0}, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3450 | {0x0003, CMN_PLL0_VCOCAL_TCTRL}, |
| 3451 | {0x0003, CMN_PLL1_VCOCAL_TCTRL} |
| 3452 | }; |
| 3453 | |
Swapnil Jakhade | e25c9db | 2021-03-04 07:08:13 +0100 | [diff] [blame] | 3454 | static struct cdns_torrent_vals sl_qsgmii_100_no_ssc_cmn_vals = { |
| 3455 | .reg_pairs = sl_qsgmii_100_no_ssc_cmn_regs, |
| 3456 | .num_regs = ARRAY_SIZE(sl_qsgmii_100_no_ssc_cmn_regs), |
| 3457 | }; |
| 3458 | |
| 3459 | static struct cdns_reg_pairs qsgmii_100_no_ssc_cmn_regs[] = { |
| 3460 | {0x007F, CMN_TXPUCAL_TUNE}, |
| 3461 | {0x007F, CMN_TXPDCAL_TUNE} |
| 3462 | }; |
| 3463 | |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3464 | static struct cdns_reg_pairs qsgmii_100_no_ssc_tx_ln_regs[] = { |
| 3465 | {0x00F3, TX_PSC_A0}, |
| 3466 | {0x04A2, TX_PSC_A2}, |
| 3467 | {0x04A2, TX_PSC_A3}, |
| 3468 | {0x0000, TX_TXCC_CPOST_MULT_00}, |
Swapnil Jakhade | e25c9db | 2021-03-04 07:08:13 +0100 | [diff] [blame] | 3469 | {0x0011, TX_TXCC_MGNFS_MULT_100}, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3470 | {0x0003, DRV_DIAG_TX_DRV} |
| 3471 | }; |
| 3472 | |
Kishon Vijay Abraham I | 70901a7 | 2021-03-04 07:08:15 +0100 | [diff] [blame] | 3473 | static struct cdns_reg_pairs ti_qsgmii_100_no_ssc_tx_ln_regs[] = { |
| 3474 | {0x00F3, TX_PSC_A0}, |
| 3475 | {0x04A2, TX_PSC_A2}, |
| 3476 | {0x04A2, TX_PSC_A3}, |
| 3477 | {0x0000, TX_TXCC_CPOST_MULT_00}, |
| 3478 | {0x0011, TX_TXCC_MGNFS_MULT_100}, |
| 3479 | {0x0003, DRV_DIAG_TX_DRV}, |
| 3480 | {0x4000, XCVR_DIAG_RXCLK_CTRL}, |
| 3481 | }; |
| 3482 | |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3483 | static struct cdns_reg_pairs qsgmii_100_no_ssc_rx_ln_regs[] = { |
| 3484 | {0x091D, RX_PSC_A0}, |
| 3485 | {0x0900, RX_PSC_A2}, |
| 3486 | {0x0100, RX_PSC_A3}, |
| 3487 | {0x03C7, RX_REE_GCSM1_EQENM_PH1}, |
| 3488 | {0x01C7, RX_REE_GCSM1_EQENM_PH2}, |
| 3489 | {0x0000, RX_DIAG_DFE_CTRL}, |
| 3490 | {0x0019, RX_REE_TAP1_CLIP}, |
| 3491 | {0x0019, RX_REE_TAP2TON_CLIP}, |
| 3492 | {0x0098, RX_DIAG_NQST_CTRL}, |
| 3493 | {0x0C01, RX_DIAG_DFE_AMP_TUNE_2}, |
| 3494 | {0x0000, RX_DIAG_DFE_AMP_TUNE_3}, |
| 3495 | {0x0000, RX_DIAG_PI_CAP}, |
| 3496 | {0x0010, RX_DIAG_PI_RATE}, |
| 3497 | {0x0001, RX_DIAG_ACYA}, |
| 3498 | {0x018C, RX_CDRLF_CNFG}, |
| 3499 | }; |
| 3500 | |
| 3501 | static struct cdns_torrent_vals qsgmii_100_no_ssc_cmn_vals = { |
| 3502 | .reg_pairs = qsgmii_100_no_ssc_cmn_regs, |
| 3503 | .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_cmn_regs), |
| 3504 | }; |
| 3505 | |
| 3506 | static struct cdns_torrent_vals qsgmii_100_no_ssc_tx_ln_vals = { |
| 3507 | .reg_pairs = qsgmii_100_no_ssc_tx_ln_regs, |
| 3508 | .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_tx_ln_regs), |
| 3509 | }; |
| 3510 | |
Kishon Vijay Abraham I | 70901a7 | 2021-03-04 07:08:15 +0100 | [diff] [blame] | 3511 | static struct cdns_torrent_vals ti_qsgmii_100_no_ssc_tx_ln_vals = { |
| 3512 | .reg_pairs = ti_qsgmii_100_no_ssc_tx_ln_regs, |
| 3513 | .num_regs = ARRAY_SIZE(ti_qsgmii_100_no_ssc_tx_ln_regs), |
| 3514 | }; |
| 3515 | |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3516 | static struct cdns_torrent_vals qsgmii_100_no_ssc_rx_ln_vals = { |
| 3517 | .reg_pairs = qsgmii_100_no_ssc_rx_ln_regs, |
| 3518 | .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_rx_ln_regs), |
| 3519 | }; |
| 3520 | |
| 3521 | /* QSGMII 100 MHz Ref clk, internal SSC */ |
| 3522 | static struct cdns_reg_pairs qsgmii_100_int_ssc_cmn_regs[] = { |
| 3523 | {0x0004, CMN_PLL0_DSM_DIAG_M0}, |
| 3524 | {0x0004, CMN_PLL0_DSM_DIAG_M1}, |
| 3525 | {0x0004, CMN_PLL1_DSM_DIAG_M0}, |
| 3526 | {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, |
| 3527 | {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1}, |
| 3528 | {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, |
| 3529 | {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, |
| 3530 | {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1}, |
| 3531 | {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, |
| 3532 | {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, |
| 3533 | {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1}, |
| 3534 | {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, |
| 3535 | {0x0064, CMN_PLL0_INTDIV_M0}, |
| 3536 | {0x0050, CMN_PLL0_INTDIV_M1}, |
| 3537 | {0x0064, CMN_PLL1_INTDIV_M0}, |
| 3538 | {0x0002, CMN_PLL0_FRACDIVH_M0}, |
| 3539 | {0x0002, CMN_PLL0_FRACDIVH_M1}, |
| 3540 | {0x0002, CMN_PLL1_FRACDIVH_M0}, |
| 3541 | {0x0044, CMN_PLL0_HIGH_THR_M0}, |
| 3542 | {0x0036, CMN_PLL0_HIGH_THR_M1}, |
| 3543 | {0x0044, CMN_PLL1_HIGH_THR_M0}, |
| 3544 | {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, |
| 3545 | {0x0002, CMN_PDIAG_PLL0_CTRL_M1}, |
| 3546 | {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, |
| 3547 | {0x0001, CMN_PLL0_SS_CTRL1_M0}, |
| 3548 | {0x0001, CMN_PLL0_SS_CTRL1_M1}, |
| 3549 | {0x0001, CMN_PLL1_SS_CTRL1_M0}, |
| 3550 | {0x011B, CMN_PLL0_SS_CTRL2_M0}, |
| 3551 | {0x011B, CMN_PLL0_SS_CTRL2_M1}, |
| 3552 | {0x011B, CMN_PLL1_SS_CTRL2_M0}, |
| 3553 | {0x006E, CMN_PLL0_SS_CTRL3_M0}, |
| 3554 | {0x0058, CMN_PLL0_SS_CTRL3_M1}, |
| 3555 | {0x006E, CMN_PLL1_SS_CTRL3_M0}, |
| 3556 | {0x000E, CMN_PLL0_SS_CTRL4_M0}, |
| 3557 | {0x0012, CMN_PLL0_SS_CTRL4_M1}, |
| 3558 | {0x000E, CMN_PLL1_SS_CTRL4_M0}, |
| 3559 | {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, |
| 3560 | {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, |
| 3561 | {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, |
| 3562 | {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3563 | {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, |
| 3564 | {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, |
| 3565 | {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, |
| 3566 | {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, |
| 3567 | {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, |
Swapnil Jakhade | e25c9db | 2021-03-04 07:08:13 +0100 | [diff] [blame] | 3568 | {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}, |
| 3569 | {0x007F, CMN_TXPUCAL_TUNE}, |
| 3570 | {0x007F, CMN_TXPDCAL_TUNE} |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3571 | }; |
| 3572 | |
| 3573 | static struct cdns_torrent_vals qsgmii_100_int_ssc_cmn_vals = { |
| 3574 | .reg_pairs = qsgmii_100_int_ssc_cmn_regs, |
| 3575 | .num_regs = ARRAY_SIZE(qsgmii_100_int_ssc_cmn_regs), |
| 3576 | }; |
| 3577 | |
Swapnil Jakhade | 9f33b76 | 2020-09-17 09:30:43 +0200 | [diff] [blame] | 3578 | /* Single SGMII/QSGMII link configuration */ |
| 3579 | static struct cdns_reg_pairs sl_sgmii_link_cmn_regs[] = { |
| 3580 | {0x0000, PHY_PLL_CFG}, |
| 3581 | {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0} |
| 3582 | }; |
| 3583 | |
| 3584 | static struct cdns_reg_pairs sl_sgmii_xcvr_diag_ln_regs[] = { |
| 3585 | {0x0000, XCVR_DIAG_HSCLK_SEL}, |
| 3586 | {0x0003, XCVR_DIAG_HSCLK_DIV}, |
| 3587 | {0x0013, XCVR_DIAG_PLLDRC_CTRL} |
| 3588 | }; |
| 3589 | |
| 3590 | static struct cdns_torrent_vals sl_sgmii_link_cmn_vals = { |
| 3591 | .reg_pairs = sl_sgmii_link_cmn_regs, |
| 3592 | .num_regs = ARRAY_SIZE(sl_sgmii_link_cmn_regs), |
| 3593 | }; |
| 3594 | |
| 3595 | static struct cdns_torrent_vals sl_sgmii_xcvr_diag_ln_vals = { |
| 3596 | .reg_pairs = sl_sgmii_xcvr_diag_ln_regs, |
| 3597 | .num_regs = ARRAY_SIZE(sl_sgmii_xcvr_diag_ln_regs), |
| 3598 | }; |
| 3599 | |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3600 | /* Multi link PCIe, 100 MHz Ref clk, internal SSC */ |
| 3601 | static struct cdns_reg_pairs pcie_100_int_ssc_cmn_regs[] = { |
| 3602 | {0x0004, CMN_PLL0_DSM_DIAG_M0}, |
| 3603 | {0x0004, CMN_PLL0_DSM_DIAG_M1}, |
| 3604 | {0x0004, CMN_PLL1_DSM_DIAG_M0}, |
| 3605 | {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, |
| 3606 | {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1}, |
| 3607 | {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, |
| 3608 | {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, |
| 3609 | {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1}, |
| 3610 | {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, |
| 3611 | {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, |
| 3612 | {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1}, |
| 3613 | {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, |
| 3614 | {0x0064, CMN_PLL0_INTDIV_M0}, |
| 3615 | {0x0050, CMN_PLL0_INTDIV_M1}, |
| 3616 | {0x0064, CMN_PLL1_INTDIV_M0}, |
| 3617 | {0x0002, CMN_PLL0_FRACDIVH_M0}, |
| 3618 | {0x0002, CMN_PLL0_FRACDIVH_M1}, |
| 3619 | {0x0002, CMN_PLL1_FRACDIVH_M0}, |
| 3620 | {0x0044, CMN_PLL0_HIGH_THR_M0}, |
| 3621 | {0x0036, CMN_PLL0_HIGH_THR_M1}, |
| 3622 | {0x0044, CMN_PLL1_HIGH_THR_M0}, |
| 3623 | {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, |
| 3624 | {0x0002, CMN_PDIAG_PLL0_CTRL_M1}, |
| 3625 | {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, |
| 3626 | {0x0001, CMN_PLL0_SS_CTRL1_M0}, |
| 3627 | {0x0001, CMN_PLL0_SS_CTRL1_M1}, |
| 3628 | {0x0001, CMN_PLL1_SS_CTRL1_M0}, |
| 3629 | {0x011B, CMN_PLL0_SS_CTRL2_M0}, |
| 3630 | {0x011B, CMN_PLL0_SS_CTRL2_M1}, |
| 3631 | {0x011B, CMN_PLL1_SS_CTRL2_M0}, |
| 3632 | {0x006E, CMN_PLL0_SS_CTRL3_M0}, |
| 3633 | {0x0058, CMN_PLL0_SS_CTRL3_M1}, |
| 3634 | {0x006E, CMN_PLL1_SS_CTRL3_M0}, |
| 3635 | {0x000E, CMN_PLL0_SS_CTRL4_M0}, |
| 3636 | {0x0012, CMN_PLL0_SS_CTRL4_M1}, |
| 3637 | {0x000E, CMN_PLL1_SS_CTRL4_M0}, |
| 3638 | {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, |
| 3639 | {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, |
| 3640 | {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, |
| 3641 | {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3642 | {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, |
| 3643 | {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, |
| 3644 | {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, |
| 3645 | {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, |
| 3646 | {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, |
| 3647 | {0x0005, CMN_PLL1_LOCK_PLLCNT_THR} |
| 3648 | }; |
| 3649 | |
| 3650 | static struct cdns_torrent_vals pcie_100_int_ssc_cmn_vals = { |
| 3651 | .reg_pairs = pcie_100_int_ssc_cmn_regs, |
| 3652 | .num_regs = ARRAY_SIZE(pcie_100_int_ssc_cmn_regs), |
| 3653 | }; |
| 3654 | |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 3655 | /* Single link PCIe, 100 MHz Ref clk, internal SSC */ |
| 3656 | static struct cdns_reg_pairs sl_pcie_100_int_ssc_cmn_regs[] = { |
| 3657 | {0x0004, CMN_PLL0_DSM_DIAG_M0}, |
| 3658 | {0x0004, CMN_PLL0_DSM_DIAG_M1}, |
| 3659 | {0x0004, CMN_PLL1_DSM_DIAG_M0}, |
| 3660 | {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, |
| 3661 | {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1}, |
| 3662 | {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, |
| 3663 | {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, |
| 3664 | {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1}, |
| 3665 | {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, |
| 3666 | {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, |
| 3667 | {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1}, |
| 3668 | {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, |
| 3669 | {0x0064, CMN_PLL0_INTDIV_M0}, |
| 3670 | {0x0050, CMN_PLL0_INTDIV_M1}, |
| 3671 | {0x0050, CMN_PLL1_INTDIV_M0}, |
| 3672 | {0x0002, CMN_PLL0_FRACDIVH_M0}, |
| 3673 | {0x0002, CMN_PLL0_FRACDIVH_M1}, |
| 3674 | {0x0002, CMN_PLL1_FRACDIVH_M0}, |
| 3675 | {0x0044, CMN_PLL0_HIGH_THR_M0}, |
| 3676 | {0x0036, CMN_PLL0_HIGH_THR_M1}, |
| 3677 | {0x0036, CMN_PLL1_HIGH_THR_M0}, |
| 3678 | {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, |
| 3679 | {0x0002, CMN_PDIAG_PLL0_CTRL_M1}, |
| 3680 | {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, |
| 3681 | {0x0001, CMN_PLL0_SS_CTRL1_M0}, |
| 3682 | {0x0001, CMN_PLL0_SS_CTRL1_M1}, |
| 3683 | {0x0001, CMN_PLL1_SS_CTRL1_M0}, |
| 3684 | {0x011B, CMN_PLL0_SS_CTRL2_M0}, |
| 3685 | {0x011B, CMN_PLL0_SS_CTRL2_M1}, |
| 3686 | {0x011B, CMN_PLL1_SS_CTRL2_M0}, |
| 3687 | {0x006E, CMN_PLL0_SS_CTRL3_M0}, |
| 3688 | {0x0058, CMN_PLL0_SS_CTRL3_M1}, |
| 3689 | {0x0058, CMN_PLL1_SS_CTRL3_M0}, |
| 3690 | {0x000E, CMN_PLL0_SS_CTRL4_M0}, |
| 3691 | {0x0012, CMN_PLL0_SS_CTRL4_M1}, |
| 3692 | {0x0012, CMN_PLL1_SS_CTRL4_M0}, |
| 3693 | {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, |
| 3694 | {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, |
| 3695 | {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, |
| 3696 | {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 3697 | {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, |
| 3698 | {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, |
| 3699 | {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, |
| 3700 | {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, |
| 3701 | {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, |
| 3702 | {0x0005, CMN_PLL1_LOCK_PLLCNT_THR} |
| 3703 | }; |
| 3704 | |
| 3705 | static struct cdns_torrent_vals sl_pcie_100_int_ssc_cmn_vals = { |
| 3706 | .reg_pairs = sl_pcie_100_int_ssc_cmn_regs, |
| 3707 | .num_regs = ARRAY_SIZE(sl_pcie_100_int_ssc_cmn_regs), |
| 3708 | }; |
| 3709 | |
| 3710 | /* PCIe, 100 MHz Ref clk, no SSC & external SSC */ |
| 3711 | static struct cdns_reg_pairs pcie_100_ext_no_ssc_cmn_regs[] = { |
Swapnil Jakhade | e25c9db | 2021-03-04 07:08:13 +0100 | [diff] [blame] | 3712 | {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, |
| 3713 | {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0}, |
| 3714 | {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0} |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 3715 | }; |
| 3716 | |
| 3717 | static struct cdns_reg_pairs pcie_100_ext_no_ssc_rx_ln_regs[] = { |
| 3718 | {0x0019, RX_REE_TAP1_CLIP}, |
| 3719 | {0x0019, RX_REE_TAP2TON_CLIP}, |
| 3720 | {0x0001, RX_DIAG_ACYA} |
| 3721 | }; |
| 3722 | |
| 3723 | static struct cdns_torrent_vals pcie_100_no_ssc_cmn_vals = { |
| 3724 | .reg_pairs = pcie_100_ext_no_ssc_cmn_regs, |
| 3725 | .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_cmn_regs), |
| 3726 | }; |
| 3727 | |
| 3728 | static struct cdns_torrent_vals pcie_100_no_ssc_rx_ln_vals = { |
| 3729 | .reg_pairs = pcie_100_ext_no_ssc_rx_ln_regs, |
| 3730 | .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_rx_ln_regs), |
| 3731 | }; |
| 3732 | |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 3733 | static const struct cdns_torrent_data cdns_map_torrent = { |
| 3734 | .block_offset_shift = 0x2, |
| 3735 | .reg_offset_shift = 0x2, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3736 | .link_cmn_vals = { |
Swapnil Jakhade | da055e5 | 2021-07-28 16:54:50 +0200 | [diff] [blame] | 3737 | [TYPE_DP] = { |
| 3738 | [TYPE_NONE] = { |
| 3739 | [NO_SSC] = &sl_dp_link_cmn_vals, |
| 3740 | }, |
| 3741 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3742 | [TYPE_PCIE] = { |
Swapnil Jakhade | cd9aa94 | 2020-09-17 09:30:41 +0200 | [diff] [blame] | 3743 | [TYPE_NONE] = { |
| 3744 | [NO_SSC] = NULL, |
| 3745 | [EXTERNAL_SSC] = NULL, |
| 3746 | [INTERNAL_SSC] = NULL, |
| 3747 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3748 | [TYPE_SGMII] = { |
| 3749 | [NO_SSC] = &pcie_sgmii_link_cmn_vals, |
| 3750 | [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, |
| 3751 | [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, |
| 3752 | }, |
| 3753 | [TYPE_QSGMII] = { |
| 3754 | [NO_SSC] = &pcie_sgmii_link_cmn_vals, |
| 3755 | [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, |
| 3756 | [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, |
| 3757 | }, |
Swapnil Jakhade | 4acea47 | 2020-09-17 09:30:45 +0200 | [diff] [blame] | 3758 | [TYPE_USB] = { |
| 3759 | [NO_SSC] = &pcie_usb_link_cmn_vals, |
| 3760 | [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals, |
| 3761 | [INTERNAL_SSC] = &pcie_usb_link_cmn_vals, |
| 3762 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3763 | }, |
| 3764 | [TYPE_SGMII] = { |
Swapnil Jakhade | 9f33b76 | 2020-09-17 09:30:43 +0200 | [diff] [blame] | 3765 | [TYPE_NONE] = { |
| 3766 | [NO_SSC] = &sl_sgmii_link_cmn_vals, |
| 3767 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3768 | [TYPE_PCIE] = { |
| 3769 | [NO_SSC] = &pcie_sgmii_link_cmn_vals, |
| 3770 | [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, |
| 3771 | [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, |
| 3772 | }, |
Swapnil Jakhade | 6fd428f | 2020-09-17 09:30:46 +0200 | [diff] [blame] | 3773 | [TYPE_USB] = { |
| 3774 | [NO_SSC] = &usb_sgmii_link_cmn_vals, |
| 3775 | [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals, |
| 3776 | [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals, |
| 3777 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3778 | }, |
| 3779 | [TYPE_QSGMII] = { |
Swapnil Jakhade | 9f33b76 | 2020-09-17 09:30:43 +0200 | [diff] [blame] | 3780 | [TYPE_NONE] = { |
| 3781 | [NO_SSC] = &sl_sgmii_link_cmn_vals, |
| 3782 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3783 | [TYPE_PCIE] = { |
| 3784 | [NO_SSC] = &pcie_sgmii_link_cmn_vals, |
| 3785 | [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, |
| 3786 | [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, |
| 3787 | }, |
Swapnil Jakhade | 6fd428f | 2020-09-17 09:30:46 +0200 | [diff] [blame] | 3788 | [TYPE_USB] = { |
| 3789 | [NO_SSC] = &usb_sgmii_link_cmn_vals, |
| 3790 | [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals, |
| 3791 | [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals, |
| 3792 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3793 | }, |
Swapnil Jakhade | 9855d84 | 2020-09-17 09:30:44 +0200 | [diff] [blame] | 3794 | [TYPE_USB] = { |
| 3795 | [TYPE_NONE] = { |
| 3796 | [NO_SSC] = &sl_usb_link_cmn_vals, |
| 3797 | [EXTERNAL_SSC] = &sl_usb_link_cmn_vals, |
| 3798 | [INTERNAL_SSC] = &sl_usb_link_cmn_vals, |
| 3799 | }, |
Swapnil Jakhade | 4acea47 | 2020-09-17 09:30:45 +0200 | [diff] [blame] | 3800 | [TYPE_PCIE] = { |
| 3801 | [NO_SSC] = &pcie_usb_link_cmn_vals, |
| 3802 | [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals, |
| 3803 | [INTERNAL_SSC] = &pcie_usb_link_cmn_vals, |
| 3804 | }, |
Swapnil Jakhade | 6fd428f | 2020-09-17 09:30:46 +0200 | [diff] [blame] | 3805 | [TYPE_SGMII] = { |
| 3806 | [NO_SSC] = &usb_sgmii_link_cmn_vals, |
| 3807 | [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals, |
| 3808 | [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals, |
| 3809 | }, |
| 3810 | [TYPE_QSGMII] = { |
| 3811 | [NO_SSC] = &usb_sgmii_link_cmn_vals, |
| 3812 | [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals, |
| 3813 | [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals, |
| 3814 | }, |
Swapnil Jakhade | 9855d84 | 2020-09-17 09:30:44 +0200 | [diff] [blame] | 3815 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3816 | }, |
| 3817 | .xcvr_diag_vals = { |
Swapnil Jakhade | da055e5 | 2021-07-28 16:54:50 +0200 | [diff] [blame] | 3818 | [TYPE_DP] = { |
| 3819 | [TYPE_NONE] = { |
| 3820 | [NO_SSC] = &sl_dp_xcvr_diag_ln_vals, |
| 3821 | }, |
| 3822 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3823 | [TYPE_PCIE] = { |
Swapnil Jakhade | cd9aa94 | 2020-09-17 09:30:41 +0200 | [diff] [blame] | 3824 | [TYPE_NONE] = { |
| 3825 | [NO_SSC] = NULL, |
| 3826 | [EXTERNAL_SSC] = NULL, |
| 3827 | [INTERNAL_SSC] = NULL, |
| 3828 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3829 | [TYPE_SGMII] = { |
| 3830 | [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, |
| 3831 | [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, |
| 3832 | [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, |
| 3833 | }, |
| 3834 | [TYPE_QSGMII] = { |
| 3835 | [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, |
| 3836 | [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, |
| 3837 | [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, |
| 3838 | }, |
Swapnil Jakhade | 4acea47 | 2020-09-17 09:30:45 +0200 | [diff] [blame] | 3839 | [TYPE_USB] = { |
| 3840 | [NO_SSC] = &pcie_usb_xcvr_diag_ln_vals, |
| 3841 | [EXTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals, |
| 3842 | [INTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals, |
| 3843 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3844 | }, |
| 3845 | [TYPE_SGMII] = { |
Swapnil Jakhade | 9f33b76 | 2020-09-17 09:30:43 +0200 | [diff] [blame] | 3846 | [TYPE_NONE] = { |
| 3847 | [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals, |
| 3848 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3849 | [TYPE_PCIE] = { |
| 3850 | [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, |
| 3851 | [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, |
| 3852 | [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, |
| 3853 | }, |
Swapnil Jakhade | 6fd428f | 2020-09-17 09:30:46 +0200 | [diff] [blame] | 3854 | [TYPE_USB] = { |
| 3855 | [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals, |
| 3856 | [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals, |
| 3857 | [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals, |
| 3858 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3859 | }, |
| 3860 | [TYPE_QSGMII] = { |
Swapnil Jakhade | 9f33b76 | 2020-09-17 09:30:43 +0200 | [diff] [blame] | 3861 | [TYPE_NONE] = { |
| 3862 | [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals, |
| 3863 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3864 | [TYPE_PCIE] = { |
| 3865 | [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, |
| 3866 | [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, |
| 3867 | [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, |
| 3868 | }, |
Swapnil Jakhade | 6fd428f | 2020-09-17 09:30:46 +0200 | [diff] [blame] | 3869 | [TYPE_USB] = { |
| 3870 | [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals, |
| 3871 | [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals, |
| 3872 | [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals, |
| 3873 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3874 | }, |
Swapnil Jakhade | 9855d84 | 2020-09-17 09:30:44 +0200 | [diff] [blame] | 3875 | [TYPE_USB] = { |
| 3876 | [TYPE_NONE] = { |
| 3877 | [NO_SSC] = &sl_usb_xcvr_diag_ln_vals, |
| 3878 | [EXTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals, |
| 3879 | [INTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals, |
| 3880 | }, |
Swapnil Jakhade | 4acea47 | 2020-09-17 09:30:45 +0200 | [diff] [blame] | 3881 | [TYPE_PCIE] = { |
| 3882 | [NO_SSC] = &usb_pcie_xcvr_diag_ln_vals, |
| 3883 | [EXTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals, |
| 3884 | [INTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals, |
| 3885 | }, |
Swapnil Jakhade | 6fd428f | 2020-09-17 09:30:46 +0200 | [diff] [blame] | 3886 | [TYPE_SGMII] = { |
| 3887 | [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals, |
| 3888 | [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals, |
| 3889 | [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals, |
| 3890 | }, |
| 3891 | [TYPE_QSGMII] = { |
| 3892 | [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals, |
| 3893 | [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals, |
| 3894 | [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals, |
| 3895 | }, |
Swapnil Jakhade | 9855d84 | 2020-09-17 09:30:44 +0200 | [diff] [blame] | 3896 | }, |
| 3897 | }, |
| 3898 | .pcs_cmn_vals = { |
| 3899 | [TYPE_USB] = { |
| 3900 | [TYPE_NONE] = { |
| 3901 | [NO_SSC] = &usb_phy_pcs_cmn_vals, |
| 3902 | [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals, |
| 3903 | [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals, |
| 3904 | }, |
Swapnil Jakhade | 4acea47 | 2020-09-17 09:30:45 +0200 | [diff] [blame] | 3905 | [TYPE_PCIE] = { |
| 3906 | [NO_SSC] = &usb_phy_pcs_cmn_vals, |
| 3907 | [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals, |
| 3908 | [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals, |
| 3909 | }, |
Swapnil Jakhade | 6fd428f | 2020-09-17 09:30:46 +0200 | [diff] [blame] | 3910 | [TYPE_SGMII] = { |
| 3911 | [NO_SSC] = &usb_phy_pcs_cmn_vals, |
| 3912 | [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals, |
| 3913 | [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals, |
| 3914 | }, |
| 3915 | [TYPE_QSGMII] = { |
| 3916 | [NO_SSC] = &usb_phy_pcs_cmn_vals, |
| 3917 | [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals, |
| 3918 | [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals, |
| 3919 | }, |
Swapnil Jakhade | 9855d84 | 2020-09-17 09:30:44 +0200 | [diff] [blame] | 3920 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3921 | }, |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 3922 | .cmn_vals = { |
Swapnil Jakhade | da055e5 | 2021-07-28 16:54:50 +0200 | [diff] [blame] | 3923 | [CLK_19_2_MHZ] = { |
| 3924 | [TYPE_DP] = { |
| 3925 | [TYPE_NONE] = { |
| 3926 | [NO_SSC] = &sl_dp_19_2_no_ssc_cmn_vals, |
| 3927 | }, |
| 3928 | }, |
| 3929 | }, |
| 3930 | [CLK_25_MHZ] = { |
| 3931 | [TYPE_DP] = { |
| 3932 | [TYPE_NONE] = { |
| 3933 | [NO_SSC] = &sl_dp_25_no_ssc_cmn_vals, |
| 3934 | }, |
| 3935 | }, |
| 3936 | }, |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 3937 | [CLK_100_MHZ] = { |
Swapnil Jakhade | 1cc4551 | 2021-07-28 16:54:51 +0200 | [diff] [blame] | 3938 | [TYPE_DP] = { |
| 3939 | [TYPE_NONE] = { |
| 3940 | [NO_SSC] = &sl_dp_100_no_ssc_cmn_vals, |
| 3941 | }, |
| 3942 | }, |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 3943 | [TYPE_PCIE] = { |
| 3944 | [TYPE_NONE] = { |
| 3945 | [NO_SSC] = NULL, |
| 3946 | [EXTERNAL_SSC] = NULL, |
| 3947 | [INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals, |
| 3948 | }, |
| 3949 | [TYPE_SGMII] = { |
| 3950 | [NO_SSC] = &pcie_100_no_ssc_cmn_vals, |
| 3951 | [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals, |
| 3952 | [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals, |
| 3953 | }, |
| 3954 | [TYPE_QSGMII] = { |
| 3955 | [NO_SSC] = &pcie_100_no_ssc_cmn_vals, |
| 3956 | [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals, |
| 3957 | [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals, |
| 3958 | }, |
| 3959 | [TYPE_USB] = { |
| 3960 | [NO_SSC] = &pcie_100_no_ssc_cmn_vals, |
| 3961 | [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals, |
| 3962 | [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals, |
| 3963 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3964 | }, |
| 3965 | [TYPE_SGMII] = { |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 3966 | [TYPE_NONE] = { |
| 3967 | [NO_SSC] = &sl_sgmii_100_no_ssc_cmn_vals, |
| 3968 | }, |
| 3969 | [TYPE_PCIE] = { |
| 3970 | [NO_SSC] = &sgmii_100_no_ssc_cmn_vals, |
| 3971 | [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals, |
| 3972 | [INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals, |
| 3973 | }, |
| 3974 | [TYPE_USB] = { |
| 3975 | [NO_SSC] = &sgmii_100_no_ssc_cmn_vals, |
| 3976 | [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals, |
| 3977 | [INTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals, |
| 3978 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3979 | }, |
| 3980 | [TYPE_QSGMII] = { |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 3981 | [TYPE_NONE] = { |
| 3982 | [NO_SSC] = &sl_qsgmii_100_no_ssc_cmn_vals, |
| 3983 | }, |
| 3984 | [TYPE_PCIE] = { |
| 3985 | [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals, |
| 3986 | [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals, |
| 3987 | [INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals, |
| 3988 | }, |
| 3989 | [TYPE_USB] = { |
| 3990 | [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals, |
| 3991 | [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals, |
| 3992 | [INTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals, |
| 3993 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 3994 | }, |
Swapnil Jakhade | 4acea47 | 2020-09-17 09:30:45 +0200 | [diff] [blame] | 3995 | [TYPE_USB] = { |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 3996 | [TYPE_NONE] = { |
| 3997 | [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals, |
| 3998 | [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals, |
| 3999 | [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals, |
| 4000 | }, |
| 4001 | [TYPE_PCIE] = { |
| 4002 | [NO_SSC] = &usb_100_no_ssc_cmn_vals, |
| 4003 | [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals, |
| 4004 | [INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals, |
| 4005 | }, |
| 4006 | [TYPE_SGMII] = { |
| 4007 | [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals, |
| 4008 | [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals, |
| 4009 | [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals, |
| 4010 | }, |
| 4011 | [TYPE_QSGMII] = { |
| 4012 | [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals, |
| 4013 | [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals, |
| 4014 | [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals, |
| 4015 | }, |
Swapnil Jakhade | 6fd428f | 2020-09-17 09:30:46 +0200 | [diff] [blame] | 4016 | }, |
Swapnil Jakhade | 9855d84 | 2020-09-17 09:30:44 +0200 | [diff] [blame] | 4017 | }, |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 4018 | }, |
| 4019 | .tx_ln_vals = { |
Swapnil Jakhade | da055e5 | 2021-07-28 16:54:50 +0200 | [diff] [blame] | 4020 | [CLK_19_2_MHZ] = { |
| 4021 | [TYPE_DP] = { |
| 4022 | [TYPE_NONE] = { |
| 4023 | [NO_SSC] = &sl_dp_19_2_no_ssc_tx_ln_vals, |
| 4024 | }, |
| 4025 | }, |
| 4026 | }, |
| 4027 | [CLK_25_MHZ] = { |
| 4028 | [TYPE_DP] = { |
| 4029 | [TYPE_NONE] = { |
| 4030 | [NO_SSC] = &sl_dp_25_no_ssc_tx_ln_vals, |
| 4031 | }, |
| 4032 | }, |
| 4033 | }, |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 4034 | [CLK_100_MHZ] = { |
Swapnil Jakhade | 1cc4551 | 2021-07-28 16:54:51 +0200 | [diff] [blame] | 4035 | [TYPE_DP] = { |
| 4036 | [TYPE_NONE] = { |
| 4037 | [NO_SSC] = &sl_dp_100_no_ssc_tx_ln_vals, |
| 4038 | }, |
| 4039 | }, |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 4040 | [TYPE_PCIE] = { |
| 4041 | [TYPE_NONE] = { |
| 4042 | [NO_SSC] = NULL, |
| 4043 | [EXTERNAL_SSC] = NULL, |
| 4044 | [INTERNAL_SSC] = NULL, |
| 4045 | }, |
| 4046 | [TYPE_SGMII] = { |
| 4047 | [NO_SSC] = NULL, |
| 4048 | [EXTERNAL_SSC] = NULL, |
| 4049 | [INTERNAL_SSC] = NULL, |
| 4050 | }, |
| 4051 | [TYPE_QSGMII] = { |
| 4052 | [NO_SSC] = NULL, |
| 4053 | [EXTERNAL_SSC] = NULL, |
| 4054 | [INTERNAL_SSC] = NULL, |
| 4055 | }, |
| 4056 | [TYPE_USB] = { |
| 4057 | [NO_SSC] = NULL, |
| 4058 | [EXTERNAL_SSC] = NULL, |
| 4059 | [INTERNAL_SSC] = NULL, |
| 4060 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 4061 | }, |
| 4062 | [TYPE_SGMII] = { |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 4063 | [TYPE_NONE] = { |
| 4064 | [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals, |
| 4065 | }, |
| 4066 | [TYPE_PCIE] = { |
| 4067 | [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals, |
| 4068 | [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals, |
| 4069 | [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals, |
| 4070 | }, |
| 4071 | [TYPE_USB] = { |
| 4072 | [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals, |
| 4073 | [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals, |
| 4074 | [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals, |
| 4075 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 4076 | }, |
| 4077 | [TYPE_QSGMII] = { |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 4078 | [TYPE_NONE] = { |
| 4079 | [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, |
| 4080 | }, |
| 4081 | [TYPE_PCIE] = { |
| 4082 | [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, |
| 4083 | [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, |
| 4084 | [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, |
| 4085 | }, |
| 4086 | [TYPE_USB] = { |
| 4087 | [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, |
| 4088 | [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, |
| 4089 | [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, |
| 4090 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 4091 | }, |
Swapnil Jakhade | 4acea47 | 2020-09-17 09:30:45 +0200 | [diff] [blame] | 4092 | [TYPE_USB] = { |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 4093 | [TYPE_NONE] = { |
| 4094 | [NO_SSC] = &usb_100_no_ssc_tx_ln_vals, |
| 4095 | [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, |
| 4096 | [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, |
| 4097 | }, |
| 4098 | [TYPE_PCIE] = { |
| 4099 | [NO_SSC] = &usb_100_no_ssc_tx_ln_vals, |
| 4100 | [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, |
| 4101 | [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, |
| 4102 | }, |
| 4103 | [TYPE_SGMII] = { |
| 4104 | [NO_SSC] = &usb_100_no_ssc_tx_ln_vals, |
| 4105 | [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, |
| 4106 | [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, |
| 4107 | }, |
| 4108 | [TYPE_QSGMII] = { |
| 4109 | [NO_SSC] = &usb_100_no_ssc_tx_ln_vals, |
| 4110 | [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, |
| 4111 | [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, |
| 4112 | }, |
Swapnil Jakhade | 6fd428f | 2020-09-17 09:30:46 +0200 | [diff] [blame] | 4113 | }, |
Swapnil Jakhade | 9855d84 | 2020-09-17 09:30:44 +0200 | [diff] [blame] | 4114 | }, |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 4115 | }, |
| 4116 | .rx_ln_vals = { |
Swapnil Jakhade | da055e5 | 2021-07-28 16:54:50 +0200 | [diff] [blame] | 4117 | [CLK_19_2_MHZ] = { |
| 4118 | [TYPE_DP] = { |
| 4119 | [TYPE_NONE] = { |
| 4120 | [NO_SSC] = &sl_dp_19_2_no_ssc_rx_ln_vals, |
| 4121 | }, |
| 4122 | }, |
| 4123 | }, |
| 4124 | [CLK_25_MHZ] = { |
| 4125 | [TYPE_DP] = { |
| 4126 | [TYPE_NONE] = { |
| 4127 | [NO_SSC] = &sl_dp_25_no_ssc_rx_ln_vals, |
| 4128 | }, |
| 4129 | }, |
| 4130 | }, |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 4131 | [CLK_100_MHZ] = { |
Swapnil Jakhade | 1cc4551 | 2021-07-28 16:54:51 +0200 | [diff] [blame] | 4132 | [TYPE_DP] = { |
| 4133 | [TYPE_NONE] = { |
| 4134 | [NO_SSC] = &sl_dp_100_no_ssc_rx_ln_vals, |
| 4135 | }, |
| 4136 | }, |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 4137 | [TYPE_PCIE] = { |
| 4138 | [TYPE_NONE] = { |
| 4139 | [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals, |
| 4140 | [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, |
| 4141 | [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, |
| 4142 | }, |
| 4143 | [TYPE_SGMII] = { |
| 4144 | [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals, |
| 4145 | [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, |
| 4146 | [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, |
| 4147 | }, |
| 4148 | [TYPE_QSGMII] = { |
| 4149 | [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals, |
| 4150 | [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, |
| 4151 | [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, |
| 4152 | }, |
| 4153 | [TYPE_USB] = { |
| 4154 | [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals, |
| 4155 | [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, |
| 4156 | [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, |
| 4157 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 4158 | }, |
| 4159 | [TYPE_SGMII] = { |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 4160 | [TYPE_NONE] = { |
| 4161 | [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals, |
| 4162 | }, |
| 4163 | [TYPE_PCIE] = { |
| 4164 | [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals, |
| 4165 | [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals, |
| 4166 | [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals, |
| 4167 | }, |
| 4168 | [TYPE_USB] = { |
| 4169 | [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals, |
| 4170 | [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals, |
| 4171 | [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals, |
| 4172 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 4173 | }, |
| 4174 | [TYPE_QSGMII] = { |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 4175 | [TYPE_NONE] = { |
| 4176 | [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, |
| 4177 | }, |
| 4178 | [TYPE_PCIE] = { |
| 4179 | [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, |
| 4180 | [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, |
| 4181 | [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, |
| 4182 | }, |
| 4183 | [TYPE_USB] = { |
| 4184 | [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, |
| 4185 | [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, |
| 4186 | [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, |
| 4187 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 4188 | }, |
Swapnil Jakhade | 4acea47 | 2020-09-17 09:30:45 +0200 | [diff] [blame] | 4189 | [TYPE_USB] = { |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 4190 | [TYPE_NONE] = { |
| 4191 | [NO_SSC] = &usb_100_no_ssc_rx_ln_vals, |
| 4192 | [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, |
| 4193 | [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, |
| 4194 | }, |
| 4195 | [TYPE_PCIE] = { |
| 4196 | [NO_SSC] = &usb_100_no_ssc_rx_ln_vals, |
| 4197 | [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, |
| 4198 | [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, |
| 4199 | }, |
| 4200 | [TYPE_SGMII] = { |
| 4201 | [NO_SSC] = &usb_100_no_ssc_rx_ln_vals, |
| 4202 | [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, |
| 4203 | [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, |
| 4204 | }, |
| 4205 | [TYPE_QSGMII] = { |
| 4206 | [NO_SSC] = &usb_100_no_ssc_rx_ln_vals, |
| 4207 | [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, |
| 4208 | [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, |
| 4209 | }, |
Swapnil Jakhade | 6fd428f | 2020-09-17 09:30:46 +0200 | [diff] [blame] | 4210 | }, |
Swapnil Jakhade | 9855d84 | 2020-09-17 09:30:44 +0200 | [diff] [blame] | 4211 | }, |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 4212 | }, |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 4213 | }; |
| 4214 | |
Swapnil Jakhade | 597bf3f | 2020-02-06 07:11:00 +0100 | [diff] [blame] | 4215 | static const struct cdns_torrent_data ti_j721e_map_torrent = { |
| 4216 | .block_offset_shift = 0x0, |
| 4217 | .reg_offset_shift = 0x1, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 4218 | .link_cmn_vals = { |
Swapnil Jakhade | da055e5 | 2021-07-28 16:54:50 +0200 | [diff] [blame] | 4219 | [TYPE_DP] = { |
| 4220 | [TYPE_NONE] = { |
| 4221 | [NO_SSC] = &sl_dp_link_cmn_vals, |
| 4222 | }, |
| 4223 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 4224 | [TYPE_PCIE] = { |
Swapnil Jakhade | cd9aa94 | 2020-09-17 09:30:41 +0200 | [diff] [blame] | 4225 | [TYPE_NONE] = { |
| 4226 | [NO_SSC] = NULL, |
| 4227 | [EXTERNAL_SSC] = NULL, |
| 4228 | [INTERNAL_SSC] = NULL, |
| 4229 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 4230 | [TYPE_SGMII] = { |
| 4231 | [NO_SSC] = &pcie_sgmii_link_cmn_vals, |
| 4232 | [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, |
| 4233 | [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, |
| 4234 | }, |
| 4235 | [TYPE_QSGMII] = { |
| 4236 | [NO_SSC] = &pcie_sgmii_link_cmn_vals, |
| 4237 | [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, |
| 4238 | [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, |
| 4239 | }, |
Swapnil Jakhade | 4acea47 | 2020-09-17 09:30:45 +0200 | [diff] [blame] | 4240 | [TYPE_USB] = { |
| 4241 | [NO_SSC] = &pcie_usb_link_cmn_vals, |
| 4242 | [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals, |
| 4243 | [INTERNAL_SSC] = &pcie_usb_link_cmn_vals, |
| 4244 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 4245 | }, |
| 4246 | [TYPE_SGMII] = { |
Swapnil Jakhade | 9f33b76 | 2020-09-17 09:30:43 +0200 | [diff] [blame] | 4247 | [TYPE_NONE] = { |
| 4248 | [NO_SSC] = &sl_sgmii_link_cmn_vals, |
| 4249 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 4250 | [TYPE_PCIE] = { |
| 4251 | [NO_SSC] = &pcie_sgmii_link_cmn_vals, |
| 4252 | [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, |
| 4253 | [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, |
| 4254 | }, |
Swapnil Jakhade | 6fd428f | 2020-09-17 09:30:46 +0200 | [diff] [blame] | 4255 | [TYPE_USB] = { |
| 4256 | [NO_SSC] = &usb_sgmii_link_cmn_vals, |
| 4257 | [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals, |
| 4258 | [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals, |
| 4259 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 4260 | }, |
| 4261 | [TYPE_QSGMII] = { |
Swapnil Jakhade | 9f33b76 | 2020-09-17 09:30:43 +0200 | [diff] [blame] | 4262 | [TYPE_NONE] = { |
| 4263 | [NO_SSC] = &sl_sgmii_link_cmn_vals, |
| 4264 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 4265 | [TYPE_PCIE] = { |
| 4266 | [NO_SSC] = &pcie_sgmii_link_cmn_vals, |
| 4267 | [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, |
| 4268 | [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, |
| 4269 | }, |
Swapnil Jakhade | 6fd428f | 2020-09-17 09:30:46 +0200 | [diff] [blame] | 4270 | [TYPE_USB] = { |
| 4271 | [NO_SSC] = &usb_sgmii_link_cmn_vals, |
| 4272 | [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals, |
| 4273 | [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals, |
| 4274 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 4275 | }, |
Swapnil Jakhade | 9855d84 | 2020-09-17 09:30:44 +0200 | [diff] [blame] | 4276 | [TYPE_USB] = { |
| 4277 | [TYPE_NONE] = { |
| 4278 | [NO_SSC] = &sl_usb_link_cmn_vals, |
| 4279 | [EXTERNAL_SSC] = &sl_usb_link_cmn_vals, |
| 4280 | [INTERNAL_SSC] = &sl_usb_link_cmn_vals, |
| 4281 | }, |
Swapnil Jakhade | 4acea47 | 2020-09-17 09:30:45 +0200 | [diff] [blame] | 4282 | [TYPE_PCIE] = { |
| 4283 | [NO_SSC] = &pcie_usb_link_cmn_vals, |
| 4284 | [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals, |
| 4285 | [INTERNAL_SSC] = &pcie_usb_link_cmn_vals, |
| 4286 | }, |
Swapnil Jakhade | 6fd428f | 2020-09-17 09:30:46 +0200 | [diff] [blame] | 4287 | [TYPE_SGMII] = { |
| 4288 | [NO_SSC] = &usb_sgmii_link_cmn_vals, |
| 4289 | [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals, |
| 4290 | [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals, |
| 4291 | }, |
| 4292 | [TYPE_QSGMII] = { |
| 4293 | [NO_SSC] = &usb_sgmii_link_cmn_vals, |
| 4294 | [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals, |
| 4295 | [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals, |
| 4296 | }, |
Swapnil Jakhade | 9855d84 | 2020-09-17 09:30:44 +0200 | [diff] [blame] | 4297 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 4298 | }, |
| 4299 | .xcvr_diag_vals = { |
Swapnil Jakhade | da055e5 | 2021-07-28 16:54:50 +0200 | [diff] [blame] | 4300 | [TYPE_DP] = { |
| 4301 | [TYPE_NONE] = { |
| 4302 | [NO_SSC] = &sl_dp_xcvr_diag_ln_vals, |
| 4303 | }, |
| 4304 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 4305 | [TYPE_PCIE] = { |
Swapnil Jakhade | cd9aa94 | 2020-09-17 09:30:41 +0200 | [diff] [blame] | 4306 | [TYPE_NONE] = { |
| 4307 | [NO_SSC] = NULL, |
| 4308 | [EXTERNAL_SSC] = NULL, |
| 4309 | [INTERNAL_SSC] = NULL, |
| 4310 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 4311 | [TYPE_SGMII] = { |
| 4312 | [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, |
| 4313 | [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, |
| 4314 | [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, |
| 4315 | }, |
| 4316 | [TYPE_QSGMII] = { |
| 4317 | [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, |
| 4318 | [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, |
| 4319 | [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, |
| 4320 | }, |
Swapnil Jakhade | 4acea47 | 2020-09-17 09:30:45 +0200 | [diff] [blame] | 4321 | [TYPE_USB] = { |
| 4322 | [NO_SSC] = &pcie_usb_xcvr_diag_ln_vals, |
| 4323 | [EXTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals, |
| 4324 | [INTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals, |
| 4325 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 4326 | }, |
| 4327 | [TYPE_SGMII] = { |
Swapnil Jakhade | 9f33b76 | 2020-09-17 09:30:43 +0200 | [diff] [blame] | 4328 | [TYPE_NONE] = { |
| 4329 | [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals, |
| 4330 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 4331 | [TYPE_PCIE] = { |
| 4332 | [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, |
| 4333 | [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, |
| 4334 | [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, |
| 4335 | }, |
Swapnil Jakhade | 6fd428f | 2020-09-17 09:30:46 +0200 | [diff] [blame] | 4336 | [TYPE_USB] = { |
| 4337 | [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals, |
| 4338 | [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals, |
| 4339 | [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals, |
| 4340 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 4341 | }, |
| 4342 | [TYPE_QSGMII] = { |
Swapnil Jakhade | 9f33b76 | 2020-09-17 09:30:43 +0200 | [diff] [blame] | 4343 | [TYPE_NONE] = { |
| 4344 | [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals, |
| 4345 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 4346 | [TYPE_PCIE] = { |
| 4347 | [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, |
| 4348 | [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, |
| 4349 | [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, |
| 4350 | }, |
Swapnil Jakhade | 6fd428f | 2020-09-17 09:30:46 +0200 | [diff] [blame] | 4351 | [TYPE_USB] = { |
| 4352 | [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals, |
| 4353 | [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals, |
| 4354 | [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals, |
| 4355 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 4356 | }, |
Swapnil Jakhade | 9855d84 | 2020-09-17 09:30:44 +0200 | [diff] [blame] | 4357 | [TYPE_USB] = { |
| 4358 | [TYPE_NONE] = { |
| 4359 | [NO_SSC] = &sl_usb_xcvr_diag_ln_vals, |
| 4360 | [EXTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals, |
| 4361 | [INTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals, |
| 4362 | }, |
Swapnil Jakhade | 4acea47 | 2020-09-17 09:30:45 +0200 | [diff] [blame] | 4363 | [TYPE_PCIE] = { |
| 4364 | [NO_SSC] = &usb_pcie_xcvr_diag_ln_vals, |
| 4365 | [EXTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals, |
| 4366 | [INTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals, |
| 4367 | }, |
Swapnil Jakhade | 6fd428f | 2020-09-17 09:30:46 +0200 | [diff] [blame] | 4368 | [TYPE_SGMII] = { |
| 4369 | [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals, |
| 4370 | [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals, |
| 4371 | [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals, |
| 4372 | }, |
| 4373 | [TYPE_QSGMII] = { |
| 4374 | [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals, |
| 4375 | [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals, |
| 4376 | [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals, |
| 4377 | }, |
Swapnil Jakhade | 9855d84 | 2020-09-17 09:30:44 +0200 | [diff] [blame] | 4378 | }, |
| 4379 | }, |
| 4380 | .pcs_cmn_vals = { |
| 4381 | [TYPE_USB] = { |
| 4382 | [TYPE_NONE] = { |
| 4383 | [NO_SSC] = &usb_phy_pcs_cmn_vals, |
| 4384 | [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals, |
| 4385 | [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals, |
| 4386 | }, |
Swapnil Jakhade | 4acea47 | 2020-09-17 09:30:45 +0200 | [diff] [blame] | 4387 | [TYPE_PCIE] = { |
| 4388 | [NO_SSC] = &usb_phy_pcs_cmn_vals, |
| 4389 | [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals, |
| 4390 | [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals, |
| 4391 | }, |
Swapnil Jakhade | 6fd428f | 2020-09-17 09:30:46 +0200 | [diff] [blame] | 4392 | [TYPE_SGMII] = { |
| 4393 | [NO_SSC] = &usb_phy_pcs_cmn_vals, |
| 4394 | [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals, |
| 4395 | [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals, |
| 4396 | }, |
| 4397 | [TYPE_QSGMII] = { |
| 4398 | [NO_SSC] = &usb_phy_pcs_cmn_vals, |
| 4399 | [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals, |
| 4400 | [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals, |
| 4401 | }, |
Swapnil Jakhade | 9855d84 | 2020-09-17 09:30:44 +0200 | [diff] [blame] | 4402 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 4403 | }, |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 4404 | .cmn_vals = { |
Swapnil Jakhade | da055e5 | 2021-07-28 16:54:50 +0200 | [diff] [blame] | 4405 | [CLK_19_2_MHZ] = { |
| 4406 | [TYPE_DP] = { |
| 4407 | [TYPE_NONE] = { |
| 4408 | [NO_SSC] = &sl_dp_19_2_no_ssc_cmn_vals, |
| 4409 | }, |
| 4410 | }, |
| 4411 | }, |
| 4412 | [CLK_25_MHZ] = { |
| 4413 | [TYPE_DP] = { |
| 4414 | [TYPE_NONE] = { |
| 4415 | [NO_SSC] = &sl_dp_25_no_ssc_cmn_vals, |
| 4416 | }, |
| 4417 | }, |
| 4418 | }, |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 4419 | [CLK_100_MHZ] = { |
Swapnil Jakhade | 1cc4551 | 2021-07-28 16:54:51 +0200 | [diff] [blame] | 4420 | [TYPE_DP] = { |
| 4421 | [TYPE_NONE] = { |
| 4422 | [NO_SSC] = &sl_dp_100_no_ssc_cmn_vals, |
| 4423 | }, |
| 4424 | }, |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 4425 | [TYPE_PCIE] = { |
| 4426 | [TYPE_NONE] = { |
| 4427 | [NO_SSC] = NULL, |
| 4428 | [EXTERNAL_SSC] = NULL, |
| 4429 | [INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals, |
| 4430 | }, |
| 4431 | [TYPE_SGMII] = { |
| 4432 | [NO_SSC] = &pcie_100_no_ssc_cmn_vals, |
| 4433 | [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals, |
| 4434 | [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals, |
| 4435 | }, |
| 4436 | [TYPE_QSGMII] = { |
| 4437 | [NO_SSC] = &pcie_100_no_ssc_cmn_vals, |
| 4438 | [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals, |
| 4439 | [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals, |
| 4440 | }, |
| 4441 | [TYPE_USB] = { |
| 4442 | [NO_SSC] = &pcie_100_no_ssc_cmn_vals, |
| 4443 | [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals, |
| 4444 | [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals, |
| 4445 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 4446 | }, |
| 4447 | [TYPE_SGMII] = { |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 4448 | [TYPE_NONE] = { |
| 4449 | [NO_SSC] = &sl_sgmii_100_no_ssc_cmn_vals, |
| 4450 | }, |
| 4451 | [TYPE_PCIE] = { |
| 4452 | [NO_SSC] = &sgmii_100_no_ssc_cmn_vals, |
| 4453 | [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals, |
| 4454 | [INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals, |
| 4455 | }, |
| 4456 | [TYPE_USB] = { |
| 4457 | [NO_SSC] = &sgmii_100_no_ssc_cmn_vals, |
| 4458 | [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals, |
| 4459 | [INTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals, |
| 4460 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 4461 | }, |
| 4462 | [TYPE_QSGMII] = { |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 4463 | [TYPE_NONE] = { |
| 4464 | [NO_SSC] = &sl_qsgmii_100_no_ssc_cmn_vals, |
| 4465 | }, |
| 4466 | [TYPE_PCIE] = { |
| 4467 | [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals, |
| 4468 | [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals, |
| 4469 | [INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals, |
| 4470 | }, |
| 4471 | [TYPE_USB] = { |
| 4472 | [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals, |
| 4473 | [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals, |
| 4474 | [INTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals, |
| 4475 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 4476 | }, |
Swapnil Jakhade | 4acea47 | 2020-09-17 09:30:45 +0200 | [diff] [blame] | 4477 | [TYPE_USB] = { |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 4478 | [TYPE_NONE] = { |
| 4479 | [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals, |
| 4480 | [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals, |
| 4481 | [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals, |
| 4482 | }, |
| 4483 | [TYPE_PCIE] = { |
| 4484 | [NO_SSC] = &usb_100_no_ssc_cmn_vals, |
| 4485 | [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals, |
| 4486 | [INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals, |
| 4487 | }, |
| 4488 | [TYPE_SGMII] = { |
| 4489 | [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals, |
| 4490 | [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals, |
| 4491 | [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals, |
| 4492 | }, |
| 4493 | [TYPE_QSGMII] = { |
| 4494 | [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals, |
| 4495 | [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals, |
| 4496 | [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals, |
| 4497 | }, |
Swapnil Jakhade | 6fd428f | 2020-09-17 09:30:46 +0200 | [diff] [blame] | 4498 | }, |
Swapnil Jakhade | 9855d84 | 2020-09-17 09:30:44 +0200 | [diff] [blame] | 4499 | }, |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 4500 | }, |
| 4501 | .tx_ln_vals = { |
Swapnil Jakhade | da055e5 | 2021-07-28 16:54:50 +0200 | [diff] [blame] | 4502 | [CLK_19_2_MHZ] = { |
| 4503 | [TYPE_DP] = { |
| 4504 | [TYPE_NONE] = { |
| 4505 | [NO_SSC] = &sl_dp_19_2_no_ssc_tx_ln_vals, |
| 4506 | }, |
| 4507 | }, |
| 4508 | }, |
| 4509 | [CLK_25_MHZ] = { |
| 4510 | [TYPE_DP] = { |
| 4511 | [TYPE_NONE] = { |
| 4512 | [NO_SSC] = &sl_dp_25_no_ssc_tx_ln_vals, |
| 4513 | }, |
| 4514 | }, |
| 4515 | }, |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 4516 | [CLK_100_MHZ] = { |
Swapnil Jakhade | 1cc4551 | 2021-07-28 16:54:51 +0200 | [diff] [blame] | 4517 | [TYPE_DP] = { |
| 4518 | [TYPE_NONE] = { |
| 4519 | [NO_SSC] = &sl_dp_100_no_ssc_tx_ln_vals, |
| 4520 | }, |
| 4521 | }, |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 4522 | [TYPE_PCIE] = { |
| 4523 | [TYPE_NONE] = { |
| 4524 | [NO_SSC] = NULL, |
| 4525 | [EXTERNAL_SSC] = NULL, |
| 4526 | [INTERNAL_SSC] = NULL, |
| 4527 | }, |
| 4528 | [TYPE_SGMII] = { |
| 4529 | [NO_SSC] = NULL, |
| 4530 | [EXTERNAL_SSC] = NULL, |
| 4531 | [INTERNAL_SSC] = NULL, |
| 4532 | }, |
| 4533 | [TYPE_QSGMII] = { |
| 4534 | [NO_SSC] = NULL, |
| 4535 | [EXTERNAL_SSC] = NULL, |
| 4536 | [INTERNAL_SSC] = NULL, |
| 4537 | }, |
| 4538 | [TYPE_USB] = { |
| 4539 | [NO_SSC] = NULL, |
| 4540 | [EXTERNAL_SSC] = NULL, |
| 4541 | [INTERNAL_SSC] = NULL, |
| 4542 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 4543 | }, |
| 4544 | [TYPE_SGMII] = { |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 4545 | [TYPE_NONE] = { |
| 4546 | [NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals, |
| 4547 | }, |
| 4548 | [TYPE_PCIE] = { |
| 4549 | [NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals, |
| 4550 | [EXTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals, |
| 4551 | [INTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals, |
| 4552 | }, |
| 4553 | [TYPE_USB] = { |
| 4554 | [NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals, |
| 4555 | [EXTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals, |
| 4556 | [INTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals, |
| 4557 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 4558 | }, |
| 4559 | [TYPE_QSGMII] = { |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 4560 | [TYPE_NONE] = { |
| 4561 | [NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals, |
| 4562 | }, |
| 4563 | [TYPE_PCIE] = { |
| 4564 | [NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals, |
| 4565 | [EXTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals, |
| 4566 | [INTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals, |
| 4567 | }, |
| 4568 | [TYPE_USB] = { |
| 4569 | [NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals, |
| 4570 | [EXTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals, |
| 4571 | [INTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals, |
| 4572 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 4573 | }, |
Swapnil Jakhade | 4acea47 | 2020-09-17 09:30:45 +0200 | [diff] [blame] | 4574 | [TYPE_USB] = { |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 4575 | [TYPE_NONE] = { |
| 4576 | [NO_SSC] = &usb_100_no_ssc_tx_ln_vals, |
| 4577 | [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, |
| 4578 | [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, |
| 4579 | }, |
| 4580 | [TYPE_PCIE] = { |
| 4581 | [NO_SSC] = &usb_100_no_ssc_tx_ln_vals, |
| 4582 | [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, |
| 4583 | [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, |
| 4584 | }, |
| 4585 | [TYPE_SGMII] = { |
| 4586 | [NO_SSC] = &usb_100_no_ssc_tx_ln_vals, |
| 4587 | [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, |
| 4588 | [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, |
| 4589 | }, |
| 4590 | [TYPE_QSGMII] = { |
| 4591 | [NO_SSC] = &usb_100_no_ssc_tx_ln_vals, |
| 4592 | [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, |
| 4593 | [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, |
| 4594 | }, |
Swapnil Jakhade | 6fd428f | 2020-09-17 09:30:46 +0200 | [diff] [blame] | 4595 | }, |
Swapnil Jakhade | 9855d84 | 2020-09-17 09:30:44 +0200 | [diff] [blame] | 4596 | }, |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 4597 | }, |
| 4598 | .rx_ln_vals = { |
Swapnil Jakhade | da055e5 | 2021-07-28 16:54:50 +0200 | [diff] [blame] | 4599 | [CLK_19_2_MHZ] = { |
| 4600 | [TYPE_DP] = { |
| 4601 | [TYPE_NONE] = { |
| 4602 | [NO_SSC] = &sl_dp_19_2_no_ssc_rx_ln_vals, |
| 4603 | }, |
| 4604 | }, |
| 4605 | }, |
| 4606 | [CLK_25_MHZ] = { |
| 4607 | [TYPE_DP] = { |
| 4608 | [TYPE_NONE] = { |
| 4609 | [NO_SSC] = &sl_dp_25_no_ssc_rx_ln_vals, |
| 4610 | }, |
| 4611 | }, |
| 4612 | }, |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 4613 | [CLK_100_MHZ] = { |
Swapnil Jakhade | 1cc4551 | 2021-07-28 16:54:51 +0200 | [diff] [blame] | 4614 | [TYPE_DP] = { |
| 4615 | [TYPE_NONE] = { |
| 4616 | [NO_SSC] = &sl_dp_100_no_ssc_rx_ln_vals, |
| 4617 | }, |
| 4618 | }, |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 4619 | [TYPE_PCIE] = { |
| 4620 | [TYPE_NONE] = { |
| 4621 | [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals, |
| 4622 | [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, |
| 4623 | [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, |
| 4624 | }, |
| 4625 | [TYPE_SGMII] = { |
| 4626 | [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals, |
| 4627 | [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, |
| 4628 | [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, |
| 4629 | }, |
| 4630 | [TYPE_QSGMII] = { |
| 4631 | [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals, |
| 4632 | [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, |
| 4633 | [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, |
| 4634 | }, |
| 4635 | [TYPE_USB] = { |
| 4636 | [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals, |
| 4637 | [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, |
| 4638 | [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, |
| 4639 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 4640 | }, |
| 4641 | [TYPE_SGMII] = { |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 4642 | [TYPE_NONE] = { |
| 4643 | [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals, |
| 4644 | }, |
| 4645 | [TYPE_PCIE] = { |
| 4646 | [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals, |
| 4647 | [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals, |
| 4648 | [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals, |
| 4649 | }, |
| 4650 | [TYPE_USB] = { |
| 4651 | [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals, |
| 4652 | [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals, |
| 4653 | [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals, |
| 4654 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 4655 | }, |
| 4656 | [TYPE_QSGMII] = { |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 4657 | [TYPE_NONE] = { |
| 4658 | [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, |
| 4659 | }, |
| 4660 | [TYPE_PCIE] = { |
| 4661 | [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, |
| 4662 | [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, |
| 4663 | [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, |
| 4664 | }, |
| 4665 | [TYPE_USB] = { |
| 4666 | [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, |
| 4667 | [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, |
| 4668 | [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, |
| 4669 | }, |
Swapnil Jakhade | 6bcf3cb3 | 2020-09-17 09:30:38 +0200 | [diff] [blame] | 4670 | }, |
Swapnil Jakhade | 4acea47 | 2020-09-17 09:30:45 +0200 | [diff] [blame] | 4671 | [TYPE_USB] = { |
Swapnil Jakhade | 6a2338a | 2021-07-28 16:54:49 +0200 | [diff] [blame] | 4672 | [TYPE_NONE] = { |
| 4673 | [NO_SSC] = &usb_100_no_ssc_rx_ln_vals, |
| 4674 | [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, |
| 4675 | [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, |
| 4676 | }, |
| 4677 | [TYPE_PCIE] = { |
| 4678 | [NO_SSC] = &usb_100_no_ssc_rx_ln_vals, |
| 4679 | [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, |
| 4680 | [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, |
| 4681 | }, |
| 4682 | [TYPE_SGMII] = { |
| 4683 | [NO_SSC] = &usb_100_no_ssc_rx_ln_vals, |
| 4684 | [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, |
| 4685 | [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, |
| 4686 | }, |
| 4687 | [TYPE_QSGMII] = { |
| 4688 | [NO_SSC] = &usb_100_no_ssc_rx_ln_vals, |
| 4689 | [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, |
| 4690 | [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, |
| 4691 | }, |
Swapnil Jakhade | 6fd428f | 2020-09-17 09:30:46 +0200 | [diff] [blame] | 4692 | }, |
Swapnil Jakhade | 9855d84 | 2020-09-17 09:30:44 +0200 | [diff] [blame] | 4693 | }, |
Swapnil Jakhade | b54b47b | 2020-09-17 09:30:34 +0200 | [diff] [blame] | 4694 | }, |
Swapnil Jakhade | 597bf3f | 2020-02-06 07:11:00 +0100 | [diff] [blame] | 4695 | }; |
| 4696 | |
Swapnil Jakhade | 92e9ccc | 2020-02-06 07:10:52 +0100 | [diff] [blame] | 4697 | static const struct of_device_id cdns_torrent_phy_of_match[] = { |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 4698 | { |
Swapnil Jakhade | 69d114a | 2020-02-06 07:10:58 +0100 | [diff] [blame] | 4699 | .compatible = "cdns,torrent-phy", |
| 4700 | .data = &cdns_map_torrent, |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 4701 | }, |
Swapnil Jakhade | 597bf3f | 2020-02-06 07:11:00 +0100 | [diff] [blame] | 4702 | { |
| 4703 | .compatible = "ti,j721e-serdes-10g", |
| 4704 | .data = &ti_j721e_map_torrent, |
| 4705 | }, |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 4706 | {} |
| 4707 | }; |
Swapnil Jakhade | 92e9ccc | 2020-02-06 07:10:52 +0100 | [diff] [blame] | 4708 | MODULE_DEVICE_TABLE(of, cdns_torrent_phy_of_match); |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 4709 | |
Swapnil Jakhade | 92e9ccc | 2020-02-06 07:10:52 +0100 | [diff] [blame] | 4710 | static struct platform_driver cdns_torrent_phy_driver = { |
| 4711 | .probe = cdns_torrent_phy_probe, |
Swapnil Jakhade | afa4ba0 | 2020-02-06 07:11:01 +0100 | [diff] [blame] | 4712 | .remove = cdns_torrent_phy_remove, |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 4713 | .driver = { |
Swapnil Jakhade | 92e9ccc | 2020-02-06 07:10:52 +0100 | [diff] [blame] | 4714 | .name = "cdns-torrent-phy", |
| 4715 | .of_match_table = cdns_torrent_phy_of_match, |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 4716 | } |
| 4717 | }; |
Swapnil Jakhade | 92e9ccc | 2020-02-06 07:10:52 +0100 | [diff] [blame] | 4718 | module_platform_driver(cdns_torrent_phy_driver); |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 4719 | |
| 4720 | MODULE_AUTHOR("Cadence Design Systems, Inc."); |
Swapnil Jakhade | 92e9ccc | 2020-02-06 07:10:52 +0100 | [diff] [blame] | 4721 | MODULE_DESCRIPTION("Cadence Torrent PHY driver"); |
Scott Telford | c8b427e | 2018-08-09 11:30:30 +0100 | [diff] [blame] | 4722 | MODULE_LICENSE("GPL v2"); |