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Thomas Gleixner84a14ae2019-05-28 09:57:07 -07001// SPDX-License-Identifier: GPL-2.0-only
Russell King5e742ad2005-08-18 10:08:15 +01002/*
3 * linux/drivers/mfd/mcp-sa11x0.c
4 *
5 * Copyright (C) 2001-2005 Russell King
6 *
Russell King5e742ad2005-08-18 10:08:15 +01007 * SA11x0 MCP (Multimedia Communications Port) driver.
8 *
9 * MCP read/write timeouts from Jordi Colomer, rehacked by rmk.
10 */
11#include <linux/module.h>
Russell King45c7f752012-01-20 23:09:42 +000012#include <linux/io.h>
Russell King5e742ad2005-08-18 10:08:15 +010013#include <linux/errno.h>
14#include <linux/kernel.h>
15#include <linux/delay.h>
16#include <linux/spinlock.h>
Russell Kingd052d1b2005-10-29 19:07:23 +010017#include <linux/platform_device.h>
Russell King2796e392012-01-21 09:34:30 +000018#include <linux/pm.h>
Thomas Kunzec8602ed2009-02-10 14:54:57 +010019#include <linux/mfd/mcp.h>
Russell King5e742ad2005-08-18 10:08:15 +010020
Russell Kinga09e64f2008-08-05 16:14:15 +010021#include <mach/hardware.h>
Russell King5e742ad2005-08-18 10:08:15 +010022#include <asm/mach-types.h>
Arnd Bergmanna1fd8442012-08-24 15:17:38 +020023#include <linux/platform_data/mfd-mcp-sa11x0.h>
Russell King5e742ad2005-08-18 10:08:15 +010024
Russell Kingc4592ce2012-01-20 22:30:15 +000025#define DRIVER_NAME "sa11x0-mcp"
Russell King5e742ad2005-08-18 10:08:15 +010026
27struct mcp_sa11x0 {
Russell King45c7f752012-01-20 23:09:42 +000028 void __iomem *base0;
29 void __iomem *base1;
30 u32 mccr0;
31 u32 mccr1;
Russell King5e742ad2005-08-18 10:08:15 +010032};
33
Russell King45c7f752012-01-20 23:09:42 +000034/* Register offsets */
35#define MCCR0(m) ((m)->base0 + 0x00)
36#define MCDR0(m) ((m)->base0 + 0x08)
37#define MCDR1(m) ((m)->base0 + 0x0c)
38#define MCDR2(m) ((m)->base0 + 0x10)
39#define MCSR(m) ((m)->base0 + 0x18)
40#define MCCR1(m) ((m)->base1 + 0x00)
41
Russell King5e742ad2005-08-18 10:08:15 +010042#define priv(mcp) ((struct mcp_sa11x0 *)mcp_priv(mcp))
43
44static void
45mcp_sa11x0_set_telecom_divisor(struct mcp *mcp, unsigned int divisor)
46{
Russell King45c7f752012-01-20 23:09:42 +000047 struct mcp_sa11x0 *m = priv(mcp);
Russell King5e742ad2005-08-18 10:08:15 +010048
49 divisor /= 32;
50
Russell King45c7f752012-01-20 23:09:42 +000051 m->mccr0 &= ~0x00007f00;
52 m->mccr0 |= divisor << 8;
53 writel_relaxed(m->mccr0, MCCR0(m));
Russell King5e742ad2005-08-18 10:08:15 +010054}
55
56static void
57mcp_sa11x0_set_audio_divisor(struct mcp *mcp, unsigned int divisor)
58{
Russell King45c7f752012-01-20 23:09:42 +000059 struct mcp_sa11x0 *m = priv(mcp);
Russell King5e742ad2005-08-18 10:08:15 +010060
61 divisor /= 32;
62
Russell King45c7f752012-01-20 23:09:42 +000063 m->mccr0 &= ~0x0000007f;
64 m->mccr0 |= divisor;
65 writel_relaxed(m->mccr0, MCCR0(m));
Russell King5e742ad2005-08-18 10:08:15 +010066}
67
68/*
69 * Write data to the device. The bit should be set after 3 subframe
70 * times (each frame is 64 clocks). We wait a maximum of 6 subframes.
71 * We really should try doing something more productive while we
72 * wait.
73 */
74static void
75mcp_sa11x0_write(struct mcp *mcp, unsigned int reg, unsigned int val)
76{
Russell King45c7f752012-01-20 23:09:42 +000077 struct mcp_sa11x0 *m = priv(mcp);
Russell King5e742ad2005-08-18 10:08:15 +010078 int ret = -ETIME;
79 int i;
80
Russell King45c7f752012-01-20 23:09:42 +000081 writel_relaxed(reg << 17 | MCDR2_Wr | (val & 0xffff), MCDR2(m));
Russell King5e742ad2005-08-18 10:08:15 +010082
83 for (i = 0; i < 2; i++) {
84 udelay(mcp->rw_timeout);
Russell King45c7f752012-01-20 23:09:42 +000085 if (readl_relaxed(MCSR(m)) & MCSR_CWC) {
Russell King5e742ad2005-08-18 10:08:15 +010086 ret = 0;
87 break;
88 }
89 }
90
91 if (ret < 0)
92 printk(KERN_WARNING "mcp: write timed out\n");
93}
94
95/*
96 * Read data from the device. The bit should be set after 3 subframe
97 * times (each frame is 64 clocks). We wait a maximum of 6 subframes.
98 * We really should try doing something more productive while we
99 * wait.
100 */
101static unsigned int
102mcp_sa11x0_read(struct mcp *mcp, unsigned int reg)
103{
Russell King45c7f752012-01-20 23:09:42 +0000104 struct mcp_sa11x0 *m = priv(mcp);
Russell King5e742ad2005-08-18 10:08:15 +0100105 int ret = -ETIME;
106 int i;
107
Russell King45c7f752012-01-20 23:09:42 +0000108 writel_relaxed(reg << 17 | MCDR2_Rd, MCDR2(m));
Russell King5e742ad2005-08-18 10:08:15 +0100109
110 for (i = 0; i < 2; i++) {
111 udelay(mcp->rw_timeout);
Russell King45c7f752012-01-20 23:09:42 +0000112 if (readl_relaxed(MCSR(m)) & MCSR_CRC) {
113 ret = readl_relaxed(MCDR2(m)) & 0xffff;
Russell King5e742ad2005-08-18 10:08:15 +0100114 break;
115 }
116 }
117
118 if (ret < 0)
119 printk(KERN_WARNING "mcp: read timed out\n");
120
121 return ret;
122}
123
124static void mcp_sa11x0_enable(struct mcp *mcp)
125{
Russell King45c7f752012-01-20 23:09:42 +0000126 struct mcp_sa11x0 *m = priv(mcp);
127
128 writel(-1, MCSR(m));
129 m->mccr0 |= MCCR0_MCE;
130 writel_relaxed(m->mccr0, MCCR0(m));
Russell King5e742ad2005-08-18 10:08:15 +0100131}
132
133static void mcp_sa11x0_disable(struct mcp *mcp)
134{
Russell King45c7f752012-01-20 23:09:42 +0000135 struct mcp_sa11x0 *m = priv(mcp);
136
137 m->mccr0 &= ~MCCR0_MCE;
138 writel_relaxed(m->mccr0, MCCR0(m));
Russell King5e742ad2005-08-18 10:08:15 +0100139}
140
141/*
142 * Our methods.
143 */
144static struct mcp_ops mcp_sa11x0 = {
145 .set_telecom_divisor = mcp_sa11x0_set_telecom_divisor,
146 .set_audio_divisor = mcp_sa11x0_set_audio_divisor,
147 .reg_write = mcp_sa11x0_write,
148 .reg_read = mcp_sa11x0_read,
149 .enable = mcp_sa11x0_enable,
150 .disable = mcp_sa11x0_disable,
151};
152
Russell King45c7f752012-01-20 23:09:42 +0000153static int mcp_sa11x0_probe(struct platform_device *dev)
Russell King5e742ad2005-08-18 10:08:15 +0100154{
Jingoo Han334a41ce2013-07-30 17:10:05 +0900155 struct mcp_plat_data *data = dev_get_platdata(&dev->dev);
Russell King45c7f752012-01-20 23:09:42 +0000156 struct resource *mem0, *mem1;
157 struct mcp_sa11x0 *m;
Russell King5e742ad2005-08-18 10:08:15 +0100158 struct mcp *mcp;
159 int ret;
160
Russell King323cdfc2005-08-18 10:10:46 +0100161 if (!data)
Russell King5e742ad2005-08-18 10:08:15 +0100162 return -ENODEV;
163
Russell King45c7f752012-01-20 23:09:42 +0000164 mem0 = platform_get_resource(dev, IORESOURCE_MEM, 0);
165 mem1 = platform_get_resource(dev, IORESOURCE_MEM, 1);
166 if (!mem0 || !mem1)
167 return -ENXIO;
Russell King5e742ad2005-08-18 10:08:15 +0100168
Russell King45c7f752012-01-20 23:09:42 +0000169 if (!request_mem_region(mem0->start, resource_size(mem0),
170 DRIVER_NAME)) {
171 ret = -EBUSY;
172 goto err_mem0;
173 }
174
175 if (!request_mem_region(mem1->start, resource_size(mem1),
176 DRIVER_NAME)) {
177 ret = -EBUSY;
178 goto err_mem1;
179 }
180
181 mcp = mcp_host_alloc(&dev->dev, sizeof(struct mcp_sa11x0));
Russell King5e742ad2005-08-18 10:08:15 +0100182 if (!mcp) {
183 ret = -ENOMEM;
Russell King45c7f752012-01-20 23:09:42 +0000184 goto err_alloc;
Russell King5e742ad2005-08-18 10:08:15 +0100185 }
186
187 mcp->owner = THIS_MODULE;
188 mcp->ops = &mcp_sa11x0;
Russell King323cdfc2005-08-18 10:10:46 +0100189 mcp->sclk_rate = data->sclk_rate;
Russell King5e742ad2005-08-18 10:08:15 +0100190
Russell King45c7f752012-01-20 23:09:42 +0000191 m = priv(mcp);
192 m->mccr0 = data->mccr0 | 0x7f7f;
193 m->mccr1 = data->mccr1;
194
195 m->base0 = ioremap(mem0->start, resource_size(mem0));
196 m->base1 = ioremap(mem1->start, resource_size(mem1));
197 if (!m->base0 || !m->base1) {
198 ret = -ENOMEM;
199 goto err_ioremap;
200 }
201
202 platform_set_drvdata(dev, mcp);
Russell King5e742ad2005-08-18 10:08:15 +0100203
Russell King216f63c2012-01-20 17:37:21 +0000204 /*
Russell King323cdfc2005-08-18 10:10:46 +0100205 * Initialise device. Note that we initially
206 * set the sampling rate to minimum.
207 */
Russell King45c7f752012-01-20 23:09:42 +0000208 writel_relaxed(-1, MCSR(m));
209 writel_relaxed(m->mccr1, MCCR1(m));
210 writel_relaxed(m->mccr0, MCCR0(m));
Russell King5e742ad2005-08-18 10:08:15 +0100211
212 /*
213 * Calculate the read/write timeout (us) from the bit clock
214 * rate. This is the period for 3 64-bit frames. Always
215 * round this time up.
216 */
Zheng Yongjunab099cc2020-12-22 21:33:26 +0800217 mcp->rw_timeout = DIV_ROUND_UP(64 * 3 * 1000000, mcp->sclk_rate);
Russell King5e742ad2005-08-18 10:08:15 +0100218
Russell Kingabe06082012-01-20 22:13:52 +0000219 ret = mcp_host_add(mcp, data->codec_pdata);
Russell King5e742ad2005-08-18 10:08:15 +0100220 if (ret == 0)
Russell King45c7f752012-01-20 23:09:42 +0000221 return 0;
Russell King5e742ad2005-08-18 10:08:15 +0100222
Russell King45c7f752012-01-20 23:09:42 +0000223 err_ioremap:
224 iounmap(m->base1);
225 iounmap(m->base0);
Russell King30816ac2012-01-20 22:51:07 +0000226 mcp_host_free(mcp);
Russell King45c7f752012-01-20 23:09:42 +0000227 err_alloc:
228 release_mem_region(mem1->start, resource_size(mem1));
229 err_mem1:
230 release_mem_region(mem0->start, resource_size(mem0));
231 err_mem0:
Russell King5e742ad2005-08-18 10:08:15 +0100232 return ret;
233}
234
Russell King216f63c2012-01-20 17:37:21 +0000235static int mcp_sa11x0_remove(struct platform_device *dev)
Russell King5e742ad2005-08-18 10:08:15 +0100236{
Russell King216f63c2012-01-20 17:37:21 +0000237 struct mcp *mcp = platform_get_drvdata(dev);
Russell King45c7f752012-01-20 23:09:42 +0000238 struct mcp_sa11x0 *m = priv(mcp);
239 struct resource *mem0, *mem1;
240
Russell Kinga4b54ac2012-01-21 18:26:17 +0000241 if (m->mccr0 & MCCR0_MCE)
242 dev_warn(&dev->dev,
243 "device left active (missing disable call?)\n");
244
Russell King45c7f752012-01-20 23:09:42 +0000245 mem0 = platform_get_resource(dev, IORESOURCE_MEM, 0);
246 mem1 = platform_get_resource(dev, IORESOURCE_MEM, 1);
Russell King5e742ad2005-08-18 10:08:15 +0100247
Russell King30816ac2012-01-20 22:51:07 +0000248 mcp_host_del(mcp);
Russell King45c7f752012-01-20 23:09:42 +0000249 iounmap(m->base1);
250 iounmap(m->base0);
Russell King30816ac2012-01-20 22:51:07 +0000251 mcp_host_free(mcp);
Russell King45c7f752012-01-20 23:09:42 +0000252 release_mem_region(mem1->start, resource_size(mem1));
253 release_mem_region(mem0->start, resource_size(mem0));
Russell King5e742ad2005-08-18 10:08:15 +0100254
255 return 0;
256}
257
Russell King2796e392012-01-21 09:34:30 +0000258#ifdef CONFIG_PM_SLEEP
259static int mcp_sa11x0_suspend(struct device *dev)
Russell King5e742ad2005-08-18 10:08:15 +0100260{
Russell King2796e392012-01-21 09:34:30 +0000261 struct mcp_sa11x0 *m = priv(dev_get_drvdata(dev));
Russell King5e742ad2005-08-18 10:08:15 +0100262
Russell Kinga4b54ac2012-01-21 18:26:17 +0000263 if (m->mccr0 & MCCR0_MCE)
264 dev_warn(dev, "device left active (missing disable call?)\n");
265
Russell King45c7f752012-01-20 23:09:42 +0000266 writel(m->mccr0 & ~MCCR0_MCE, MCCR0(m));
Russell King9480e302005-10-28 09:52:56 -0700267
Russell King5e742ad2005-08-18 10:08:15 +0100268 return 0;
269}
270
Russell King2796e392012-01-21 09:34:30 +0000271static int mcp_sa11x0_resume(struct device *dev)
Russell King5e742ad2005-08-18 10:08:15 +0100272{
Russell King2796e392012-01-21 09:34:30 +0000273 struct mcp_sa11x0 *m = priv(dev_get_drvdata(dev));
Russell King5e742ad2005-08-18 10:08:15 +0100274
Russell King45c7f752012-01-20 23:09:42 +0000275 writel_relaxed(m->mccr1, MCCR1(m));
276 writel_relaxed(m->mccr0, MCCR0(m));
Russell King9480e302005-10-28 09:52:56 -0700277
Russell King5e742ad2005-08-18 10:08:15 +0100278 return 0;
279}
Russell King2796e392012-01-21 09:34:30 +0000280#endif
281
282static const struct dev_pm_ops mcp_sa11x0_pm_ops = {
Russell Kinga6aecae2012-01-21 18:03:00 +0000283#ifdef CONFIG_PM_SLEEP
284 .suspend = mcp_sa11x0_suspend,
285 .freeze = mcp_sa11x0_suspend,
286 .poweroff = mcp_sa11x0_suspend,
287 .resume_noirq = mcp_sa11x0_resume,
288 .thaw_noirq = mcp_sa11x0_resume,
289 .restore_noirq = mcp_sa11x0_resume,
290#endif
Russell King2796e392012-01-21 09:34:30 +0000291};
Russell King5e742ad2005-08-18 10:08:15 +0100292
Russell King3ae5eae2005-11-09 22:32:44 +0000293static struct platform_driver mcp_sa11x0_driver = {
Russell King5e742ad2005-08-18 10:08:15 +0100294 .probe = mcp_sa11x0_probe,
295 .remove = mcp_sa11x0_remove,
Russell King3ae5eae2005-11-09 22:32:44 +0000296 .driver = {
Russell Kingc4592ce2012-01-20 22:30:15 +0000297 .name = DRIVER_NAME,
Russell King2796e392012-01-21 09:34:30 +0000298 .pm = &mcp_sa11x0_pm_ops,
Russell King3ae5eae2005-11-09 22:32:44 +0000299 },
Russell King5e742ad2005-08-18 10:08:15 +0100300};
301
302/*
303 * This needs re-working
304 */
Mark Brown65349d62011-11-23 22:58:34 +0000305module_platform_driver(mcp_sa11x0_driver);
Russell King5e742ad2005-08-18 10:08:15 +0100306
Russell Kingc4592ce2012-01-20 22:30:15 +0000307MODULE_ALIAS("platform:" DRIVER_NAME);
Russell King5e742ad2005-08-18 10:08:15 +0100308MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
309MODULE_DESCRIPTION("SA11x0 multimedia communications port driver");
310MODULE_LICENSE("GPL");