blob: 573ad8b86804ed28d42f4b1c40aad2a5bc5d984f [file] [log] [blame]
Dave Jiangbfe1d562020-01-21 16:43:59 -07001// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
3#include <linux/init.h>
4#include <linux/kernel.h>
5#include <linux/module.h>
6#include <linux/pci.h>
7#include <linux/io-64-nonatomic-lo-hi.h>
Dave Jiang8f47d1a2020-01-21 16:44:23 -07008#include <linux/dmaengine.h>
Dave Jiang4548a6a2020-06-26 11:12:56 -07009#include <linux/irq.h>
10#include <linux/msi.h>
Dave Jiangbfe1d562020-01-21 16:43:59 -070011#include <uapi/linux/idxd.h>
Dave Jiang8f47d1a2020-01-21 16:44:23 -070012#include "../dmaengine.h"
Dave Jiangbfe1d562020-01-21 16:43:59 -070013#include "idxd.h"
14#include "registers.h"
15
Dave Jiang0d5c10b2020-06-26 11:11:18 -070016static void idxd_cmd_exec(struct idxd_device *idxd, int cmd_code, u32 operand,
17 u32 *status);
Dave Jiang0dcfe412021-06-04 17:06:21 -070018static void idxd_device_wqs_clear_state(struct idxd_device *idxd);
19static void idxd_wq_disable_cleanup(struct idxd_wq *wq);
Dave Jiangbfe1d562020-01-21 16:43:59 -070020
21/* Interrupt control bits */
Dave Jiangbfe1d562020-01-21 16:43:59 -070022void idxd_unmask_error_interrupts(struct idxd_device *idxd)
23{
24 union genctrl_reg genctrl;
25
26 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET);
27 genctrl.softerr_int_en = 1;
Dave Jiang5b0c68c2021-04-20 11:46:51 -070028 genctrl.halt_int_en = 1;
Dave Jiangbfe1d562020-01-21 16:43:59 -070029 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET);
30}
31
32void idxd_mask_error_interrupts(struct idxd_device *idxd)
33{
34 union genctrl_reg genctrl;
35
36 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET);
37 genctrl.softerr_int_en = 0;
Dave Jiang5b0c68c2021-04-20 11:46:51 -070038 genctrl.halt_int_en = 0;
Dave Jiangbfe1d562020-01-21 16:43:59 -070039 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET);
40}
41
42static void free_hw_descs(struct idxd_wq *wq)
43{
44 int i;
45
46 for (i = 0; i < wq->num_descs; i++)
47 kfree(wq->hw_descs[i]);
48
49 kfree(wq->hw_descs);
50}
51
52static int alloc_hw_descs(struct idxd_wq *wq, int num)
53{
54 struct device *dev = &wq->idxd->pdev->dev;
55 int i;
56 int node = dev_to_node(dev);
57
58 wq->hw_descs = kcalloc_node(num, sizeof(struct dsa_hw_desc *),
59 GFP_KERNEL, node);
60 if (!wq->hw_descs)
61 return -ENOMEM;
62
63 for (i = 0; i < num; i++) {
64 wq->hw_descs[i] = kzalloc_node(sizeof(*wq->hw_descs[i]),
65 GFP_KERNEL, node);
66 if (!wq->hw_descs[i]) {
67 free_hw_descs(wq);
68 return -ENOMEM;
69 }
70 }
71
72 return 0;
73}
74
75static void free_descs(struct idxd_wq *wq)
76{
77 int i;
78
79 for (i = 0; i < wq->num_descs; i++)
80 kfree(wq->descs[i]);
81
82 kfree(wq->descs);
83}
84
85static int alloc_descs(struct idxd_wq *wq, int num)
86{
87 struct device *dev = &wq->idxd->pdev->dev;
88 int i;
89 int node = dev_to_node(dev);
90
91 wq->descs = kcalloc_node(num, sizeof(struct idxd_desc *),
92 GFP_KERNEL, node);
93 if (!wq->descs)
94 return -ENOMEM;
95
96 for (i = 0; i < num; i++) {
97 wq->descs[i] = kzalloc_node(sizeof(*wq->descs[i]),
98 GFP_KERNEL, node);
99 if (!wq->descs[i]) {
100 free_descs(wq);
101 return -ENOMEM;
102 }
103 }
104
105 return 0;
106}
107
108/* WQ control bits */
109int idxd_wq_alloc_resources(struct idxd_wq *wq)
110{
111 struct idxd_device *idxd = wq->idxd;
Dave Jiangbfe1d562020-01-21 16:43:59 -0700112 struct device *dev = &idxd->pdev->dev;
113 int rc, num_descs, i;
114
Dave Jiangc52ca472020-01-21 16:44:05 -0700115 if (wq->type != IDXD_WQT_KERNEL)
116 return 0;
117
Dave Jiang9806eb52021-08-06 10:38:37 -0700118 num_descs = wq_dedicated(wq) ? wq->size : wq->threshold;
119 wq->num_descs = num_descs;
Dave Jiangbfe1d562020-01-21 16:43:59 -0700120
121 rc = alloc_hw_descs(wq, num_descs);
122 if (rc < 0)
123 return rc;
124
Dave Jiang2efe58c2021-10-25 07:59:49 -0700125 wq->compls_size = num_descs * idxd->data->compl_size;
126 wq->compls = dma_alloc_coherent(dev, wq->compls_size, &wq->compls_addr, GFP_KERNEL);
127 if (!wq->compls) {
Dave Jiangbfe1d562020-01-21 16:43:59 -0700128 rc = -ENOMEM;
129 goto fail_alloc_compls;
130 }
131
132 rc = alloc_descs(wq, num_descs);
133 if (rc < 0)
134 goto fail_alloc_descs;
135
Dave Jiang07051072020-06-15 13:54:26 -0700136 rc = sbitmap_queue_init_node(&wq->sbq, num_descs, -1, false, GFP_KERNEL,
137 dev_to_node(dev));
Dave Jiangbfe1d562020-01-21 16:43:59 -0700138 if (rc < 0)
139 goto fail_sbitmap_init;
140
141 for (i = 0; i < num_descs; i++) {
142 struct idxd_desc *desc = wq->descs[i];
143
144 desc->hw = wq->hw_descs[i];
Dave Jiang435b5122021-04-15 16:38:09 -0700145 if (idxd->data->type == IDXD_TYPE_DSA)
Dave Jiangf25b46382020-11-17 13:39:14 -0700146 desc->completion = &wq->compls[i];
Dave Jiang435b5122021-04-15 16:38:09 -0700147 else if (idxd->data->type == IDXD_TYPE_IAX)
Dave Jiangf25b46382020-11-17 13:39:14 -0700148 desc->iax_completion = &wq->iax_compls[i];
Dave Jiang435b5122021-04-15 16:38:09 -0700149 desc->compl_dma = wq->compls_addr + idxd->data->compl_size * i;
Dave Jiangbfe1d562020-01-21 16:43:59 -0700150 desc->id = i;
151 desc->wq = wq;
Dave Jiang07051072020-06-15 13:54:26 -0700152 desc->cpu = -1;
Dave Jiangbfe1d562020-01-21 16:43:59 -0700153 }
154
155 return 0;
156
157 fail_sbitmap_init:
158 free_descs(wq);
159 fail_alloc_descs:
Dave Jiang2efe58c2021-10-25 07:59:49 -0700160 dma_free_coherent(dev, wq->compls_size, wq->compls, wq->compls_addr);
Dave Jiangbfe1d562020-01-21 16:43:59 -0700161 fail_alloc_compls:
162 free_hw_descs(wq);
163 return rc;
164}
165
166void idxd_wq_free_resources(struct idxd_wq *wq)
167{
168 struct device *dev = &wq->idxd->pdev->dev;
169
Dave Jiangc52ca472020-01-21 16:44:05 -0700170 if (wq->type != IDXD_WQT_KERNEL)
171 return;
172
Dave Jiangbfe1d562020-01-21 16:43:59 -0700173 free_hw_descs(wq);
174 free_descs(wq);
Dave Jiang2efe58c2021-10-25 07:59:49 -0700175 dma_free_coherent(dev, wq->compls_size, wq->compls, wq->compls_addr);
Dave Jiang07051072020-06-15 13:54:26 -0700176 sbitmap_queue_free(&wq->sbq);
Dave Jiangbfe1d562020-01-21 16:43:59 -0700177}
178
179int idxd_wq_enable(struct idxd_wq *wq)
180{
181 struct idxd_device *idxd = wq->idxd;
182 struct device *dev = &idxd->pdev->dev;
183 u32 status;
Dave Jiangbfe1d562020-01-21 16:43:59 -0700184
185 if (wq->state == IDXD_WQ_ENABLED) {
186 dev_dbg(dev, "WQ %d already enabled\n", wq->id);
187 return -ENXIO;
188 }
189
Dave Jiang0d5c10b2020-06-26 11:11:18 -0700190 idxd_cmd_exec(idxd, IDXD_CMD_ENABLE_WQ, wq->id, &status);
Dave Jiangbfe1d562020-01-21 16:43:59 -0700191
192 if (status != IDXD_CMDSTS_SUCCESS &&
193 status != IDXD_CMDSTS_ERR_WQ_ENABLED) {
194 dev_dbg(dev, "WQ enable failed: %#x\n", status);
195 return -ENXIO;
196 }
197
198 wq->state = IDXD_WQ_ENABLED;
199 dev_dbg(dev, "WQ %d enabled\n", wq->id);
200 return 0;
201}
202
Dave Jiang0dcfe412021-06-04 17:06:21 -0700203int idxd_wq_disable(struct idxd_wq *wq, bool reset_config)
Dave Jiangbfe1d562020-01-21 16:43:59 -0700204{
205 struct idxd_device *idxd = wq->idxd;
206 struct device *dev = &idxd->pdev->dev;
207 u32 status, operand;
Dave Jiangbfe1d562020-01-21 16:43:59 -0700208
Dave Jiangbfe1d562020-01-21 16:43:59 -0700209 dev_dbg(dev, "Disabling WQ %d\n", wq->id);
210
211 if (wq->state != IDXD_WQ_ENABLED) {
212 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state);
213 return 0;
214 }
215
216 operand = BIT(wq->id % 16) | ((wq->id / 16) << 16);
Dave Jiang0d5c10b2020-06-26 11:11:18 -0700217 idxd_cmd_exec(idxd, IDXD_CMD_DISABLE_WQ, operand, &status);
Dave Jiangbfe1d562020-01-21 16:43:59 -0700218
219 if (status != IDXD_CMDSTS_SUCCESS) {
220 dev_dbg(dev, "WQ disable failed: %#x\n", status);
221 return -ENXIO;
222 }
223
Dave Jiang0dcfe412021-06-04 17:06:21 -0700224 if (reset_config)
225 idxd_wq_disable_cleanup(wq);
Dave Jiangbfe1d562020-01-21 16:43:59 -0700226 wq->state = IDXD_WQ_DISABLED;
227 dev_dbg(dev, "WQ %d disabled\n", wq->id);
228 return 0;
229}
230
Dave Jiang0d5c10b2020-06-26 11:11:18 -0700231void idxd_wq_drain(struct idxd_wq *wq)
232{
233 struct idxd_device *idxd = wq->idxd;
234 struct device *dev = &idxd->pdev->dev;
235 u32 operand;
236
237 if (wq->state != IDXD_WQ_ENABLED) {
238 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state);
239 return;
240 }
241
242 dev_dbg(dev, "Draining WQ %d\n", wq->id);
243 operand = BIT(wq->id % 16) | ((wq->id / 16) << 16);
244 idxd_cmd_exec(idxd, IDXD_CMD_DRAIN_WQ, operand, NULL);
245}
246
Dave Jiangea9aadc2021-04-12 09:02:36 -0700247void idxd_wq_reset(struct idxd_wq *wq)
248{
249 struct idxd_device *idxd = wq->idxd;
250 struct device *dev = &idxd->pdev->dev;
251 u32 operand;
252
253 if (wq->state != IDXD_WQ_ENABLED) {
254 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state);
255 return;
256 }
257
258 operand = BIT(wq->id % 16) | ((wq->id / 16) << 16);
259 idxd_cmd_exec(idxd, IDXD_CMD_RESET_WQ, operand, NULL);
Dave Jiang0dcfe412021-06-04 17:06:21 -0700260 idxd_wq_disable_cleanup(wq);
Dave Jiangea9aadc2021-04-12 09:02:36 -0700261 wq->state = IDXD_WQ_DISABLED;
262}
263
Dave Jiangc52ca472020-01-21 16:44:05 -0700264int idxd_wq_map_portal(struct idxd_wq *wq)
265{
266 struct idxd_device *idxd = wq->idxd;
267 struct pci_dev *pdev = idxd->pdev;
268 struct device *dev = &pdev->dev;
269 resource_size_t start;
270
271 start = pci_resource_start(pdev, IDXD_WQ_BAR);
Dave Jiang8326be92020-11-11 15:23:46 -0700272 start += idxd_get_wq_portal_full_offset(wq->id, IDXD_PORTAL_LIMITED);
Dave Jiangc52ca472020-01-21 16:44:05 -0700273
Dave Jiang8e50d392020-10-27 10:34:35 -0700274 wq->portal = devm_ioremap(dev, start, IDXD_PORTAL_SIZE);
275 if (!wq->portal)
Dave Jiangc52ca472020-01-21 16:44:05 -0700276 return -ENOMEM;
Dave Jiangc52ca472020-01-21 16:44:05 -0700277
278 return 0;
279}
280
281void idxd_wq_unmap_portal(struct idxd_wq *wq)
282{
283 struct device *dev = &wq->idxd->pdev->dev;
284
Dave Jiang8e50d392020-10-27 10:34:35 -0700285 devm_iounmap(dev, wq->portal);
Dave Jiang5b0c68c2021-04-20 11:46:51 -0700286 wq->portal = NULL;
Dave Jianga9c17152021-07-20 13:42:04 -0700287 wq->portal_offset = 0;
Dave Jiang5b0c68c2021-04-20 11:46:51 -0700288}
289
290void idxd_wqs_unmap_portal(struct idxd_device *idxd)
291{
292 int i;
293
294 for (i = 0; i < idxd->max_wqs; i++) {
295 struct idxd_wq *wq = idxd->wqs[i];
296
297 if (wq->portal)
298 idxd_wq_unmap_portal(wq);
299 }
Dave Jiang8e50d392020-10-27 10:34:35 -0700300}
301
302int idxd_wq_set_pasid(struct idxd_wq *wq, int pasid)
303{
304 struct idxd_device *idxd = wq->idxd;
305 int rc;
306 union wqcfg wqcfg;
307 unsigned int offset;
Dave Jiang8e50d392020-10-27 10:34:35 -0700308
Dave Jiang0dcfe412021-06-04 17:06:21 -0700309 rc = idxd_wq_disable(wq, false);
Dave Jiang8e50d392020-10-27 10:34:35 -0700310 if (rc < 0)
311 return rc;
312
313 offset = WQCFG_OFFSET(idxd, wq->id, WQCFG_PASID_IDX);
Dave Jiangcf84a4b2021-08-24 14:24:27 -0700314 spin_lock(&idxd->dev_lock);
Dave Jiang8e50d392020-10-27 10:34:35 -0700315 wqcfg.bits[WQCFG_PASID_IDX] = ioread32(idxd->reg_base + offset);
316 wqcfg.pasid_en = 1;
317 wqcfg.pasid = pasid;
318 iowrite32(wqcfg.bits[WQCFG_PASID_IDX], idxd->reg_base + offset);
Dave Jiangcf84a4b2021-08-24 14:24:27 -0700319 spin_unlock(&idxd->dev_lock);
Dave Jiang8e50d392020-10-27 10:34:35 -0700320
321 rc = idxd_wq_enable(wq);
322 if (rc < 0)
323 return rc;
324
325 return 0;
326}
327
328int idxd_wq_disable_pasid(struct idxd_wq *wq)
329{
330 struct idxd_device *idxd = wq->idxd;
331 int rc;
332 union wqcfg wqcfg;
333 unsigned int offset;
Dave Jiang8e50d392020-10-27 10:34:35 -0700334
Dave Jiang0dcfe412021-06-04 17:06:21 -0700335 rc = idxd_wq_disable(wq, false);
Dave Jiang8e50d392020-10-27 10:34:35 -0700336 if (rc < 0)
337 return rc;
338
339 offset = WQCFG_OFFSET(idxd, wq->id, WQCFG_PASID_IDX);
Dave Jiangcf84a4b2021-08-24 14:24:27 -0700340 spin_lock(&idxd->dev_lock);
Dave Jiang8e50d392020-10-27 10:34:35 -0700341 wqcfg.bits[WQCFG_PASID_IDX] = ioread32(idxd->reg_base + offset);
342 wqcfg.pasid_en = 0;
343 wqcfg.pasid = 0;
344 iowrite32(wqcfg.bits[WQCFG_PASID_IDX], idxd->reg_base + offset);
Dave Jiangcf84a4b2021-08-24 14:24:27 -0700345 spin_unlock(&idxd->dev_lock);
Dave Jiang8e50d392020-10-27 10:34:35 -0700346
347 rc = idxd_wq_enable(wq);
348 if (rc < 0)
349 return rc;
350
351 return 0;
Dave Jiangc52ca472020-01-21 16:44:05 -0700352}
353
Dave Jiang0dcfe412021-06-04 17:06:21 -0700354static void idxd_wq_disable_cleanup(struct idxd_wq *wq)
Dave Jiangda32b282020-06-25 12:17:42 -0700355{
356 struct idxd_device *idxd = wq->idxd;
Dave Jiangda32b282020-06-25 12:17:42 -0700357
Dave Jiang0dcfe412021-06-04 17:06:21 -0700358 lockdep_assert_held(&wq->wq_lock);
Dave Jiang484f9102020-10-27 14:34:09 -0700359 memset(wq->wqcfg, 0, idxd->wqcfg_size);
Dave Jiangda32b282020-06-25 12:17:42 -0700360 wq->type = IDXD_WQT_NONE;
Dave Jiangda32b282020-06-25 12:17:42 -0700361 wq->threshold = 0;
362 wq->priority = 0;
Dave Jiang92de5fa2020-11-13 15:55:05 -0700363 wq->ats_dis = 0;
Dave Jiang7930d852021-11-29 10:19:38 -0700364 wq->enqcmds_retries = IDXD_ENQCMDS_RETRIES;
Dave Jiangda32b282020-06-25 12:17:42 -0700365 clear_bit(WQ_FLAG_DEDICATED, &wq->flags);
Dave Jiangbd2f4ae2021-08-03 15:37:15 -0700366 clear_bit(WQ_FLAG_BLOCK_ON_FAULT, &wq->flags);
Dave Jiangda32b282020-06-25 12:17:42 -0700367 memset(wq->name, 0, WQ_NAME_SIZE);
Dave Jiang92452a72021-10-26 14:45:34 -0700368 wq->max_xfer_bytes = WQ_DEFAULT_MAX_XFER;
369 wq->max_batch_size = WQ_DEFAULT_MAX_BATCH;
Dave Jiangda32b282020-06-25 12:17:42 -0700370}
371
Dave Jiang0f225702021-12-14 13:15:17 -0700372static void idxd_wq_device_reset_cleanup(struct idxd_wq *wq)
373{
374 lockdep_assert_held(&wq->wq_lock);
375
376 idxd_wq_disable_cleanup(wq);
377 wq->size = 0;
378 wq->group = NULL;
379}
380
Dave Jiang93a40a62021-04-20 11:46:22 -0700381static void idxd_wq_ref_release(struct percpu_ref *ref)
382{
383 struct idxd_wq *wq = container_of(ref, struct idxd_wq, wq_active);
384
385 complete(&wq->wq_dead);
386}
387
388int idxd_wq_init_percpu_ref(struct idxd_wq *wq)
389{
390 int rc;
391
392 memset(&wq->wq_active, 0, sizeof(wq->wq_active));
Dave Jiang56fc39f2021-10-26 14:36:41 -0700393 rc = percpu_ref_init(&wq->wq_active, idxd_wq_ref_release,
394 PERCPU_REF_ALLOW_REINIT, GFP_KERNEL);
Dave Jiang93a40a62021-04-20 11:46:22 -0700395 if (rc < 0)
396 return rc;
397 reinit_completion(&wq->wq_dead);
Dave Jiang56fc39f2021-10-26 14:36:41 -0700398 reinit_completion(&wq->wq_resurrect);
Dave Jiang93a40a62021-04-20 11:46:22 -0700399 return 0;
400}
401
Dave Jiangbd5970a2021-10-26 14:36:29 -0700402void __idxd_wq_quiesce(struct idxd_wq *wq)
Dave Jiang93a40a62021-04-20 11:46:22 -0700403{
Dave Jiangbd5970a2021-10-26 14:36:29 -0700404 lockdep_assert_held(&wq->wq_lock);
Dave Jiang56fc39f2021-10-26 14:36:41 -0700405 reinit_completion(&wq->wq_resurrect);
Dave Jiang93a40a62021-04-20 11:46:22 -0700406 percpu_ref_kill(&wq->wq_active);
Dave Jiang56fc39f2021-10-26 14:36:41 -0700407 complete_all(&wq->wq_resurrect);
Dave Jiang93a40a62021-04-20 11:46:22 -0700408 wait_for_completion(&wq->wq_dead);
Dave Jiang93a40a62021-04-20 11:46:22 -0700409}
410
Dave Jiangbd5970a2021-10-26 14:36:29 -0700411void idxd_wq_quiesce(struct idxd_wq *wq)
412{
413 mutex_lock(&wq->wq_lock);
414 __idxd_wq_quiesce(wq);
415 mutex_unlock(&wq->wq_lock);
416}
417
Dave Jiangbfe1d562020-01-21 16:43:59 -0700418/* Device control bits */
419static inline bool idxd_is_enabled(struct idxd_device *idxd)
420{
421 union gensts_reg gensts;
422
423 gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET);
424
425 if (gensts.state == IDXD_DEVICE_STATE_ENABLED)
426 return true;
427 return false;
428}
429
Dave Jiang89e3bec2021-02-01 08:26:14 -0700430static inline bool idxd_device_is_halted(struct idxd_device *idxd)
431{
432 union gensts_reg gensts;
433
434 gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET);
435
436 return (gensts.state == IDXD_DEVICE_STATE_HALT);
437}
438
Dave Jiang0d5c10b2020-06-26 11:11:18 -0700439/*
440 * This is function is only used for reset during probe and will
441 * poll for completion. Once the device is setup with interrupts,
442 * all commands will be done via interrupt completion.
443 */
Dave Jiang89e3bec2021-02-01 08:26:14 -0700444int idxd_device_init_reset(struct idxd_device *idxd)
Dave Jiangbfe1d562020-01-21 16:43:59 -0700445{
Dave Jiang0d5c10b2020-06-26 11:11:18 -0700446 struct device *dev = &idxd->pdev->dev;
447 union idxd_command_reg cmd;
Dave Jiangbfe1d562020-01-21 16:43:59 -0700448
Dave Jiang89e3bec2021-02-01 08:26:14 -0700449 if (idxd_device_is_halted(idxd)) {
450 dev_warn(&idxd->pdev->dev, "Device is HALTED!\n");
451 return -ENXIO;
452 }
453
Dave Jiang0d5c10b2020-06-26 11:11:18 -0700454 memset(&cmd, 0, sizeof(cmd));
455 cmd.cmd = IDXD_CMD_RESET_DEVICE;
456 dev_dbg(dev, "%s: sending reset for init.\n", __func__);
Dave Jiangf9f40822021-08-24 14:24:39 -0700457 spin_lock(&idxd->cmd_lock);
Dave Jiang0d5c10b2020-06-26 11:11:18 -0700458 iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET);
459
460 while (ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET) &
461 IDXD_CMDSTS_ACTIVE)
Dave Jiangbfe1d562020-01-21 16:43:59 -0700462 cpu_relax();
Dave Jiangf9f40822021-08-24 14:24:39 -0700463 spin_unlock(&idxd->cmd_lock);
Dave Jiang89e3bec2021-02-01 08:26:14 -0700464 return 0;
Dave Jiangbfe1d562020-01-21 16:43:59 -0700465}
466
Dave Jiang0d5c10b2020-06-26 11:11:18 -0700467static void idxd_cmd_exec(struct idxd_device *idxd, int cmd_code, u32 operand,
468 u32 *status)
Dave Jiangbfe1d562020-01-21 16:43:59 -0700469{
470 union idxd_command_reg cmd;
Dave Jiang0d5c10b2020-06-26 11:11:18 -0700471 DECLARE_COMPLETION_ONSTACK(done);
Dave Jiang53499d12021-06-03 11:01:37 -0700472 u32 stat;
Dave Jiangbfe1d562020-01-21 16:43:59 -0700473
Dave Jiang89e3bec2021-02-01 08:26:14 -0700474 if (idxd_device_is_halted(idxd)) {
475 dev_warn(&idxd->pdev->dev, "Device is HALTED!\n");
Colin Ian King28ac8e02021-04-15 12:06:54 +0100476 if (status)
477 *status = IDXD_CMDSTS_HW_ERR;
Dave Jiang89e3bec2021-02-01 08:26:14 -0700478 return;
479 }
480
Dave Jiangbfe1d562020-01-21 16:43:59 -0700481 memset(&cmd, 0, sizeof(cmd));
482 cmd.cmd = cmd_code;
483 cmd.operand = operand;
Dave Jiang0d5c10b2020-06-26 11:11:18 -0700484 cmd.int_req = 1;
485
Dave Jiangf9f40822021-08-24 14:24:39 -0700486 spin_lock(&idxd->cmd_lock);
Dave Jiang0d5c10b2020-06-26 11:11:18 -0700487 wait_event_lock_irq(idxd->cmd_waitq,
488 !test_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags),
Dave Jiang53b2ee7f2021-04-20 12:00:56 -0700489 idxd->cmd_lock);
Dave Jiang0d5c10b2020-06-26 11:11:18 -0700490
Dave Jiangbfe1d562020-01-21 16:43:59 -0700491 dev_dbg(&idxd->pdev->dev, "%s: sending cmd: %#x op: %#x\n",
492 __func__, cmd_code, operand);
Dave Jiang0d5c10b2020-06-26 11:11:18 -0700493
Dave Jiangff18de52020-08-28 15:13:55 -0700494 idxd->cmd_status = 0;
Dave Jiang0d5c10b2020-06-26 11:11:18 -0700495 __set_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags);
496 idxd->cmd_done = &done;
Dave Jiangbfe1d562020-01-21 16:43:59 -0700497 iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET);
498
Dave Jiang0d5c10b2020-06-26 11:11:18 -0700499 /*
500 * After command submitted, release lock and go to sleep until
501 * the command completes via interrupt.
502 */
Dave Jiangf9f40822021-08-24 14:24:39 -0700503 spin_unlock(&idxd->cmd_lock);
Dave Jiang0d5c10b2020-06-26 11:11:18 -0700504 wait_for_completion(&done);
Dave Jiang53499d12021-06-03 11:01:37 -0700505 stat = ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET);
Dave Jiangf9f40822021-08-24 14:24:39 -0700506 spin_lock(&idxd->cmd_lock);
Dave Jiang53499d12021-06-03 11:01:37 -0700507 if (status)
508 *status = stat;
509 idxd->cmd_status = stat & GENMASK(7, 0);
Dave Jiangff18de52020-08-28 15:13:55 -0700510
Dave Jiang0d5c10b2020-06-26 11:11:18 -0700511 __clear_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags);
512 /* Wake up other pending commands */
513 wake_up(&idxd->cmd_waitq);
Dave Jiangf9f40822021-08-24 14:24:39 -0700514 spin_unlock(&idxd->cmd_lock);
Dave Jiangbfe1d562020-01-21 16:43:59 -0700515}
516
517int idxd_device_enable(struct idxd_device *idxd)
518{
519 struct device *dev = &idxd->pdev->dev;
Dave Jiangbfe1d562020-01-21 16:43:59 -0700520 u32 status;
521
Dave Jiangbfe1d562020-01-21 16:43:59 -0700522 if (idxd_is_enabled(idxd)) {
523 dev_dbg(dev, "Device already enabled\n");
524 return -ENXIO;
525 }
526
Dave Jiang0d5c10b2020-06-26 11:11:18 -0700527 idxd_cmd_exec(idxd, IDXD_CMD_ENABLE_DEVICE, 0, &status);
Dave Jiangbfe1d562020-01-21 16:43:59 -0700528
529 /* If the command is successful or if the device was enabled */
530 if (status != IDXD_CMDSTS_SUCCESS &&
531 status != IDXD_CMDSTS_ERR_DEV_ENABLED) {
532 dev_dbg(dev, "%s: err_code: %#x\n", __func__, status);
533 return -ENXIO;
534 }
535
536 idxd->state = IDXD_DEV_ENABLED;
537 return 0;
538}
539
540int idxd_device_disable(struct idxd_device *idxd)
541{
542 struct device *dev = &idxd->pdev->dev;
Dave Jiangbfe1d562020-01-21 16:43:59 -0700543 u32 status;
544
Dave Jiangbfe1d562020-01-21 16:43:59 -0700545 if (!idxd_is_enabled(idxd)) {
546 dev_dbg(dev, "Device is not enabled\n");
547 return 0;
548 }
549
Dave Jiang0d5c10b2020-06-26 11:11:18 -0700550 idxd_cmd_exec(idxd, IDXD_CMD_DISABLE_DEVICE, 0, &status);
Dave Jiangbfe1d562020-01-21 16:43:59 -0700551
552 /* If the command is successful or if the device was disabled */
553 if (status != IDXD_CMDSTS_SUCCESS &&
554 !(status & IDXD_CMDSTS_ERR_DIS_DEV_EN)) {
555 dev_dbg(dev, "%s: err_code: %#x\n", __func__, status);
Dave Jiang0d5c10b2020-06-26 11:11:18 -0700556 return -ENXIO;
Dave Jiangbfe1d562020-01-21 16:43:59 -0700557 }
558
Dave Jiangcf84a4b2021-08-24 14:24:27 -0700559 spin_lock(&idxd->dev_lock);
Dave Jiang0dcfe412021-06-04 17:06:21 -0700560 idxd_device_clear_state(idxd);
Dave Jiangf52058ae2021-07-15 11:43:26 -0700561 idxd->state = IDXD_DEV_DISABLED;
Dave Jiangcf84a4b2021-08-24 14:24:27 -0700562 spin_unlock(&idxd->dev_lock);
Dave Jiangbfe1d562020-01-21 16:43:59 -0700563 return 0;
564}
565
Dave Jiang0d5c10b2020-06-26 11:11:18 -0700566void idxd_device_reset(struct idxd_device *idxd)
Dave Jiangbfe1d562020-01-21 16:43:59 -0700567{
Dave Jiang0d5c10b2020-06-26 11:11:18 -0700568 idxd_cmd_exec(idxd, IDXD_CMD_RESET_DEVICE, 0, NULL);
Dave Jiangcf84a4b2021-08-24 14:24:27 -0700569 spin_lock(&idxd->dev_lock);
Dave Jiang0dcfe412021-06-04 17:06:21 -0700570 idxd_device_clear_state(idxd);
Dave Jiangf52058ae2021-07-15 11:43:26 -0700571 idxd->state = IDXD_DEV_DISABLED;
Dave Jiange530a9f2021-09-01 17:18:05 -0700572 idxd_unmask_error_interrupts(idxd);
Dave Jiangcf84a4b2021-08-24 14:24:27 -0700573 spin_unlock(&idxd->dev_lock);
Dave Jiangbfe1d562020-01-21 16:43:59 -0700574}
575
Dave Jiang8e50d392020-10-27 10:34:35 -0700576void idxd_device_drain_pasid(struct idxd_device *idxd, int pasid)
577{
578 struct device *dev = &idxd->pdev->dev;
579 u32 operand;
580
581 operand = pasid;
582 dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_DRAIN_PASID, operand);
583 idxd_cmd_exec(idxd, IDXD_CMD_DRAIN_PASID, operand, NULL);
584 dev_dbg(dev, "pasid %d drained\n", pasid);
585}
586
Dave Jiangeb15e712021-04-20 11:46:34 -0700587int idxd_device_request_int_handle(struct idxd_device *idxd, int idx, int *handle,
588 enum idxd_interrupt_type irq_type)
589{
590 struct device *dev = &idxd->pdev->dev;
591 u32 operand, status;
592
593 if (!(idxd->hw.cmd_cap & BIT(IDXD_CMD_REQUEST_INT_HANDLE)))
594 return -EOPNOTSUPP;
595
596 dev_dbg(dev, "get int handle, idx %d\n", idx);
597
598 operand = idx & GENMASK(15, 0);
599 if (irq_type == IDXD_IRQ_IMS)
600 operand |= CMD_INT_HANDLE_IMS;
601
602 dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_REQUEST_INT_HANDLE, operand);
603
604 idxd_cmd_exec(idxd, IDXD_CMD_REQUEST_INT_HANDLE, operand, &status);
605
606 if ((status & IDXD_CMDSTS_ERR_MASK) != IDXD_CMDSTS_SUCCESS) {
607 dev_dbg(dev, "request int handle failed: %#x\n", status);
608 return -ENXIO;
609 }
610
611 *handle = (status >> IDXD_CMDSTS_RES_SHIFT) & GENMASK(15, 0);
612
613 dev_dbg(dev, "int handle acquired: %u\n", *handle);
614 return 0;
615}
616
617int idxd_device_release_int_handle(struct idxd_device *idxd, int handle,
618 enum idxd_interrupt_type irq_type)
619{
620 struct device *dev = &idxd->pdev->dev;
621 u32 operand, status;
622 union idxd_command_reg cmd;
Dave Jiangeb15e712021-04-20 11:46:34 -0700623
624 if (!(idxd->hw.cmd_cap & BIT(IDXD_CMD_RELEASE_INT_HANDLE)))
625 return -EOPNOTSUPP;
626
627 dev_dbg(dev, "release int handle, handle %d\n", handle);
628
629 memset(&cmd, 0, sizeof(cmd));
630 operand = handle & GENMASK(15, 0);
631
632 if (irq_type == IDXD_IRQ_IMS)
633 operand |= CMD_INT_HANDLE_IMS;
634
635 cmd.cmd = IDXD_CMD_RELEASE_INT_HANDLE;
636 cmd.operand = operand;
637
638 dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_RELEASE_INT_HANDLE, operand);
639
Dave Jiangf9f40822021-08-24 14:24:39 -0700640 spin_lock(&idxd->cmd_lock);
Dave Jiangeb15e712021-04-20 11:46:34 -0700641 iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET);
642
643 while (ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET) & IDXD_CMDSTS_ACTIVE)
644 cpu_relax();
645 status = ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET);
Dave Jiangf9f40822021-08-24 14:24:39 -0700646 spin_unlock(&idxd->cmd_lock);
Dave Jiangeb15e712021-04-20 11:46:34 -0700647
648 if ((status & IDXD_CMDSTS_ERR_MASK) != IDXD_CMDSTS_SUCCESS) {
649 dev_dbg(dev, "release int handle failed: %#x\n", status);
650 return -ENXIO;
651 }
652
653 dev_dbg(dev, "int handle released.\n");
654 return 0;
655}
656
Dave Jiangbfe1d562020-01-21 16:43:59 -0700657/* Device configuration bits */
Dave Jiang0dcfe412021-06-04 17:06:21 -0700658static void idxd_engines_clear_state(struct idxd_device *idxd)
659{
660 struct idxd_engine *engine;
661 int i;
662
663 lockdep_assert_held(&idxd->dev_lock);
664 for (i = 0; i < idxd->max_engines; i++) {
665 engine = idxd->engines[i];
666 engine->group = NULL;
667 }
668}
669
670static void idxd_groups_clear_state(struct idxd_device *idxd)
671{
672 struct idxd_group *group;
673 int i;
674
675 lockdep_assert_held(&idxd->dev_lock);
676 for (i = 0; i < idxd->max_groups; i++) {
677 group = idxd->groups[i];
678 memset(&group->grpcfg, 0, sizeof(group->grpcfg));
679 group->num_engines = 0;
680 group->num_wqs = 0;
Dave Jiang7ed6f1b2021-12-14 13:23:09 -0700681 group->use_rdbuf_limit = false;
682 group->rdbufs_allowed = 0;
683 group->rdbufs_reserved = 0;
Dave Jiang0dcfe412021-06-04 17:06:21 -0700684 group->tc_a = -1;
685 group->tc_b = -1;
686 }
687}
688
689static void idxd_device_wqs_clear_state(struct idxd_device *idxd)
690{
691 int i;
692
693 lockdep_assert_held(&idxd->dev_lock);
694 for (i = 0; i < idxd->max_wqs; i++) {
695 struct idxd_wq *wq = idxd->wqs[i];
696
697 if (wq->state == IDXD_WQ_ENABLED) {
698 idxd_wq_disable_cleanup(wq);
Dave Jiang0f225702021-12-14 13:15:17 -0700699 idxd_wq_device_reset_cleanup(wq);
Dave Jiang0dcfe412021-06-04 17:06:21 -0700700 wq->state = IDXD_WQ_DISABLED;
701 }
702 }
703}
704
705void idxd_device_clear_state(struct idxd_device *idxd)
706{
707 idxd_groups_clear_state(idxd);
708 idxd_engines_clear_state(idxd);
709 idxd_device_wqs_clear_state(idxd);
710}
711
Dave Jiangbfe1d562020-01-21 16:43:59 -0700712static void idxd_group_config_write(struct idxd_group *group)
713{
714 struct idxd_device *idxd = group->idxd;
715 struct device *dev = &idxd->pdev->dev;
716 int i;
717 u32 grpcfg_offset;
718
719 dev_dbg(dev, "Writing group %d cfg registers\n", group->id);
720
721 /* setup GRPWQCFG */
Dave Jiang5a712702020-10-30 08:49:06 -0700722 for (i = 0; i < GRPWQCFG_STRIDES; i++) {
723 grpcfg_offset = GRPWQCFG_OFFSET(idxd, group->id, i);
724 iowrite64(group->grpcfg.wqs[i], idxd->reg_base + grpcfg_offset);
Dave Jiangbfe1d562020-01-21 16:43:59 -0700725 dev_dbg(dev, "GRPCFG wq[%d:%d: %#x]: %#llx\n",
726 group->id, i, grpcfg_offset,
727 ioread64(idxd->reg_base + grpcfg_offset));
728 }
729
730 /* setup GRPENGCFG */
Dave Jiang5a712702020-10-30 08:49:06 -0700731 grpcfg_offset = GRPENGCFG_OFFSET(idxd, group->id);
Dave Jiangbfe1d562020-01-21 16:43:59 -0700732 iowrite64(group->grpcfg.engines, idxd->reg_base + grpcfg_offset);
733 dev_dbg(dev, "GRPCFG engs[%d: %#x]: %#llx\n", group->id,
734 grpcfg_offset, ioread64(idxd->reg_base + grpcfg_offset));
735
736 /* setup GRPFLAGS */
Dave Jiang5a712702020-10-30 08:49:06 -0700737 grpcfg_offset = GRPFLGCFG_OFFSET(idxd, group->id);
Dave Jiangbfe1d562020-01-21 16:43:59 -0700738 iowrite32(group->grpcfg.flags.bits, idxd->reg_base + grpcfg_offset);
739 dev_dbg(dev, "GRPFLAGS flags[%d: %#x]: %#x\n",
740 group->id, grpcfg_offset,
741 ioread32(idxd->reg_base + grpcfg_offset));
742}
743
744static int idxd_groups_config_write(struct idxd_device *idxd)
745
746{
747 union gencfg_reg reg;
748 int i;
749 struct device *dev = &idxd->pdev->dev;
750
Dave Jiang7ed6f1b2021-12-14 13:23:09 -0700751 /* Setup bandwidth rdbuf limit */
752 if (idxd->hw.gen_cap.config_en && idxd->rdbuf_limit) {
Dave Jiangbfe1d562020-01-21 16:43:59 -0700753 reg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET);
Dave Jiang7ed6f1b2021-12-14 13:23:09 -0700754 reg.rdbuf_limit = idxd->rdbuf_limit;
Dave Jiangbfe1d562020-01-21 16:43:59 -0700755 iowrite32(reg.bits, idxd->reg_base + IDXD_GENCFG_OFFSET);
756 }
757
758 dev_dbg(dev, "GENCFG(%#x): %#x\n", IDXD_GENCFG_OFFSET,
759 ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET));
760
761 for (i = 0; i < idxd->max_groups; i++) {
Dave Jiangdefe49f2021-04-15 16:37:51 -0700762 struct idxd_group *group = idxd->groups[i];
Dave Jiangbfe1d562020-01-21 16:43:59 -0700763
764 idxd_group_config_write(group);
765 }
766
767 return 0;
768}
769
Dave Jiangd8071322021-08-19 09:34:06 -0700770static bool idxd_device_pasid_priv_enabled(struct idxd_device *idxd)
771{
772 struct pci_dev *pdev = idxd->pdev;
773
774 if (pdev->pasid_enabled && (pdev->pasid_features & PCI_PASID_CAP_PRIV))
775 return true;
776 return false;
777}
778
Dave Jiangbfe1d562020-01-21 16:43:59 -0700779static int idxd_wq_config_write(struct idxd_wq *wq)
780{
781 struct idxd_device *idxd = wq->idxd;
782 struct device *dev = &idxd->pdev->dev;
783 u32 wq_offset;
784 int i;
785
786 if (!wq->group)
787 return 0;
788
Dave Jiangea9aadc2021-04-12 09:02:36 -0700789 /*
790 * Instead of memset the entire shadow copy of WQCFG, copy from the hardware after
791 * wq reset. This will copy back the sticky values that are present on some devices.
792 */
793 for (i = 0; i < WQCFG_STRIDES(idxd); i++) {
794 wq_offset = WQCFG_OFFSET(idxd, wq->id, i);
795 wq->wqcfg->bits[i] = ioread32(idxd->reg_base + wq_offset);
796 }
Dave Jiangbfe1d562020-01-21 16:43:59 -0700797
Dave Jiang92452a72021-10-26 14:45:34 -0700798 if (wq->size == 0 && wq->type != IDXD_WQT_NONE)
799 wq->size = WQ_DEFAULT_QUEUE_DEPTH;
800
Dave Jiangbfe1d562020-01-21 16:43:59 -0700801 /* byte 0-3 */
Dave Jiang484f9102020-10-27 14:34:09 -0700802 wq->wqcfg->wq_size = wq->size;
Dave Jiangbfe1d562020-01-21 16:43:59 -0700803
Dave Jiangbfe1d562020-01-21 16:43:59 -0700804 /* bytes 4-7 */
Dave Jiang484f9102020-10-27 14:34:09 -0700805 wq->wqcfg->wq_thresh = wq->threshold;
Dave Jiangbfe1d562020-01-21 16:43:59 -0700806
807 /* byte 8-11 */
Dave Jiang8e50d392020-10-27 10:34:35 -0700808 if (wq_dedicated(wq))
809 wq->wqcfg->mode = 1;
810
811 if (device_pasid_enabled(idxd)) {
812 wq->wqcfg->pasid_en = 1;
813 if (wq->type == IDXD_WQT_KERNEL && wq_dedicated(wq))
814 wq->wqcfg->pasid = idxd->pasid;
815 }
816
Dave Jiangd8071322021-08-19 09:34:06 -0700817 /*
818 * Here the priv bit is set depending on the WQ type. priv = 1 if the
819 * WQ type is kernel to indicate privileged access. This setting only
820 * matters for dedicated WQ. According to the DSA spec:
821 * If the WQ is in dedicated mode, WQ PASID Enable is 1, and the
822 * Privileged Mode Enable field of the PCI Express PASID capability
823 * is 0, this field must be 0.
824 *
825 * In the case of a dedicated kernel WQ that is not able to support
826 * the PASID cap, then the configuration will be rejected.
827 */
828 wq->wqcfg->priv = !!(wq->type == IDXD_WQT_KERNEL);
829 if (wq_dedicated(wq) && wq->wqcfg->pasid_en &&
830 !idxd_device_pasid_priv_enabled(idxd) &&
831 wq->type == IDXD_WQT_KERNEL) {
832 idxd->cmd_status = IDXD_SCMD_WQ_NO_PRIV;
833 return -EOPNOTSUPP;
834 }
835
Dave Jiang484f9102020-10-27 14:34:09 -0700836 wq->wqcfg->priority = wq->priority;
Dave Jiangbfe1d562020-01-21 16:43:59 -0700837
Dave Jiang8e50d392020-10-27 10:34:35 -0700838 if (idxd->hw.gen_cap.block_on_fault &&
839 test_bit(WQ_FLAG_BLOCK_ON_FAULT, &wq->flags))
840 wq->wqcfg->bof = 1;
841
Dave Jiang92de5fa2020-11-13 15:55:05 -0700842 if (idxd->hw.wq_cap.wq_ats_support)
843 wq->wqcfg->wq_ats_disable = wq->ats_dis;
844
Dave Jiangbfe1d562020-01-21 16:43:59 -0700845 /* bytes 12-15 */
Dave Jiang484f9102020-10-27 14:34:09 -0700846 wq->wqcfg->max_xfer_shift = ilog2(wq->max_xfer_bytes);
847 wq->wqcfg->max_batch_shift = ilog2(wq->max_batch_size);
Dave Jiangbfe1d562020-01-21 16:43:59 -0700848
849 dev_dbg(dev, "WQ %d CFGs\n", wq->id);
Dave Jiang484f9102020-10-27 14:34:09 -0700850 for (i = 0; i < WQCFG_STRIDES(idxd); i++) {
851 wq_offset = WQCFG_OFFSET(idxd, wq->id, i);
852 iowrite32(wq->wqcfg->bits[i], idxd->reg_base + wq_offset);
Dave Jiangbfe1d562020-01-21 16:43:59 -0700853 dev_dbg(dev, "WQ[%d][%d][%#x]: %#x\n",
854 wq->id, i, wq_offset,
855 ioread32(idxd->reg_base + wq_offset));
856 }
857
858 return 0;
859}
860
861static int idxd_wqs_config_write(struct idxd_device *idxd)
862{
863 int i, rc;
864
865 for (i = 0; i < idxd->max_wqs; i++) {
Dave Jiang7c5dd232021-04-15 16:37:39 -0700866 struct idxd_wq *wq = idxd->wqs[i];
Dave Jiangbfe1d562020-01-21 16:43:59 -0700867
868 rc = idxd_wq_config_write(wq);
869 if (rc < 0)
870 return rc;
871 }
872
873 return 0;
874}
875
876static void idxd_group_flags_setup(struct idxd_device *idxd)
877{
878 int i;
879
880 /* TC-A 0 and TC-B 1 should be defaults */
881 for (i = 0; i < idxd->max_groups; i++) {
Dave Jiangdefe49f2021-04-15 16:37:51 -0700882 struct idxd_group *group = idxd->groups[i];
Dave Jiangbfe1d562020-01-21 16:43:59 -0700883
884 if (group->tc_a == -1)
Dave Jianga1fcaf02020-03-10 10:50:30 -0700885 group->tc_a = group->grpcfg.flags.tc_a = 0;
Dave Jiangbfe1d562020-01-21 16:43:59 -0700886 else
887 group->grpcfg.flags.tc_a = group->tc_a;
888 if (group->tc_b == -1)
Dave Jianga1fcaf02020-03-10 10:50:30 -0700889 group->tc_b = group->grpcfg.flags.tc_b = 1;
Dave Jiangbfe1d562020-01-21 16:43:59 -0700890 else
891 group->grpcfg.flags.tc_b = group->tc_b;
Dave Jiang7ed6f1b2021-12-14 13:23:09 -0700892 group->grpcfg.flags.use_rdbuf_limit = group->use_rdbuf_limit;
893 group->grpcfg.flags.rdbufs_reserved = group->rdbufs_reserved;
894 if (group->rdbufs_allowed)
895 group->grpcfg.flags.rdbufs_allowed = group->rdbufs_allowed;
Dave Jiangbfe1d562020-01-21 16:43:59 -0700896 else
Dave Jiang7ed6f1b2021-12-14 13:23:09 -0700897 group->grpcfg.flags.rdbufs_allowed = idxd->max_rdbufs;
Dave Jiangbfe1d562020-01-21 16:43:59 -0700898 }
899}
900
901static int idxd_engines_setup(struct idxd_device *idxd)
902{
903 int i, engines = 0;
904 struct idxd_engine *eng;
905 struct idxd_group *group;
906
907 for (i = 0; i < idxd->max_groups; i++) {
Dave Jiangdefe49f2021-04-15 16:37:51 -0700908 group = idxd->groups[i];
Dave Jiangbfe1d562020-01-21 16:43:59 -0700909 group->grpcfg.engines = 0;
910 }
911
912 for (i = 0; i < idxd->max_engines; i++) {
Dave Jiang75b91132021-04-15 16:37:44 -0700913 eng = idxd->engines[i];
Dave Jiangbfe1d562020-01-21 16:43:59 -0700914 group = eng->group;
915
916 if (!group)
917 continue;
918
919 group->grpcfg.engines |= BIT(eng->id);
920 engines++;
921 }
922
923 if (!engines)
924 return -EINVAL;
925
926 return 0;
927}
928
929static int idxd_wqs_setup(struct idxd_device *idxd)
930{
931 struct idxd_wq *wq;
932 struct idxd_group *group;
933 int i, j, configured = 0;
934 struct device *dev = &idxd->pdev->dev;
935
936 for (i = 0; i < idxd->max_groups; i++) {
Dave Jiangdefe49f2021-04-15 16:37:51 -0700937 group = idxd->groups[i];
Dave Jiangbfe1d562020-01-21 16:43:59 -0700938 for (j = 0; j < 4; j++)
939 group->grpcfg.wqs[j] = 0;
940 }
941
942 for (i = 0; i < idxd->max_wqs; i++) {
Dave Jiang7c5dd232021-04-15 16:37:39 -0700943 wq = idxd->wqs[i];
Dave Jiangbfe1d562020-01-21 16:43:59 -0700944 group = wq->group;
945
946 if (!wq->group)
947 continue;
Dave Jiangbfe1d562020-01-21 16:43:59 -0700948
Dave Jiang8e50d392020-10-27 10:34:35 -0700949 if (wq_shared(wq) && !device_swq_supported(idxd)) {
Dave Jiang125d10372021-07-20 13:42:15 -0700950 idxd->cmd_status = IDXD_SCMD_WQ_NO_SWQ_SUPPORT;
Dave Jiang8e50d392020-10-27 10:34:35 -0700951 dev_warn(dev, "No shared wq support but configured.\n");
Dave Jiangbfe1d562020-01-21 16:43:59 -0700952 return -EINVAL;
953 }
954
955 group->grpcfg.wqs[wq->id / 64] |= BIT(wq->id % 64);
956 configured++;
957 }
958
Dave Jiang125d10372021-07-20 13:42:15 -0700959 if (configured == 0) {
960 idxd->cmd_status = IDXD_SCMD_WQ_NONE_CONFIGURED;
Dave Jiangbfe1d562020-01-21 16:43:59 -0700961 return -EINVAL;
Dave Jiang125d10372021-07-20 13:42:15 -0700962 }
Dave Jiangbfe1d562020-01-21 16:43:59 -0700963
964 return 0;
965}
966
967int idxd_device_config(struct idxd_device *idxd)
968{
969 int rc;
970
971 lockdep_assert_held(&idxd->dev_lock);
972 rc = idxd_wqs_setup(idxd);
973 if (rc < 0)
974 return rc;
975
976 rc = idxd_engines_setup(idxd);
977 if (rc < 0)
978 return rc;
979
980 idxd_group_flags_setup(idxd);
981
982 rc = idxd_wqs_config_write(idxd);
983 if (rc < 0)
984 return rc;
985
986 rc = idxd_groups_config_write(idxd);
987 if (rc < 0)
988 return rc;
989
990 return 0;
991}
Dave Jiang8c66bbdc2021-04-20 11:46:28 -0700992
993static int idxd_wq_load_config(struct idxd_wq *wq)
994{
995 struct idxd_device *idxd = wq->idxd;
996 struct device *dev = &idxd->pdev->dev;
997 int wqcfg_offset;
998 int i;
999
1000 wqcfg_offset = WQCFG_OFFSET(idxd, wq->id, 0);
1001 memcpy_fromio(wq->wqcfg, idxd->reg_base + wqcfg_offset, idxd->wqcfg_size);
1002
1003 wq->size = wq->wqcfg->wq_size;
1004 wq->threshold = wq->wqcfg->wq_thresh;
Dave Jiang8c66bbdc2021-04-20 11:46:28 -07001005
1006 /* The driver does not support shared WQ mode in read-only config yet */
1007 if (wq->wqcfg->mode == 0 || wq->wqcfg->pasid_en)
1008 return -EOPNOTSUPP;
1009
1010 set_bit(WQ_FLAG_DEDICATED, &wq->flags);
1011
1012 wq->priority = wq->wqcfg->priority;
1013
1014 for (i = 0; i < WQCFG_STRIDES(idxd); i++) {
1015 wqcfg_offset = WQCFG_OFFSET(idxd, wq->id, i);
1016 dev_dbg(dev, "WQ[%d][%d][%#x]: %#x\n", wq->id, i, wqcfg_offset, wq->wqcfg->bits[i]);
1017 }
1018
1019 return 0;
1020}
1021
1022static void idxd_group_load_config(struct idxd_group *group)
1023{
1024 struct idxd_device *idxd = group->idxd;
1025 struct device *dev = &idxd->pdev->dev;
1026 int i, j, grpcfg_offset;
1027
1028 /*
1029 * Load WQS bit fields
1030 * Iterate through all 256 bits 64 bits at a time
1031 */
1032 for (i = 0; i < GRPWQCFG_STRIDES; i++) {
1033 struct idxd_wq *wq;
1034
1035 grpcfg_offset = GRPWQCFG_OFFSET(idxd, group->id, i);
1036 group->grpcfg.wqs[i] = ioread64(idxd->reg_base + grpcfg_offset);
1037 dev_dbg(dev, "GRPCFG wq[%d:%d: %#x]: %#llx\n",
1038 group->id, i, grpcfg_offset, group->grpcfg.wqs[i]);
1039
1040 if (i * 64 >= idxd->max_wqs)
1041 break;
1042
1043 /* Iterate through all 64 bits and check for wq set */
1044 for (j = 0; j < 64; j++) {
1045 int id = i * 64 + j;
1046
1047 /* No need to check beyond max wqs */
1048 if (id >= idxd->max_wqs)
1049 break;
1050
1051 /* Set group assignment for wq if wq bit is set */
1052 if (group->grpcfg.wqs[i] & BIT(j)) {
1053 wq = idxd->wqs[id];
1054 wq->group = group;
1055 }
1056 }
1057 }
1058
1059 grpcfg_offset = GRPENGCFG_OFFSET(idxd, group->id);
1060 group->grpcfg.engines = ioread64(idxd->reg_base + grpcfg_offset);
1061 dev_dbg(dev, "GRPCFG engs[%d: %#x]: %#llx\n", group->id,
1062 grpcfg_offset, group->grpcfg.engines);
1063
1064 /* Iterate through all 64 bits to check engines set */
1065 for (i = 0; i < 64; i++) {
1066 if (i >= idxd->max_engines)
1067 break;
1068
1069 if (group->grpcfg.engines & BIT(i)) {
1070 struct idxd_engine *engine = idxd->engines[i];
1071
1072 engine->group = group;
1073 }
1074 }
1075
1076 grpcfg_offset = GRPFLGCFG_OFFSET(idxd, group->id);
1077 group->grpcfg.flags.bits = ioread32(idxd->reg_base + grpcfg_offset);
1078 dev_dbg(dev, "GRPFLAGS flags[%d: %#x]: %#x\n",
1079 group->id, grpcfg_offset, group->grpcfg.flags.bits);
1080}
1081
1082int idxd_device_load_config(struct idxd_device *idxd)
1083{
1084 union gencfg_reg reg;
1085 int i, rc;
1086
1087 reg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET);
Dave Jiang7ed6f1b2021-12-14 13:23:09 -07001088 idxd->rdbuf_limit = reg.rdbuf_limit;
Dave Jiang8c66bbdc2021-04-20 11:46:28 -07001089
1090 for (i = 0; i < idxd->max_groups; i++) {
1091 struct idxd_group *group = idxd->groups[i];
1092
1093 idxd_group_load_config(group);
1094 }
1095
1096 for (i = 0; i < idxd->max_wqs; i++) {
1097 struct idxd_wq *wq = idxd->wqs[i];
1098
1099 rc = idxd_wq_load_config(wq);
1100 if (rc < 0)
1101 return rc;
1102 }
1103
1104 return 0;
1105}
Dave Jiang1f2bb402021-07-15 11:43:31 -07001106
Dave Jiang403a2e22021-12-13 11:51:34 -07001107static void idxd_flush_pending_descs(struct idxd_irq_entry *ie)
1108{
1109 struct idxd_desc *desc, *itr;
1110 struct llist_node *head;
1111 LIST_HEAD(flist);
1112 enum idxd_complete_type ctype;
1113
1114 spin_lock(&ie->list_lock);
1115 head = llist_del_all(&ie->pending_llist);
1116 if (head) {
1117 llist_for_each_entry_safe(desc, itr, head, llnode)
1118 list_add_tail(&desc->list, &ie->work_list);
1119 }
1120
1121 list_for_each_entry_safe(desc, itr, &ie->work_list, list)
1122 list_move_tail(&desc->list, &flist);
1123 spin_unlock(&ie->list_lock);
1124
1125 list_for_each_entry_safe(desc, itr, &flist, list) {
1126 list_del(&desc->list);
1127 ctype = desc->completion->status ? IDXD_COMPLETE_NORMAL : IDXD_COMPLETE_ABORT;
1128 idxd_dma_complete_txd(desc, ctype, true);
1129 }
1130}
1131
1132static void idxd_device_set_perm_entry(struct idxd_device *idxd,
1133 struct idxd_irq_entry *ie)
1134{
1135 union msix_perm mperm;
1136
1137 if (ie->pasid == INVALID_IOASID)
1138 return;
1139
1140 mperm.bits = 0;
1141 mperm.pasid = ie->pasid;
1142 mperm.pasid_en = 1;
1143 iowrite32(mperm.bits, idxd->reg_base + idxd->msix_perm_offset + ie->id * 8);
1144}
1145
1146static void idxd_device_clear_perm_entry(struct idxd_device *idxd,
1147 struct idxd_irq_entry *ie)
1148{
1149 iowrite32(0, idxd->reg_base + idxd->msix_perm_offset + ie->id * 8);
1150}
1151
1152void idxd_wq_free_irq(struct idxd_wq *wq)
1153{
1154 struct idxd_device *idxd = wq->idxd;
1155 struct idxd_irq_entry *ie = &wq->ie;
1156
1157 synchronize_irq(ie->vector);
1158 free_irq(ie->vector, ie);
1159 idxd_flush_pending_descs(ie);
1160 if (idxd->request_int_handles)
1161 idxd_device_release_int_handle(idxd, ie->int_handle, IDXD_IRQ_MSIX);
1162 idxd_device_clear_perm_entry(idxd, ie);
1163 ie->vector = -1;
1164 ie->int_handle = INVALID_INT_HANDLE;
1165 ie->pasid = INVALID_IOASID;
1166}
1167
1168int idxd_wq_request_irq(struct idxd_wq *wq)
1169{
1170 struct idxd_device *idxd = wq->idxd;
1171 struct pci_dev *pdev = idxd->pdev;
1172 struct device *dev = &pdev->dev;
1173 struct idxd_irq_entry *ie;
1174 int rc;
1175
1176 ie = &wq->ie;
1177 ie->vector = pci_irq_vector(pdev, ie->id);
1178 ie->pasid = device_pasid_enabled(idxd) ? idxd->pasid : INVALID_IOASID;
1179 idxd_device_set_perm_entry(idxd, ie);
1180
1181 rc = request_threaded_irq(ie->vector, NULL, idxd_wq_thread, 0, "idxd-portal", ie);
1182 if (rc < 0) {
1183 dev_err(dev, "Failed to request irq %d.\n", ie->vector);
1184 goto err_irq;
1185 }
1186
1187 if (idxd->request_int_handles) {
1188 rc = idxd_device_request_int_handle(idxd, ie->id, &ie->int_handle,
1189 IDXD_IRQ_MSIX);
1190 if (rc < 0)
1191 goto err_int_handle;
1192 } else {
1193 ie->int_handle = ie->id;
1194 }
1195
1196 return 0;
1197
1198err_int_handle:
1199 ie->int_handle = INVALID_INT_HANDLE;
1200 free_irq(ie->vector, ie);
1201err_irq:
1202 idxd_device_clear_perm_entry(idxd, ie);
1203 ie->pasid = INVALID_IOASID;
1204 return rc;
1205}
1206
Dave Jiang0cda4f62021-07-15 11:44:30 -07001207int __drv_enable_wq(struct idxd_wq *wq)
Dave Jiang1f2bb402021-07-15 11:43:31 -07001208{
1209 struct idxd_device *idxd = wq->idxd;
1210 struct device *dev = &idxd->pdev->dev;
Dave Jiang1f2bb402021-07-15 11:43:31 -07001211 int rc = -ENXIO;
1212
1213 lockdep_assert_held(&wq->wq_lock);
1214
Dave Jiang125d10372021-07-20 13:42:15 -07001215 if (idxd->state != IDXD_DEV_ENABLED) {
1216 idxd->cmd_status = IDXD_SCMD_DEV_NOT_ENABLED;
Dave Jiang1f2bb402021-07-15 11:43:31 -07001217 goto err;
Dave Jiang125d10372021-07-20 13:42:15 -07001218 }
Dave Jiang1f2bb402021-07-15 11:43:31 -07001219
1220 if (wq->state != IDXD_WQ_DISABLED) {
1221 dev_dbg(dev, "wq %d already enabled.\n", wq->id);
Dave Jiang125d10372021-07-20 13:42:15 -07001222 idxd->cmd_status = IDXD_SCMD_WQ_ENABLED;
Dave Jiang1f2bb402021-07-15 11:43:31 -07001223 rc = -EBUSY;
1224 goto err;
1225 }
1226
1227 if (!wq->group) {
1228 dev_dbg(dev, "wq %d not attached to group.\n", wq->id);
Dave Jiang125d10372021-07-20 13:42:15 -07001229 idxd->cmd_status = IDXD_SCMD_WQ_NO_GRP;
Dave Jiang1f2bb402021-07-15 11:43:31 -07001230 goto err;
1231 }
1232
1233 if (strlen(wq->name) == 0) {
Dave Jiang125d10372021-07-20 13:42:15 -07001234 idxd->cmd_status = IDXD_SCMD_WQ_NO_NAME;
Dave Jiang1f2bb402021-07-15 11:43:31 -07001235 dev_dbg(dev, "wq %d name not set.\n", wq->id);
1236 goto err;
1237 }
1238
1239 /* Shared WQ checks */
1240 if (wq_shared(wq)) {
1241 if (!device_swq_supported(idxd)) {
Dave Jiang125d10372021-07-20 13:42:15 -07001242 idxd->cmd_status = IDXD_SCMD_WQ_NO_SVM;
Dave Jiang1f2bb402021-07-15 11:43:31 -07001243 dev_dbg(dev, "PASID not enabled and shared wq.\n");
1244 goto err;
1245 }
1246 /*
1247 * Shared wq with the threshold set to 0 means the user
1248 * did not set the threshold or transitioned from a
1249 * dedicated wq but did not set threshold. A value
1250 * of 0 would effectively disable the shared wq. The
1251 * driver does not allow a value of 0 to be set for
1252 * threshold via sysfs.
1253 */
1254 if (wq->threshold == 0) {
Dave Jiang125d10372021-07-20 13:42:15 -07001255 idxd->cmd_status = IDXD_SCMD_WQ_NO_THRESH;
Dave Jiang1f2bb402021-07-15 11:43:31 -07001256 dev_dbg(dev, "Shared wq and threshold 0.\n");
1257 goto err;
1258 }
1259 }
1260
Dave Jiang0cda4f62021-07-15 11:44:30 -07001261 rc = 0;
Dave Jiangcf84a4b2021-08-24 14:24:27 -07001262 spin_lock(&idxd->dev_lock);
Dave Jiang1f2bb402021-07-15 11:43:31 -07001263 if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags))
1264 rc = idxd_device_config(idxd);
Dave Jiangcf84a4b2021-08-24 14:24:27 -07001265 spin_unlock(&idxd->dev_lock);
Dave Jiang1f2bb402021-07-15 11:43:31 -07001266 if (rc < 0) {
1267 dev_dbg(dev, "Writing wq %d config failed: %d\n", wq->id, rc);
1268 goto err;
1269 }
1270
1271 rc = idxd_wq_enable(wq);
1272 if (rc < 0) {
1273 dev_dbg(dev, "wq %d enabling failed: %d\n", wq->id, rc);
1274 goto err;
1275 }
1276
1277 rc = idxd_wq_map_portal(wq);
1278 if (rc < 0) {
Dave Jiang125d10372021-07-20 13:42:15 -07001279 idxd->cmd_status = IDXD_SCMD_WQ_PORTAL_ERR;
Dave Jiang1f2bb402021-07-15 11:43:31 -07001280 dev_dbg(dev, "wq %d portal mapping failed: %d\n", wq->id, rc);
1281 goto err_map_portal;
1282 }
1283
1284 wq->client_count = 0;
Dave Jiang1f2bb402021-07-15 11:43:31 -07001285 return 0;
1286
Dave Jiang1f2bb402021-07-15 11:43:31 -07001287err_map_portal:
1288 rc = idxd_wq_disable(wq, false);
1289 if (rc < 0)
1290 dev_dbg(dev, "wq %s disable failed\n", dev_name(wq_confdev(wq)));
1291err:
1292 return rc;
1293}
1294
1295int drv_enable_wq(struct idxd_wq *wq)
1296{
1297 int rc;
1298
1299 mutex_lock(&wq->wq_lock);
1300 rc = __drv_enable_wq(wq);
1301 mutex_unlock(&wq->wq_lock);
1302 return rc;
1303}
Dave Jiang69e4f8b2021-07-15 11:43:37 -07001304
Dave Jiang0cda4f62021-07-15 11:44:30 -07001305void __drv_disable_wq(struct idxd_wq *wq)
Dave Jiang69e4f8b2021-07-15 11:43:37 -07001306{
1307 struct idxd_device *idxd = wq->idxd;
1308 struct device *dev = &idxd->pdev->dev;
1309
1310 lockdep_assert_held(&wq->wq_lock);
1311
Dave Jiang69e4f8b2021-07-15 11:43:37 -07001312 if (idxd_wq_refcount(wq))
1313 dev_warn(dev, "Clients has claim on wq %d: %d\n",
1314 wq->id, idxd_wq_refcount(wq));
1315
1316 idxd_wq_unmap_portal(wq);
1317
1318 idxd_wq_drain(wq);
1319 idxd_wq_reset(wq);
1320
Dave Jiang69e4f8b2021-07-15 11:43:37 -07001321 wq->client_count = 0;
Dave Jiang69e4f8b2021-07-15 11:43:37 -07001322}
1323
1324void drv_disable_wq(struct idxd_wq *wq)
1325{
1326 mutex_lock(&wq->wq_lock);
1327 __drv_disable_wq(wq);
1328 mutex_unlock(&wq->wq_lock);
1329}
Dave Jiangbd428052021-07-15 11:44:01 -07001330
1331int idxd_device_drv_probe(struct idxd_dev *idxd_dev)
1332{
1333 struct idxd_device *idxd = idxd_dev_to_idxd(idxd_dev);
Dave Jiangbd428052021-07-15 11:44:01 -07001334 int rc = 0;
1335
1336 /*
1337 * Device should be in disabled state for the idxd_drv to load. If it's in
1338 * enabled state, then the device was altered outside of driver's control.
1339 * If the state is in halted state, then we don't want to proceed.
1340 */
Dave Jiang125d10372021-07-20 13:42:15 -07001341 if (idxd->state != IDXD_DEV_DISABLED) {
1342 idxd->cmd_status = IDXD_SCMD_DEV_ENABLED;
Dave Jiangbd428052021-07-15 11:44:01 -07001343 return -ENXIO;
Dave Jiang125d10372021-07-20 13:42:15 -07001344 }
Dave Jiangbd428052021-07-15 11:44:01 -07001345
1346 /* Device configuration */
Dave Jiangcf84a4b2021-08-24 14:24:27 -07001347 spin_lock(&idxd->dev_lock);
Dave Jiangbd428052021-07-15 11:44:01 -07001348 if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags))
1349 rc = idxd_device_config(idxd);
Dave Jiangcf84a4b2021-08-24 14:24:27 -07001350 spin_unlock(&idxd->dev_lock);
Dave Jiangbd428052021-07-15 11:44:01 -07001351 if (rc < 0)
1352 return -ENXIO;
1353
1354 /* Start device */
1355 rc = idxd_device_enable(idxd);
1356 if (rc < 0)
1357 return rc;
1358
1359 /* Setup DMA device without channels */
1360 rc = idxd_register_dma_device(idxd);
1361 if (rc < 0) {
1362 idxd_device_disable(idxd);
Dave Jiang125d10372021-07-20 13:42:15 -07001363 idxd->cmd_status = IDXD_SCMD_DEV_DMA_ERR;
Dave Jiangbd428052021-07-15 11:44:01 -07001364 return rc;
1365 }
1366
Dave Jiang125d10372021-07-20 13:42:15 -07001367 idxd->cmd_status = 0;
Dave Jiangbd428052021-07-15 11:44:01 -07001368 return 0;
1369}
Dave Jiang745e92a2021-07-15 11:44:07 -07001370
1371void idxd_device_drv_remove(struct idxd_dev *idxd_dev)
1372{
1373 struct device *dev = &idxd_dev->conf_dev;
1374 struct idxd_device *idxd = idxd_dev_to_idxd(idxd_dev);
1375 int i;
1376
1377 for (i = 0; i < idxd->max_wqs; i++) {
1378 struct idxd_wq *wq = idxd->wqs[i];
1379 struct device *wq_dev = wq_confdev(wq);
1380
1381 if (wq->state == IDXD_WQ_DISABLED)
1382 continue;
1383 dev_warn(dev, "Active wq %d on disable %s.\n", i, dev_name(wq_dev));
1384 device_release_driver(wq_dev);
1385 }
1386
1387 idxd_unregister_dma_device(idxd);
1388 idxd_device_disable(idxd);
1389 if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags))
1390 idxd_device_reset(idxd);
1391}
Dave Jiang034b3292021-07-15 11:44:24 -07001392
1393static enum idxd_dev_type dev_types[] = {
1394 IDXD_DEV_DSA,
1395 IDXD_DEV_IAX,
1396 IDXD_DEV_NONE,
1397};
1398
1399struct idxd_device_driver idxd_drv = {
1400 .type = dev_types,
1401 .probe = idxd_device_drv_probe,
1402 .remove = idxd_device_drv_remove,
1403 .name = "idxd",
1404};
Dave Jiang6e7f3ee92021-07-15 11:44:47 -07001405EXPORT_SYMBOL_GPL(idxd_drv);