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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / a254a9da455c171441ab3a76ed8f5d1e9412e15f / . / drivers / clk / mediatek / clk-mt7986-eth.c
blob: 495d023ccad7c64229c1b87573db764146ed7b08 [file] [log] [blame]
Sam Shihec97d232021-12-17 20:11:48 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Sam Shih <sam.shih@mediatek.com>
5 * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
6 */
7
8#include <linux/clk-provider.h>
9#include <linux/of.h>
10#include <linux/of_address.h>
11#include <linux/of_device.h>
12#include <linux/platform_device.h>
13
14#include "clk-mtk.h"
15#include "clk-gate.h"
16
17#include <dt-bindings/clock/mt7986-clk.h>
18
19static const struct mtk_gate_regs sgmii0_cg_regs = {
20 .set_ofs = 0xe4,
21 .clr_ofs = 0xe4,
22 .sta_ofs = 0xe4,
23};
24
25#define GATE_SGMII0(_id, _name, _parent, _shift) \
26 { \
27 .id = _id, .name = _name, .parent_name = _parent, \
28 .regs = &sgmii0_cg_regs, .shift = _shift, \
29 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
30 }
31
32static const struct mtk_gate sgmii0_clks[] __initconst = {
33 GATE_SGMII0(CLK_SGMII0_TX250M_EN, "sgmii0_tx250m_en", "top_xtal", 2),
34 GATE_SGMII0(CLK_SGMII0_RX250M_EN, "sgmii0_rx250m_en", "top_xtal", 3),
35 GATE_SGMII0(CLK_SGMII0_CDR_REF, "sgmii0_cdr_ref", "top_xtal", 4),
36 GATE_SGMII0(CLK_SGMII0_CDR_FB, "sgmii0_cdr_fb", "top_xtal", 5),
37};
38
39static const struct mtk_gate_regs sgmii1_cg_regs = {
40 .set_ofs = 0xe4,
41 .clr_ofs = 0xe4,
42 .sta_ofs = 0xe4,
43};
44
45#define GATE_SGMII1(_id, _name, _parent, _shift) \
46 { \
47 .id = _id, .name = _name, .parent_name = _parent, \
48 .regs = &sgmii1_cg_regs, .shift = _shift, \
49 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
50 }
51
52static const struct mtk_gate sgmii1_clks[] __initconst = {
53 GATE_SGMII1(CLK_SGMII1_TX250M_EN, "sgmii1_tx250m_en", "top_xtal", 2),
54 GATE_SGMII1(CLK_SGMII1_RX250M_EN, "sgmii1_rx250m_en", "top_xtal", 3),
55 GATE_SGMII1(CLK_SGMII1_CDR_REF, "sgmii1_cdr_ref", "top_xtal", 4),
56 GATE_SGMII1(CLK_SGMII1_CDR_FB, "sgmii1_cdr_fb", "top_xtal", 5),
57};
58
59static const struct mtk_gate_regs eth_cg_regs = {
60 .set_ofs = 0x30,
61 .clr_ofs = 0x30,
62 .sta_ofs = 0x30,
63};
64
65#define GATE_ETH(_id, _name, _parent, _shift) \
66 { \
67 .id = _id, .name = _name, .parent_name = _parent, \
68 .regs = &eth_cg_regs, .shift = _shift, \
69 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
70 }
71
72static const struct mtk_gate eth_clks[] __initconst = {
73 GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x_sel", 6),
74 GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m_sel", 7),
75 GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m_sel", 8),
76 GATE_ETH(CLK_ETH_WOCPU1_EN, "eth_wocpu1_en", "netsys_mcu_sel", 14),
77 GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_mcu_sel", 15),
78};
79
80static void __init mtk_sgmiisys_0_init(struct device_node *node)
81{
82 struct clk_onecell_data *clk_data;
83 int r;
84
85 clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks));
86
87 mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks),
88 clk_data);
89
90 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
91 if (r)
92 pr_err("%s(): could not register clock provider: %d\n",
93 __func__, r);
94}
95CLK_OF_DECLARE(mtk_sgmiisys_0, "mediatek,mt7986-sgmiisys_0",
96 mtk_sgmiisys_0_init);
97
98static void __init mtk_sgmiisys_1_init(struct device_node *node)
99{
100 struct clk_onecell_data *clk_data;
101 int r;
102
103 clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks));
104
105 mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks),
106 clk_data);
107
108 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
109
110 if (r)
111 pr_err("%s(): could not register clock provider: %d\n",
112 __func__, r);
113}
114CLK_OF_DECLARE(mtk_sgmiisys_1, "mediatek,mt7986-sgmiisys_1",
115 mtk_sgmiisys_1_init);
116
117static void __init mtk_ethsys_init(struct device_node *node)
118{
119 struct clk_onecell_data *clk_data;
120 int r;
121
122 clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks));
123
124 mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
125
126 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
127
128 if (r)
129 pr_err("%s(): could not register clock provider: %d\n",
130 __func__, r);
131}
132CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt7986-ethsys_ck", mtk_ethsys_init);