| Anson Huang | 8d99f03 | 2020-04-21 22:21:26 +0800 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/watchdog/fsl-imx7ulp-wdt.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Freescale i.MX7ULP Watchdog Timer (WDT) Controller |
| 8 | |
| 9 | maintainers: |
| 10 | - Anson Huang <Anson.Huang@nxp.com> |
| 11 | |
| 12 | allOf: |
| 13 | - $ref: "watchdog.yaml#" |
| 14 | |
| 15 | properties: |
| 16 | compatible: |
| Jacky Bai | 5c93481 | 2021-11-26 15:39:59 +0800 | [diff] [blame] | 17 | oneOf: |
| 18 | - const: fsl,imx7ulp-wdt |
| 19 | - items: |
| 20 | - const: fsl,imx8ulp-wdt |
| 21 | - const: fsl,imx7ulp-wdt |
| Anson Huang | 8d99f03 | 2020-04-21 22:21:26 +0800 | [diff] [blame] | 22 | |
| 23 | reg: |
| 24 | maxItems: 1 |
| 25 | |
| 26 | interrupts: |
| 27 | maxItems: 1 |
| 28 | |
| 29 | clocks: |
| 30 | maxItems: 1 |
| 31 | |
| 32 | assigned-clocks: |
| 33 | maxItems: 1 |
| 34 | |
| 35 | assigned-clocks-parents: |
| 36 | maxItems: 1 |
| 37 | |
| 38 | timeout-sec: true |
| 39 | |
| 40 | required: |
| 41 | - compatible |
| 42 | - interrupts |
| 43 | - reg |
| 44 | - clocks |
| 45 | |
| 46 | additionalProperties: false |
| 47 | |
| 48 | examples: |
| 49 | - | |
| 50 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 51 | #include <dt-bindings/clock/imx7ulp-clock.h> |
| 52 | |
| 53 | watchdog@403d0000 { |
| 54 | compatible = "fsl,imx7ulp-wdt"; |
| 55 | reg = <0x403d0000 0x10000>; |
| 56 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; |
| 57 | clocks = <&pcc2 IMX7ULP_CLK_WDG1>; |
| 58 | assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>; |
| 59 | assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; |
| 60 | timeout-sec = <40>; |
| 61 | }; |
| 62 | |
| 63 | ... |