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Geert Uytterhoeven384d00f2020-03-25 10:57:21 +01001# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: "http://devicetree.org/schemas/serial/renesas,sci.yaml#"
5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6
7title: Renesas Serial Communication Interface
8
9maintainers:
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11
12allOf:
13 - $ref: serial.yaml#
14
15properties:
16 compatible:
Lad Prabhakare1c0fc12021-11-10 23:29:19 +000017 oneOf:
18 - items:
19 - enum:
20 - renesas,r9a07g044-sci # RZ/G2{L,LC}
Biju Dasa359101c2021-12-21 09:47:08 +000021 - renesas,r9a07g054-sci # RZ/V2L
Lad Prabhakare1c0fc12021-11-10 23:29:19 +000022 - const: renesas,sci # generic SCI compatible UART
23
24 - items:
25 - const: renesas,sci # generic SCI compatible UART
Geert Uytterhoeven384d00f2020-03-25 10:57:21 +010026
27 reg:
28 maxItems: 1
29
30 interrupts:
31 items:
32 - description: Error interrupt
33 - description: Receive buffer full interrupt
34 - description: Transmit buffer empty interrupt
35 - description: Transmit end interrupt
36
37 interrupt-names:
38 items:
39 - const: eri
40 - const: rxi
41 - const: txi
42 - const: tei
43
44 clocks:
45 minItems: 1
46 maxItems: 2
47
48 clock-names:
49 minItems: 1
50 maxItems: 2
51 items:
52 enum:
53 - fck # UART functional clock
54 - sck # optional external clock input
55
56 uart-has-rtscts: false
57
58required:
59 - compatible
60 - reg
61 - interrupts
62 - clocks
63 - clock-names
64
Lad Prabhakare1c0fc12021-11-10 23:29:19 +000065if:
66 properties:
67 compatible:
68 contains:
69 enum:
70 - renesas,r9a07g044-sci
Biju Dasa359101c2021-12-21 09:47:08 +000071 - renesas,r9a07g054-sci
Lad Prabhakare1c0fc12021-11-10 23:29:19 +000072then:
73 properties:
74 resets:
75 maxItems: 1
76
77 power-domains:
78 maxItems: 1
79
80 required:
81 - resets
82 - power-domains
83
Rob Herring6fdc6e22020-10-05 13:38:27 -050084unevaluatedProperties: false
85
Geert Uytterhoeven384d00f2020-03-25 10:57:21 +010086examples:
87 - |
Lad Prabhakare1c0fc12021-11-10 23:29:19 +000088 #include <dt-bindings/clock/r9a07g044-cpg.h>
89 #include <dt-bindings/interrupt-controller/arm-gic.h>
90
Geert Uytterhoeven384d00f2020-03-25 10:57:21 +010091 aliases {
92 serial0 = &sci0;
93 };
94
Lad Prabhakare1c0fc12021-11-10 23:29:19 +000095 sci0: serial@1004d000 {
96 compatible = "renesas,r9a07g044-sci", "renesas,sci";
97 reg = <0x1004d000 0x400>;
98 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
99 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
100 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
101 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
102 interrupt-names = "eri", "rxi", "txi", "tei";
103 clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>;
Geert Uytterhoeven384d00f2020-03-25 10:57:21 +0100104 clock-names = "fck";
Lad Prabhakare1c0fc12021-11-10 23:29:19 +0000105 power-domains = <&cpg>;
106 resets = <&cpg R9A07G044_SCI0_RST>;
Geert Uytterhoeven384d00f2020-03-25 10:57:21 +0100107 };