blob: 2aa367c04a8ea63765fde3bfb9af160402fbb9f7 [file] [log] [blame]
Andrew Lunna2443fd2019-01-21 19:05:50 +01001// SPDX-License-Identifier: GPL-2.0+
Chaithrika U Sdbb7a952008-12-09 22:21:25 -08002/*
3 * drivers/net/phy/et1011c.c
4 *
5 * Driver for LSI ET1011C PHYs
6 *
7 * Author: Chaithrika U S
8 *
9 * Copyright (c) 2008 Texas Instruments
Chaithrika U Sdbb7a952008-12-09 22:21:25 -080010 */
11#include <linux/kernel.h>
12#include <linux/string.h>
13#include <linux/errno.h>
14#include <linux/unistd.h>
Chaithrika U Sdbb7a952008-12-09 22:21:25 -080015#include <linux/interrupt.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/netdevice.h>
19#include <linux/etherdevice.h>
20#include <linux/skbuff.h>
21#include <linux/spinlock.h>
22#include <linux/mm.h>
23#include <linux/module.h>
24#include <linux/mii.h>
25#include <linux/ethtool.h>
26#include <linux/phy.h>
27#include <linux/io.h>
28#include <linux/uaccess.h>
29#include <asm/irq.h>
30
31#define ET1011C_STATUS_REG (0x1A)
32#define ET1011C_CONFIG_REG (0x16)
33#define ET1011C_SPEED_MASK (0x0300)
34#define ET1011C_GIGABIT_SPEED (0x0200)
35#define ET1011C_TX_FIFO_MASK (0x3000)
36#define ET1011C_TX_FIFO_DEPTH_8 (0x0000)
37#define ET1011C_TX_FIFO_DEPTH_16 (0x1000)
38#define ET1011C_INTERFACE_MASK (0x0007)
39#define ET1011C_GMII_INTERFACE (0x0002)
40#define ET1011C_SYS_CLK_EN (0x01 << 4)
41
42
43MODULE_DESCRIPTION("LSI ET1011C PHY driver");
44MODULE_AUTHOR("Chaithrika U S");
45MODULE_LICENSE("GPL");
46
47static int et1011c_config_aneg(struct phy_device *phydev)
48{
49 int ctl = 0;
50 ctl = phy_read(phydev, MII_BMCR);
51 if (ctl < 0)
52 return ctl;
53 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 |
54 BMCR_ANENABLE);
55 /* First clear the PHY */
56 phy_write(phydev, MII_BMCR, ctl | BMCR_RESET);
57
58 return genphy_config_aneg(phydev);
59}
60
61static int et1011c_read_status(struct phy_device *phydev)
62{
63 int ret;
64 u32 val;
65 static int speed;
66 ret = genphy_read_status(phydev);
67
68 if (speed != phydev->speed) {
69 speed = phydev->speed;
70 val = phy_read(phydev, ET1011C_STATUS_REG);
71 if ((val & ET1011C_SPEED_MASK) ==
72 ET1011C_GIGABIT_SPEED) {
73 val = phy_read(phydev, ET1011C_CONFIG_REG);
74 val &= ~ET1011C_TX_FIFO_MASK;
75 phy_write(phydev, ET1011C_CONFIG_REG, val\
76 | ET1011C_GMII_INTERFACE\
77 | ET1011C_SYS_CLK_EN\
78 | ET1011C_TX_FIFO_DEPTH_16);
79
80 }
81 }
82 return ret;
83}
84
Johan Hovold116dffa2014-11-11 19:45:58 +010085static struct phy_driver et1011c_driver[] = { {
Chaithrika U Sdbb7a952008-12-09 22:21:25 -080086 .phy_id = 0x0282f014,
87 .name = "ET1011C",
88 .phy_id_mask = 0xfffffff0,
Andrew Lunn26eb00a4f2018-09-12 01:53:09 +020089 .features = PHY_GBIT_FEATURES,
Chaithrika U Sdbb7a952008-12-09 22:21:25 -080090 .config_aneg = et1011c_config_aneg,
91 .read_status = et1011c_read_status,
Johan Hovold116dffa2014-11-11 19:45:58 +010092} };
Chaithrika U Sdbb7a952008-12-09 22:21:25 -080093
Johan Hovold116dffa2014-11-11 19:45:58 +010094module_phy_driver(et1011c_driver);
David Woodhouse4e4f10f2010-04-02 01:05:56 +000095
Uwe Kleine-Königcf93c942010-10-03 23:43:32 +000096static struct mdio_device_id __maybe_unused et1011c_tbl[] = {
David Woodhouse4e4f10f2010-04-02 01:05:56 +000097 { 0x0282f014, 0xfffffff0 },
98 { }
99};
100
101MODULE_DEVICE_TABLE(mdio, et1011c_tbl);