Fabio Estevam | acd70ba | 2018-05-23 16:17:36 -0300 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | // |
| 3 | // Regulator Driver for Freescale MC13783 PMIC |
| 4 | // |
| 5 | // Copyright 2010 Yong Shen <yong.shen@linaro.org> |
| 6 | // Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> |
| 7 | // Copyright 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com> |
Sascha Hauer | 295c08b | 2009-08-19 01:43:50 +0200 | [diff] [blame] | 8 | |
Uwe Kleine-König | a10099b | 2009-11-10 09:18:07 +0100 | [diff] [blame] | 9 | #include <linux/mfd/mc13783.h> |
Sascha Hauer | 295c08b | 2009-08-19 01:43:50 +0200 | [diff] [blame] | 10 | #include <linux/regulator/machine.h> |
| 11 | #include <linux/regulator/driver.h> |
| 12 | #include <linux/platform_device.h> |
Sascha Hauer | 295c08b | 2009-08-19 01:43:50 +0200 | [diff] [blame] | 13 | #include <linux/kernel.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 14 | #include <linux/slab.h> |
Sascha Hauer | 295c08b | 2009-08-19 01:43:50 +0200 | [diff] [blame] | 15 | #include <linux/init.h> |
| 16 | #include <linux/err.h> |
Paul Gortmaker | 65602c3 | 2011-07-17 16:28:23 -0400 | [diff] [blame] | 17 | #include <linux/module.h> |
Yong Shen | 167e3d8 | 2010-12-14 14:00:54 +0800 | [diff] [blame] | 18 | #include "mc13xxx.h" |
Sascha Hauer | 295c08b | 2009-08-19 01:43:50 +0200 | [diff] [blame] | 19 | |
Gaëtan Carlier | ba02dfd | 2012-08-28 13:09:10 +0200 | [diff] [blame] | 20 | #define MC13783_REG_SWITCHERS0 24 |
| 21 | /* Enable does not exist for SW1A */ |
| 22 | #define MC13783_REG_SWITCHERS0_SW1AEN 0 |
| 23 | #define MC13783_REG_SWITCHERS0_SW1AVSEL 0 |
| 24 | #define MC13783_REG_SWITCHERS0_SW1AVSEL_M (63 << 0) |
| 25 | |
| 26 | #define MC13783_REG_SWITCHERS1 25 |
| 27 | /* Enable does not exist for SW1B */ |
| 28 | #define MC13783_REG_SWITCHERS1_SW1BEN 0 |
| 29 | #define MC13783_REG_SWITCHERS1_SW1BVSEL 0 |
| 30 | #define MC13783_REG_SWITCHERS1_SW1BVSEL_M (63 << 0) |
| 31 | |
| 32 | #define MC13783_REG_SWITCHERS2 26 |
| 33 | /* Enable does not exist for SW2A */ |
| 34 | #define MC13783_REG_SWITCHERS2_SW2AEN 0 |
| 35 | #define MC13783_REG_SWITCHERS2_SW2AVSEL 0 |
| 36 | #define MC13783_REG_SWITCHERS2_SW2AVSEL_M (63 << 0) |
| 37 | |
| 38 | #define MC13783_REG_SWITCHERS3 27 |
| 39 | /* Enable does not exist for SW2B */ |
| 40 | #define MC13783_REG_SWITCHERS3_SW2BEN 0 |
| 41 | #define MC13783_REG_SWITCHERS3_SW2BVSEL 0 |
| 42 | #define MC13783_REG_SWITCHERS3_SW2BVSEL_M (63 << 0) |
| 43 | |
Uwe Kleine-König | a10099b | 2009-11-10 09:18:07 +0100 | [diff] [blame] | 44 | #define MC13783_REG_SWITCHERS5 29 |
| 45 | #define MC13783_REG_SWITCHERS5_SW3EN (1 << 20) |
Alberto Panizzo | 1bd588f | 2009-12-14 18:26:38 +0100 | [diff] [blame] | 46 | #define MC13783_REG_SWITCHERS5_SW3VSEL 18 |
| 47 | #define MC13783_REG_SWITCHERS5_SW3VSEL_M (3 << 18) |
| 48 | |
| 49 | #define MC13783_REG_REGULATORSETTING0 30 |
| 50 | #define MC13783_REG_REGULATORSETTING0_VIOLOVSEL 2 |
| 51 | #define MC13783_REG_REGULATORSETTING0_VDIGVSEL 4 |
| 52 | #define MC13783_REG_REGULATORSETTING0_VGENVSEL 6 |
| 53 | #define MC13783_REG_REGULATORSETTING0_VRFDIGVSEL 9 |
| 54 | #define MC13783_REG_REGULATORSETTING0_VRFREFVSEL 11 |
| 55 | #define MC13783_REG_REGULATORSETTING0_VRFCPVSEL 13 |
| 56 | #define MC13783_REG_REGULATORSETTING0_VSIMVSEL 14 |
| 57 | #define MC13783_REG_REGULATORSETTING0_VESIMVSEL 15 |
| 58 | #define MC13783_REG_REGULATORSETTING0_VCAMVSEL 16 |
| 59 | |
| 60 | #define MC13783_REG_REGULATORSETTING0_VIOLOVSEL_M (3 << 2) |
| 61 | #define MC13783_REG_REGULATORSETTING0_VDIGVSEL_M (3 << 4) |
| 62 | #define MC13783_REG_REGULATORSETTING0_VGENVSEL_M (7 << 6) |
| 63 | #define MC13783_REG_REGULATORSETTING0_VRFDIGVSEL_M (3 << 9) |
| 64 | #define MC13783_REG_REGULATORSETTING0_VRFREFVSEL_M (3 << 11) |
| 65 | #define MC13783_REG_REGULATORSETTING0_VRFCPVSEL_M (1 << 13) |
| 66 | #define MC13783_REG_REGULATORSETTING0_VSIMVSEL_M (1 << 14) |
| 67 | #define MC13783_REG_REGULATORSETTING0_VESIMVSEL_M (1 << 15) |
| 68 | #define MC13783_REG_REGULATORSETTING0_VCAMVSEL_M (7 << 16) |
| 69 | |
| 70 | #define MC13783_REG_REGULATORSETTING1 31 |
| 71 | #define MC13783_REG_REGULATORSETTING1_VVIBVSEL 0 |
| 72 | #define MC13783_REG_REGULATORSETTING1_VRF1VSEL 2 |
| 73 | #define MC13783_REG_REGULATORSETTING1_VRF2VSEL 4 |
| 74 | #define MC13783_REG_REGULATORSETTING1_VMMC1VSEL 6 |
| 75 | #define MC13783_REG_REGULATORSETTING1_VMMC2VSEL 9 |
| 76 | |
| 77 | #define MC13783_REG_REGULATORSETTING1_VVIBVSEL_M (3 << 0) |
| 78 | #define MC13783_REG_REGULATORSETTING1_VRF1VSEL_M (3 << 2) |
| 79 | #define MC13783_REG_REGULATORSETTING1_VRF2VSEL_M (3 << 4) |
| 80 | #define MC13783_REG_REGULATORSETTING1_VMMC1VSEL_M (7 << 6) |
| 81 | #define MC13783_REG_REGULATORSETTING1_VMMC2VSEL_M (7 << 9) |
Uwe Kleine-König | a10099b | 2009-11-10 09:18:07 +0100 | [diff] [blame] | 82 | |
| 83 | #define MC13783_REG_REGULATORMODE0 32 |
| 84 | #define MC13783_REG_REGULATORMODE0_VAUDIOEN (1 << 0) |
| 85 | #define MC13783_REG_REGULATORMODE0_VIOHIEN (1 << 3) |
| 86 | #define MC13783_REG_REGULATORMODE0_VIOLOEN (1 << 6) |
| 87 | #define MC13783_REG_REGULATORMODE0_VDIGEN (1 << 9) |
| 88 | #define MC13783_REG_REGULATORMODE0_VGENEN (1 << 12) |
| 89 | #define MC13783_REG_REGULATORMODE0_VRFDIGEN (1 << 15) |
| 90 | #define MC13783_REG_REGULATORMODE0_VRFREFEN (1 << 18) |
| 91 | #define MC13783_REG_REGULATORMODE0_VRFCPEN (1 << 21) |
| 92 | |
| 93 | #define MC13783_REG_REGULATORMODE1 33 |
| 94 | #define MC13783_REG_REGULATORMODE1_VSIMEN (1 << 0) |
| 95 | #define MC13783_REG_REGULATORMODE1_VESIMEN (1 << 3) |
| 96 | #define MC13783_REG_REGULATORMODE1_VCAMEN (1 << 6) |
| 97 | #define MC13783_REG_REGULATORMODE1_VRFBGEN (1 << 9) |
| 98 | #define MC13783_REG_REGULATORMODE1_VVIBEN (1 << 11) |
| 99 | #define MC13783_REG_REGULATORMODE1_VRF1EN (1 << 12) |
| 100 | #define MC13783_REG_REGULATORMODE1_VRF2EN (1 << 15) |
| 101 | #define MC13783_REG_REGULATORMODE1_VMMC1EN (1 << 18) |
| 102 | #define MC13783_REG_REGULATORMODE1_VMMC2EN (1 << 21) |
| 103 | |
| 104 | #define MC13783_REG_POWERMISC 34 |
| 105 | #define MC13783_REG_POWERMISC_GPO1EN (1 << 6) |
| 106 | #define MC13783_REG_POWERMISC_GPO2EN (1 << 8) |
| 107 | #define MC13783_REG_POWERMISC_GPO3EN (1 << 10) |
| 108 | #define MC13783_REG_POWERMISC_GPO4EN (1 << 12) |
Alberto Panizzo | f4b97b3 | 2010-01-19 12:48:54 +0100 | [diff] [blame] | 109 | #define MC13783_REG_POWERMISC_PWGT1SPIEN (1 << 15) |
| 110 | #define MC13783_REG_POWERMISC_PWGT2SPIEN (1 << 16) |
| 111 | |
| 112 | #define MC13783_REG_POWERMISC_PWGTSPI_M (3 << 15) |
| 113 | |
Uwe Kleine-König | a10099b | 2009-11-10 09:18:07 +0100 | [diff] [blame] | 114 | |
Alberto Panizzo | 1bd588f | 2009-12-14 18:26:38 +0100 | [diff] [blame] | 115 | /* Voltage Values */ |
Gaëtan Carlier | ba02dfd | 2012-08-28 13:09:10 +0200 | [diff] [blame] | 116 | static const int mc13783_sw1x_val[] = { |
| 117 | 900000, 925000, 950000, 975000, |
| 118 | 1000000, 1025000, 1050000, 1075000, |
| 119 | 1100000, 1125000, 1150000, 1175000, |
| 120 | 1200000, 1225000, 1250000, 1275000, |
| 121 | 1300000, 1325000, 1350000, 1375000, |
| 122 | 1400000, 1425000, 1450000, 1475000, |
| 123 | 1500000, 1525000, 1550000, 1575000, |
| 124 | 1600000, 1625000, 1650000, 1675000, |
| 125 | 1700000, 1700000, 1700000, 1700000, |
| 126 | 1800000, 1800000, 1800000, 1800000, |
| 127 | 1850000, 1850000, 1850000, 1850000, |
| 128 | 2000000, 2000000, 2000000, 2000000, |
| 129 | 2100000, 2100000, 2100000, 2100000, |
| 130 | 2200000, 2200000, 2200000, 2200000, |
| 131 | 2200000, 2200000, 2200000, 2200000, |
| 132 | 2200000, 2200000, 2200000, 2200000, |
| 133 | }; |
| 134 | |
| 135 | static const int mc13783_sw2x_val[] = { |
| 136 | 900000, 925000, 950000, 975000, |
| 137 | 1000000, 1025000, 1050000, 1075000, |
| 138 | 1100000, 1125000, 1150000, 1175000, |
| 139 | 1200000, 1225000, 1250000, 1275000, |
| 140 | 1300000, 1325000, 1350000, 1375000, |
| 141 | 1400000, 1425000, 1450000, 1475000, |
| 142 | 1500000, 1525000, 1550000, 1575000, |
| 143 | 1600000, 1625000, 1650000, 1675000, |
| 144 | 1700000, 1700000, 1700000, 1700000, |
| 145 | 1800000, 1800000, 1800000, 1800000, |
| 146 | 1900000, 1900000, 1900000, 1900000, |
| 147 | 2000000, 2000000, 2000000, 2000000, |
| 148 | 2100000, 2100000, 2100000, 2100000, |
| 149 | 2200000, 2200000, 2200000, 2200000, |
| 150 | 2200000, 2200000, 2200000, 2200000, |
| 151 | 2200000, 2200000, 2200000, 2200000, |
| 152 | }; |
| 153 | |
Axel Lin | 34e74f3 | 2012-06-08 15:41:48 +0800 | [diff] [blame] | 154 | static const unsigned int mc13783_sw3_val[] = { |
Alberto Panizzo | 1bd588f | 2009-12-14 18:26:38 +0100 | [diff] [blame] | 155 | 5000000, 5000000, 5000000, 5500000, |
| 156 | }; |
| 157 | |
Axel Lin | 34e74f3 | 2012-06-08 15:41:48 +0800 | [diff] [blame] | 158 | static const unsigned int mc13783_vaudio_val[] = { |
Alberto Panizzo | 1bd588f | 2009-12-14 18:26:38 +0100 | [diff] [blame] | 159 | 2775000, |
| 160 | }; |
| 161 | |
Axel Lin | 34e74f3 | 2012-06-08 15:41:48 +0800 | [diff] [blame] | 162 | static const unsigned int mc13783_viohi_val[] = { |
Alberto Panizzo | 1bd588f | 2009-12-14 18:26:38 +0100 | [diff] [blame] | 163 | 2775000, |
| 164 | }; |
| 165 | |
Axel Lin | 34e74f3 | 2012-06-08 15:41:48 +0800 | [diff] [blame] | 166 | static const unsigned int mc13783_violo_val[] = { |
Alberto Panizzo | 1bd588f | 2009-12-14 18:26:38 +0100 | [diff] [blame] | 167 | 1200000, 1300000, 1500000, 1800000, |
| 168 | }; |
| 169 | |
Axel Lin | 34e74f3 | 2012-06-08 15:41:48 +0800 | [diff] [blame] | 170 | static const unsigned int mc13783_vdig_val[] = { |
Alberto Panizzo | 1bd588f | 2009-12-14 18:26:38 +0100 | [diff] [blame] | 171 | 1200000, 1300000, 1500000, 1800000, |
| 172 | }; |
| 173 | |
Axel Lin | 34e74f3 | 2012-06-08 15:41:48 +0800 | [diff] [blame] | 174 | static const unsigned int mc13783_vgen_val[] = { |
Alberto Panizzo | 1bd588f | 2009-12-14 18:26:38 +0100 | [diff] [blame] | 175 | 1200000, 1300000, 1500000, 1800000, |
| 176 | 1100000, 2000000, 2775000, 2400000, |
| 177 | }; |
| 178 | |
Axel Lin | 34e74f3 | 2012-06-08 15:41:48 +0800 | [diff] [blame] | 179 | static const unsigned int mc13783_vrfdig_val[] = { |
Alberto Panizzo | 1bd588f | 2009-12-14 18:26:38 +0100 | [diff] [blame] | 180 | 1200000, 1500000, 1800000, 1875000, |
| 181 | }; |
| 182 | |
Axel Lin | 34e74f3 | 2012-06-08 15:41:48 +0800 | [diff] [blame] | 183 | static const unsigned int mc13783_vrfref_val[] = { |
Alberto Panizzo | 1bd588f | 2009-12-14 18:26:38 +0100 | [diff] [blame] | 184 | 2475000, 2600000, 2700000, 2775000, |
| 185 | }; |
| 186 | |
Axel Lin | 34e74f3 | 2012-06-08 15:41:48 +0800 | [diff] [blame] | 187 | static const unsigned int mc13783_vrfcp_val[] = { |
Alberto Panizzo | 1bd588f | 2009-12-14 18:26:38 +0100 | [diff] [blame] | 188 | 2700000, 2775000, |
| 189 | }; |
| 190 | |
Axel Lin | 34e74f3 | 2012-06-08 15:41:48 +0800 | [diff] [blame] | 191 | static const unsigned int mc13783_vsim_val[] = { |
Alberto Panizzo | 1bd588f | 2009-12-14 18:26:38 +0100 | [diff] [blame] | 192 | 1800000, 2900000, 3000000, |
| 193 | }; |
| 194 | |
Axel Lin | 34e74f3 | 2012-06-08 15:41:48 +0800 | [diff] [blame] | 195 | static const unsigned int mc13783_vesim_val[] = { |
Alberto Panizzo | 1bd588f | 2009-12-14 18:26:38 +0100 | [diff] [blame] | 196 | 1800000, 2900000, |
| 197 | }; |
| 198 | |
Axel Lin | 34e74f3 | 2012-06-08 15:41:48 +0800 | [diff] [blame] | 199 | static const unsigned int mc13783_vcam_val[] = { |
Alberto Panizzo | 1bd588f | 2009-12-14 18:26:38 +0100 | [diff] [blame] | 200 | 1500000, 1800000, 2500000, 2550000, |
| 201 | 2600000, 2750000, 2800000, 3000000, |
| 202 | }; |
| 203 | |
Axel Lin | 34e74f3 | 2012-06-08 15:41:48 +0800 | [diff] [blame] | 204 | static const unsigned int mc13783_vrfbg_val[] = { |
Alberto Panizzo | 1bd588f | 2009-12-14 18:26:38 +0100 | [diff] [blame] | 205 | 1250000, |
| 206 | }; |
| 207 | |
Axel Lin | 34e74f3 | 2012-06-08 15:41:48 +0800 | [diff] [blame] | 208 | static const unsigned int mc13783_vvib_val[] = { |
Alberto Panizzo | 1bd588f | 2009-12-14 18:26:38 +0100 | [diff] [blame] | 209 | 1300000, 1800000, 2000000, 3000000, |
| 210 | }; |
| 211 | |
Axel Lin | 34e74f3 | 2012-06-08 15:41:48 +0800 | [diff] [blame] | 212 | static const unsigned int mc13783_vmmc_val[] = { |
Alberto Panizzo | 1bd588f | 2009-12-14 18:26:38 +0100 | [diff] [blame] | 213 | 1600000, 1800000, 2000000, 2600000, |
| 214 | 2700000, 2800000, 2900000, 3000000, |
| 215 | }; |
| 216 | |
Axel Lin | 34e74f3 | 2012-06-08 15:41:48 +0800 | [diff] [blame] | 217 | static const unsigned int mc13783_vrf_val[] = { |
Alberto Panizzo | 1bd588f | 2009-12-14 18:26:38 +0100 | [diff] [blame] | 218 | 1500000, 1875000, 2700000, 2775000, |
Sascha Hauer | 295c08b | 2009-08-19 01:43:50 +0200 | [diff] [blame] | 219 | }; |
| 220 | |
Axel Lin | 34e74f3 | 2012-06-08 15:41:48 +0800 | [diff] [blame] | 221 | static const unsigned int mc13783_gpo_val[] = { |
Alberto Panizzo | f4b97b3 | 2010-01-19 12:48:54 +0100 | [diff] [blame] | 222 | 3100000, |
| 223 | }; |
| 224 | |
Axel Lin | 34e74f3 | 2012-06-08 15:41:48 +0800 | [diff] [blame] | 225 | static const unsigned int mc13783_pwgtdrv_val[] = { |
Alberto Panizzo | f4b97b3 | 2010-01-19 12:48:54 +0100 | [diff] [blame] | 226 | 5500000, |
| 227 | }; |
| 228 | |
Axel Lin | e5680c4 | 2019-03-01 22:20:53 +0800 | [diff] [blame] | 229 | static const struct regulator_ops mc13783_gpo_regulator_ops; |
Sascha Hauer | 295c08b | 2009-08-19 01:43:50 +0200 | [diff] [blame] | 230 | |
Rob Herring | ec52091 | 2019-01-25 09:37:04 -0600 | [diff] [blame] | 231 | #define MC13783_DEFINE(prefix, name, node, reg, vsel_reg, voltages) \ |
| 232 | MC13xxx_DEFINE(MC13783_REG_, name, node, reg, vsel_reg, voltages, \ |
Yong Shen | 167e3d8 | 2010-12-14 14:00:54 +0800 | [diff] [blame] | 233 | mc13xxx_regulator_ops) |
Alberto Panizzo | 1bd588f | 2009-12-14 18:26:38 +0100 | [diff] [blame] | 234 | |
Rob Herring | ec52091 | 2019-01-25 09:37:04 -0600 | [diff] [blame] | 235 | #define MC13783_FIXED_DEFINE(prefix, name, node, reg, voltages) \ |
| 236 | MC13xxx_FIXED_DEFINE(MC13783_REG_, name, node, reg, voltages, \ |
Yong Shen | 167e3d8 | 2010-12-14 14:00:54 +0800 | [diff] [blame] | 237 | mc13xxx_fixed_regulator_ops) |
Alberto Panizzo | 1bd588f | 2009-12-14 18:26:38 +0100 | [diff] [blame] | 238 | |
Rob Herring | ec52091 | 2019-01-25 09:37:04 -0600 | [diff] [blame] | 239 | #define MC13783_GPO_DEFINE(prefix, name, node, reg, voltages) \ |
| 240 | MC13xxx_GPO_DEFINE(MC13783_REG_, name, node, reg, voltages, \ |
Yong Shen | 167e3d8 | 2010-12-14 14:00:54 +0800 | [diff] [blame] | 241 | mc13783_gpo_regulator_ops) |
Uwe Kleine-König | a10099b | 2009-11-10 09:18:07 +0100 | [diff] [blame] | 242 | |
Rob Herring | ec52091 | 2019-01-25 09:37:04 -0600 | [diff] [blame] | 243 | #define MC13783_DEFINE_SW(_name, _node, _reg, _vsel_reg, _voltages) \ |
| 244 | MC13783_DEFINE(REG, _name, _node, _reg, _vsel_reg, _voltages) |
| 245 | #define MC13783_DEFINE_REGU(_name, _node, _reg, _vsel_reg, _voltages) \ |
| 246 | MC13783_DEFINE(REG, _name, _node, _reg, _vsel_reg, _voltages) |
Uwe Kleine-König | a10099b | 2009-11-10 09:18:07 +0100 | [diff] [blame] | 247 | |
Yong Shen | 167e3d8 | 2010-12-14 14:00:54 +0800 | [diff] [blame] | 248 | static struct mc13xxx_regulator mc13783_regulators[] = { |
Rob Herring | ec52091 | 2019-01-25 09:37:04 -0600 | [diff] [blame] | 249 | MC13783_DEFINE_SW(SW1A, sw1a, SWITCHERS0, SWITCHERS0, mc13783_sw1x_val), |
| 250 | MC13783_DEFINE_SW(SW1B, sw1b, SWITCHERS1, SWITCHERS1, mc13783_sw1x_val), |
| 251 | MC13783_DEFINE_SW(SW2A, sw2a, SWITCHERS2, SWITCHERS2, mc13783_sw2x_val), |
| 252 | MC13783_DEFINE_SW(SW2B, sw2b, SWITCHERS3, SWITCHERS3, mc13783_sw2x_val), |
| 253 | MC13783_DEFINE_SW(SW3, sw3, SWITCHERS5, SWITCHERS5, mc13783_sw3_val), |
Uwe Kleine-König | a10099b | 2009-11-10 09:18:07 +0100 | [diff] [blame] | 254 | |
Rob Herring | ec52091 | 2019-01-25 09:37:04 -0600 | [diff] [blame] | 255 | MC13783_FIXED_DEFINE(REG, VAUDIO, vaudio, REGULATORMODE0, mc13783_vaudio_val), |
| 256 | MC13783_FIXED_DEFINE(REG, VIOHI, viohi, REGULATORMODE0, mc13783_viohi_val), |
| 257 | MC13783_DEFINE_REGU(VIOLO, violo, REGULATORMODE0, REGULATORSETTING0, |
Alberto Panizzo | 1bd588f | 2009-12-14 18:26:38 +0100 | [diff] [blame] | 258 | mc13783_violo_val), |
Rob Herring | ec52091 | 2019-01-25 09:37:04 -0600 | [diff] [blame] | 259 | MC13783_DEFINE_REGU(VDIG, vdig, REGULATORMODE0, REGULATORSETTING0, |
Alberto Panizzo | 1bd588f | 2009-12-14 18:26:38 +0100 | [diff] [blame] | 260 | mc13783_vdig_val), |
Rob Herring | ec52091 | 2019-01-25 09:37:04 -0600 | [diff] [blame] | 261 | MC13783_DEFINE_REGU(VGEN, vgen, REGULATORMODE0, REGULATORSETTING0, |
Alberto Panizzo | 1bd588f | 2009-12-14 18:26:38 +0100 | [diff] [blame] | 262 | mc13783_vgen_val), |
Rob Herring | ec52091 | 2019-01-25 09:37:04 -0600 | [diff] [blame] | 263 | MC13783_DEFINE_REGU(VRFDIG, vrfdig, REGULATORMODE0, REGULATORSETTING0, |
Alberto Panizzo | 1bd588f | 2009-12-14 18:26:38 +0100 | [diff] [blame] | 264 | mc13783_vrfdig_val), |
Rob Herring | ec52091 | 2019-01-25 09:37:04 -0600 | [diff] [blame] | 265 | MC13783_DEFINE_REGU(VRFREF, vrfref, REGULATORMODE0, REGULATORSETTING0, |
Alberto Panizzo | 1bd588f | 2009-12-14 18:26:38 +0100 | [diff] [blame] | 266 | mc13783_vrfref_val), |
Rob Herring | ec52091 | 2019-01-25 09:37:04 -0600 | [diff] [blame] | 267 | MC13783_DEFINE_REGU(VRFCP, vrfcp, REGULATORMODE0, REGULATORSETTING0, |
Alberto Panizzo | 1bd588f | 2009-12-14 18:26:38 +0100 | [diff] [blame] | 268 | mc13783_vrfcp_val), |
Rob Herring | ec52091 | 2019-01-25 09:37:04 -0600 | [diff] [blame] | 269 | MC13783_DEFINE_REGU(VSIM, vsim, REGULATORMODE1, REGULATORSETTING0, |
Alberto Panizzo | 1bd588f | 2009-12-14 18:26:38 +0100 | [diff] [blame] | 270 | mc13783_vsim_val), |
Rob Herring | ec52091 | 2019-01-25 09:37:04 -0600 | [diff] [blame] | 271 | MC13783_DEFINE_REGU(VESIM, vesim, REGULATORMODE1, REGULATORSETTING0, |
Alberto Panizzo | 1bd588f | 2009-12-14 18:26:38 +0100 | [diff] [blame] | 272 | mc13783_vesim_val), |
Rob Herring | ec52091 | 2019-01-25 09:37:04 -0600 | [diff] [blame] | 273 | MC13783_DEFINE_REGU(VCAM, vcam, REGULATORMODE1, REGULATORSETTING0, |
Alberto Panizzo | 1bd588f | 2009-12-14 18:26:38 +0100 | [diff] [blame] | 274 | mc13783_vcam_val), |
Rob Herring | ec52091 | 2019-01-25 09:37:04 -0600 | [diff] [blame] | 275 | MC13783_FIXED_DEFINE(REG, VRFBG, vrfbg, REGULATORMODE1, mc13783_vrfbg_val), |
| 276 | MC13783_DEFINE_REGU(VVIB, vvib, REGULATORMODE1, REGULATORSETTING1, |
Alberto Panizzo | 1bd588f | 2009-12-14 18:26:38 +0100 | [diff] [blame] | 277 | mc13783_vvib_val), |
Rob Herring | ec52091 | 2019-01-25 09:37:04 -0600 | [diff] [blame] | 278 | MC13783_DEFINE_REGU(VRF1, vrf1, REGULATORMODE1, REGULATORSETTING1, |
Alberto Panizzo | 1bd588f | 2009-12-14 18:26:38 +0100 | [diff] [blame] | 279 | mc13783_vrf_val), |
Rob Herring | ec52091 | 2019-01-25 09:37:04 -0600 | [diff] [blame] | 280 | MC13783_DEFINE_REGU(VRF2, vrf2, REGULATORMODE1, REGULATORSETTING1, |
Alberto Panizzo | 1bd588f | 2009-12-14 18:26:38 +0100 | [diff] [blame] | 281 | mc13783_vrf_val), |
Rob Herring | ec52091 | 2019-01-25 09:37:04 -0600 | [diff] [blame] | 282 | MC13783_DEFINE_REGU(VMMC1, vmmc1, REGULATORMODE1, REGULATORSETTING1, |
Alberto Panizzo | 1bd588f | 2009-12-14 18:26:38 +0100 | [diff] [blame] | 283 | mc13783_vmmc_val), |
Rob Herring | ec52091 | 2019-01-25 09:37:04 -0600 | [diff] [blame] | 284 | MC13783_DEFINE_REGU(VMMC2, vmmc2, REGULATORMODE1, REGULATORSETTING1, |
Alberto Panizzo | 1bd588f | 2009-12-14 18:26:38 +0100 | [diff] [blame] | 285 | mc13783_vmmc_val), |
Rob Herring | ec52091 | 2019-01-25 09:37:04 -0600 | [diff] [blame] | 286 | MC13783_GPO_DEFINE(REG, GPO1, gpo1, POWERMISC, mc13783_gpo_val), |
| 287 | MC13783_GPO_DEFINE(REG, GPO2, gpo1, POWERMISC, mc13783_gpo_val), |
| 288 | MC13783_GPO_DEFINE(REG, GPO3, gpo1, POWERMISC, mc13783_gpo_val), |
| 289 | MC13783_GPO_DEFINE(REG, GPO4, gpo1, POWERMISC, mc13783_gpo_val), |
| 290 | MC13783_GPO_DEFINE(REG, PWGT1SPI, pwgt1spi, POWERMISC, mc13783_pwgtdrv_val), |
| 291 | MC13783_GPO_DEFINE(REG, PWGT2SPI, pwgt2spi, POWERMISC, mc13783_pwgtdrv_val), |
Sascha Hauer | 295c08b | 2009-08-19 01:43:50 +0200 | [diff] [blame] | 292 | }; |
| 293 | |
Yong Shen | 167e3d8 | 2010-12-14 14:00:54 +0800 | [diff] [blame] | 294 | static int mc13783_powermisc_rmw(struct mc13xxx_regulator_priv *priv, u32 mask, |
| 295 | u32 val) |
Sascha Hauer | 295c08b | 2009-08-19 01:43:50 +0200 | [diff] [blame] | 296 | { |
Yong Shen | 167e3d8 | 2010-12-14 14:00:54 +0800 | [diff] [blame] | 297 | struct mc13xxx *mc13783 = priv->mc13xxx; |
Alberto Panizzo | f4b97b3 | 2010-01-19 12:48:54 +0100 | [diff] [blame] | 298 | int ret; |
| 299 | u32 valread; |
| 300 | |
| 301 | BUG_ON(val & ~mask); |
| 302 | |
Axel Lin | 2a2c3ac | 2012-07-19 11:16:06 +0800 | [diff] [blame] | 303 | mc13xxx_lock(priv->mc13xxx); |
Yong Shen | 167e3d8 | 2010-12-14 14:00:54 +0800 | [diff] [blame] | 304 | ret = mc13xxx_reg_read(mc13783, MC13783_REG_POWERMISC, &valread); |
Alberto Panizzo | f4b97b3 | 2010-01-19 12:48:54 +0100 | [diff] [blame] | 305 | if (ret) |
Axel Lin | 2a2c3ac | 2012-07-19 11:16:06 +0800 | [diff] [blame] | 306 | goto out; |
Alberto Panizzo | f4b97b3 | 2010-01-19 12:48:54 +0100 | [diff] [blame] | 307 | |
| 308 | /* Update the stored state for Power Gates. */ |
| 309 | priv->powermisc_pwgt_state = |
| 310 | (priv->powermisc_pwgt_state & ~mask) | val; |
| 311 | priv->powermisc_pwgt_state &= MC13783_REG_POWERMISC_PWGTSPI_M; |
| 312 | |
| 313 | /* Construct the new register value */ |
| 314 | valread = (valread & ~mask) | val; |
| 315 | /* Overwrite the PWGTxEN with the stored version */ |
| 316 | valread = (valread & ~MC13783_REG_POWERMISC_PWGTSPI_M) | |
| 317 | priv->powermisc_pwgt_state; |
| 318 | |
Axel Lin | 2a2c3ac | 2012-07-19 11:16:06 +0800 | [diff] [blame] | 319 | ret = mc13xxx_reg_write(mc13783, MC13783_REG_POWERMISC, valread); |
| 320 | out: |
| 321 | mc13xxx_unlock(priv->mc13xxx); |
| 322 | return ret; |
Alberto Panizzo | f4b97b3 | 2010-01-19 12:48:54 +0100 | [diff] [blame] | 323 | } |
| 324 | |
| 325 | static int mc13783_gpo_regulator_enable(struct regulator_dev *rdev) |
| 326 | { |
Yong Shen | 167e3d8 | 2010-12-14 14:00:54 +0800 | [diff] [blame] | 327 | struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev); |
| 328 | struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators; |
Alberto Panizzo | f4b97b3 | 2010-01-19 12:48:54 +0100 | [diff] [blame] | 329 | int id = rdev_get_id(rdev); |
Yong Shen | 167e3d8 | 2010-12-14 14:00:54 +0800 | [diff] [blame] | 330 | u32 en_val = mc13xxx_regulators[id].enable_bit; |
Alberto Panizzo | f4b97b3 | 2010-01-19 12:48:54 +0100 | [diff] [blame] | 331 | |
| 332 | dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id); |
| 333 | |
| 334 | /* Power Gate enable value is 0 */ |
Yong Shen | 57c78e3 | 2010-12-14 14:00:53 +0800 | [diff] [blame] | 335 | if (id == MC13783_REG_PWGT1SPI || |
| 336 | id == MC13783_REG_PWGT2SPI) |
Alberto Panizzo | f4b97b3 | 2010-01-19 12:48:54 +0100 | [diff] [blame] | 337 | en_val = 0; |
| 338 | |
Axel Lin | 2a2c3ac | 2012-07-19 11:16:06 +0800 | [diff] [blame] | 339 | return mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit, |
Alberto Panizzo | f4b97b3 | 2010-01-19 12:48:54 +0100 | [diff] [blame] | 340 | en_val); |
Alberto Panizzo | f4b97b3 | 2010-01-19 12:48:54 +0100 | [diff] [blame] | 341 | } |
| 342 | |
| 343 | static int mc13783_gpo_regulator_disable(struct regulator_dev *rdev) |
| 344 | { |
Yong Shen | 167e3d8 | 2010-12-14 14:00:54 +0800 | [diff] [blame] | 345 | struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev); |
| 346 | struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators; |
Alberto Panizzo | f4b97b3 | 2010-01-19 12:48:54 +0100 | [diff] [blame] | 347 | int id = rdev_get_id(rdev); |
Alberto Panizzo | f4b97b3 | 2010-01-19 12:48:54 +0100 | [diff] [blame] | 348 | u32 dis_val = 0; |
| 349 | |
| 350 | dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id); |
| 351 | |
| 352 | /* Power Gate disable value is 1 */ |
Yong Shen | 57c78e3 | 2010-12-14 14:00:53 +0800 | [diff] [blame] | 353 | if (id == MC13783_REG_PWGT1SPI || |
| 354 | id == MC13783_REG_PWGT2SPI) |
Yong Shen | 167e3d8 | 2010-12-14 14:00:54 +0800 | [diff] [blame] | 355 | dis_val = mc13xxx_regulators[id].enable_bit; |
Alberto Panizzo | f4b97b3 | 2010-01-19 12:48:54 +0100 | [diff] [blame] | 356 | |
Axel Lin | 2a2c3ac | 2012-07-19 11:16:06 +0800 | [diff] [blame] | 357 | return mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit, |
Alberto Panizzo | f4b97b3 | 2010-01-19 12:48:54 +0100 | [diff] [blame] | 358 | dis_val); |
Alberto Panizzo | f4b97b3 | 2010-01-19 12:48:54 +0100 | [diff] [blame] | 359 | } |
| 360 | |
| 361 | static int mc13783_gpo_regulator_is_enabled(struct regulator_dev *rdev) |
| 362 | { |
Yong Shen | 167e3d8 | 2010-12-14 14:00:54 +0800 | [diff] [blame] | 363 | struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev); |
| 364 | struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators; |
Alberto Panizzo | f4b97b3 | 2010-01-19 12:48:54 +0100 | [diff] [blame] | 365 | int ret, id = rdev_get_id(rdev); |
| 366 | unsigned int val; |
| 367 | |
Yong Shen | 167e3d8 | 2010-12-14 14:00:54 +0800 | [diff] [blame] | 368 | mc13xxx_lock(priv->mc13xxx); |
| 369 | ret = mc13xxx_reg_read(priv->mc13xxx, mc13xxx_regulators[id].reg, &val); |
| 370 | mc13xxx_unlock(priv->mc13xxx); |
Alberto Panizzo | f4b97b3 | 2010-01-19 12:48:54 +0100 | [diff] [blame] | 371 | |
| 372 | if (ret) |
| 373 | return ret; |
| 374 | |
| 375 | /* Power Gates state is stored in powermisc_pwgt_state |
| 376 | * where the meaning of bits is negated */ |
| 377 | val = (val & ~MC13783_REG_POWERMISC_PWGTSPI_M) | |
| 378 | (priv->powermisc_pwgt_state ^ MC13783_REG_POWERMISC_PWGTSPI_M); |
| 379 | |
Yong Shen | 167e3d8 | 2010-12-14 14:00:54 +0800 | [diff] [blame] | 380 | return (val & mc13xxx_regulators[id].enable_bit) != 0; |
Alberto Panizzo | f4b97b3 | 2010-01-19 12:48:54 +0100 | [diff] [blame] | 381 | } |
| 382 | |
Axel Lin | e5680c4 | 2019-03-01 22:20:53 +0800 | [diff] [blame] | 383 | static const struct regulator_ops mc13783_gpo_regulator_ops = { |
Alberto Panizzo | f4b97b3 | 2010-01-19 12:48:54 +0100 | [diff] [blame] | 384 | .enable = mc13783_gpo_regulator_enable, |
| 385 | .disable = mc13783_gpo_regulator_disable, |
| 386 | .is_enabled = mc13783_gpo_regulator_is_enabled, |
Axel Lin | 34e74f3 | 2012-06-08 15:41:48 +0800 | [diff] [blame] | 387 | .list_voltage = regulator_list_voltage_table, |
Yong Shen | 167e3d8 | 2010-12-14 14:00:54 +0800 | [diff] [blame] | 388 | .set_voltage = mc13xxx_fixed_regulator_set_voltage, |
Alberto Panizzo | f4b97b3 | 2010-01-19 12:48:54 +0100 | [diff] [blame] | 389 | }; |
| 390 | |
Bill Pemberton | a502357 | 2012-11-19 13:22:22 -0500 | [diff] [blame] | 391 | static int mc13783_regulator_probe(struct platform_device *pdev) |
Sascha Hauer | 295c08b | 2009-08-19 01:43:50 +0200 | [diff] [blame] | 392 | { |
Yong Shen | 167e3d8 | 2010-12-14 14:00:54 +0800 | [diff] [blame] | 393 | struct mc13xxx_regulator_priv *priv; |
| 394 | struct mc13xxx *mc13783 = dev_get_drvdata(pdev->dev.parent); |
Samuel Ortiz | 8f1585a | 2011-09-19 11:33:17 +0200 | [diff] [blame] | 395 | struct mc13xxx_regulator_platform_data *pdata = |
Samuel Ortiz | c8a03c9 | 2011-04-08 01:55:01 +0200 | [diff] [blame] | 396 | dev_get_platdata(&pdev->dev); |
Alexander Shiyan | 86b139f | 2013-04-27 10:29:25 +0400 | [diff] [blame] | 397 | struct mc13xxx_regulator_init_data *mc13xxx_data; |
Axel Lin | a9d5801 | 2012-04-10 13:51:06 +0800 | [diff] [blame] | 398 | struct regulator_config config = { }; |
Sachin Kamat | 8e56863 | 2013-09-04 12:00:59 +0530 | [diff] [blame] | 399 | int i, num_regulators; |
Sascha Hauer | 295c08b | 2009-08-19 01:43:50 +0200 | [diff] [blame] | 400 | |
Alexander Shiyan | 86b139f | 2013-04-27 10:29:25 +0400 | [diff] [blame] | 401 | num_regulators = mc13xxx_get_num_regulators_dt(pdev); |
Sascha Hauer | 295c08b | 2009-08-19 01:43:50 +0200 | [diff] [blame] | 402 | |
Alexander Shiyan | 86b139f | 2013-04-27 10:29:25 +0400 | [diff] [blame] | 403 | if (num_regulators <= 0 && pdata) |
| 404 | num_regulators = pdata->num_regulators; |
| 405 | if (num_regulators <= 0) |
Sascha Hauer | 0757b60 | 2012-02-29 09:01:40 +0100 | [diff] [blame] | 406 | return -EINVAL; |
| 407 | |
Kees Cook | 0ed2dd0 | 2018-05-08 16:08:53 -0700 | [diff] [blame] | 408 | priv = devm_kzalloc(&pdev->dev, |
| 409 | struct_size(priv, regulators, num_regulators), |
| 410 | GFP_KERNEL); |
Sascha Hauer | 295c08b | 2009-08-19 01:43:50 +0200 | [diff] [blame] | 411 | if (!priv) |
| 412 | return -ENOMEM; |
| 413 | |
Alexander Shiyan | 86b139f | 2013-04-27 10:29:25 +0400 | [diff] [blame] | 414 | priv->num_regulators = num_regulators; |
Yong Shen | 167e3d8 | 2010-12-14 14:00:54 +0800 | [diff] [blame] | 415 | priv->mc13xxx_regulators = mc13783_regulators; |
| 416 | priv->mc13xxx = mc13783; |
Alexander Shiyan | 86b139f | 2013-04-27 10:29:25 +0400 | [diff] [blame] | 417 | platform_set_drvdata(pdev, priv); |
Sascha Hauer | 295c08b | 2009-08-19 01:43:50 +0200 | [diff] [blame] | 418 | |
Alexander Shiyan | 86b139f | 2013-04-27 10:29:25 +0400 | [diff] [blame] | 419 | mc13xxx_data = mc13xxx_parse_regulators_dt(pdev, mc13783_regulators, |
| 420 | ARRAY_SIZE(mc13783_regulators)); |
| 421 | |
| 422 | for (i = 0; i < priv->num_regulators; i++) { |
| 423 | struct regulator_init_data *init_data; |
Axel Lin | a9d5801 | 2012-04-10 13:51:06 +0800 | [diff] [blame] | 424 | struct regulator_desc *desc; |
Alexander Shiyan | 86b139f | 2013-04-27 10:29:25 +0400 | [diff] [blame] | 425 | struct device_node *node = NULL; |
| 426 | int id; |
Sascha Hauer | 295c08b | 2009-08-19 01:43:50 +0200 | [diff] [blame] | 427 | |
Alexander Shiyan | 86b139f | 2013-04-27 10:29:25 +0400 | [diff] [blame] | 428 | if (mc13xxx_data) { |
| 429 | id = mc13xxx_data[i].id; |
| 430 | init_data = mc13xxx_data[i].init_data; |
| 431 | node = mc13xxx_data[i].node; |
| 432 | } else { |
| 433 | id = pdata->regulators[i].id; |
| 434 | init_data = pdata->regulators[i].init_data; |
| 435 | } |
| 436 | desc = &mc13783_regulators[id].desc; |
Axel Lin | a9d5801 | 2012-04-10 13:51:06 +0800 | [diff] [blame] | 437 | |
| 438 | config.dev = &pdev->dev; |
Alexander Shiyan | 86b139f | 2013-04-27 10:29:25 +0400 | [diff] [blame] | 439 | config.init_data = init_data; |
Axel Lin | a9d5801 | 2012-04-10 13:51:06 +0800 | [diff] [blame] | 440 | config.driver_data = priv; |
Alexander Shiyan | 86b139f | 2013-04-27 10:29:25 +0400 | [diff] [blame] | 441 | config.of_node = node; |
Axel Lin | a9d5801 | 2012-04-10 13:51:06 +0800 | [diff] [blame] | 442 | |
Sachin Kamat | 8e56863 | 2013-09-04 12:00:59 +0530 | [diff] [blame] | 443 | priv->regulators[i] = devm_regulator_register(&pdev->dev, desc, |
| 444 | &config); |
Sascha Hauer | 295c08b | 2009-08-19 01:43:50 +0200 | [diff] [blame] | 445 | if (IS_ERR(priv->regulators[i])) { |
| 446 | dev_err(&pdev->dev, "failed to register regulator %s\n", |
| 447 | mc13783_regulators[i].desc.name); |
Sachin Kamat | 8e56863 | 2013-09-04 12:00:59 +0530 | [diff] [blame] | 448 | return PTR_ERR(priv->regulators[i]); |
Sascha Hauer | 295c08b | 2009-08-19 01:43:50 +0200 | [diff] [blame] | 449 | } |
| 450 | } |
| 451 | |
Sascha Hauer | 295c08b | 2009-08-19 01:43:50 +0200 | [diff] [blame] | 452 | return 0; |
Sascha Hauer | 295c08b | 2009-08-19 01:43:50 +0200 | [diff] [blame] | 453 | } |
| 454 | |
| 455 | static struct platform_driver mc13783_regulator_driver = { |
| 456 | .driver = { |
| 457 | .name = "mc13783-regulator", |
Sascha Hauer | 295c08b | 2009-08-19 01:43:50 +0200 | [diff] [blame] | 458 | }, |
Alberto Panizzo | 735eb93 | 2009-12-14 18:53:35 +0100 | [diff] [blame] | 459 | .probe = mc13783_regulator_probe, |
Sascha Hauer | 295c08b | 2009-08-19 01:43:50 +0200 | [diff] [blame] | 460 | }; |
| 461 | |
| 462 | static int __init mc13783_regulator_init(void) |
| 463 | { |
Alberto Panizzo | 735eb93 | 2009-12-14 18:53:35 +0100 | [diff] [blame] | 464 | return platform_driver_register(&mc13783_regulator_driver); |
Sascha Hauer | 295c08b | 2009-08-19 01:43:50 +0200 | [diff] [blame] | 465 | } |
| 466 | subsys_initcall(mc13783_regulator_init); |
| 467 | |
| 468 | static void __exit mc13783_regulator_exit(void) |
| 469 | { |
| 470 | platform_driver_unregister(&mc13783_regulator_driver); |
| 471 | } |
| 472 | module_exit(mc13783_regulator_exit); |
| 473 | |
Uwe Kleine-König | a10099b | 2009-11-10 09:18:07 +0100 | [diff] [blame] | 474 | MODULE_LICENSE("GPL v2"); |
Axel Lin | 1dcc434 | 2010-05-06 11:33:36 +0800 | [diff] [blame] | 475 | MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); |
Sascha Hauer | 295c08b | 2009-08-19 01:43:50 +0200 | [diff] [blame] | 476 | MODULE_DESCRIPTION("Regulator Driver for Freescale MC13783 PMIC"); |
| 477 | MODULE_ALIAS("platform:mc13783-regulator"); |