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Thomas Gleixner8d36fe12019-06-01 10:08:35 +02001// SPDX-License-Identifier: GPL-2.0-only
Andrew Lunn5dc17fa2017-04-12 17:34:31 +02002/*
3 * mchp23k256.c
4 *
5 * Driver for Microchip 23k256 SPI RAM chips
6 *
7 * Copyright © 2016 Andrew Lunn <andrew@lunn.ch>
Andrew Lunn5dc17fa2017-04-12 17:34:31 +02008 */
9#include <linux/device.h>
10#include <linux/module.h>
11#include <linux/mtd/mtd.h>
12#include <linux/mtd/partitions.h>
13#include <linux/mutex.h>
14#include <linux/sched.h>
15#include <linux/sizes.h>
16#include <linux/spi/flash.h>
17#include <linux/spi/spi.h>
Chris Packham4db4d35e2017-05-25 11:49:12 +120018#include <linux/of_device.h>
Andrew Lunn5dc17fa2017-04-12 17:34:31 +020019
Chris Packham43790752017-06-02 15:21:19 +120020#define MAX_CMD_SIZE 4
21
22struct mchp23_caps {
23 u8 addr_width;
24 unsigned int size;
25};
26
Andrew Lunn5dc17fa2017-04-12 17:34:31 +020027struct mchp23k256_flash {
28 struct spi_device *spi;
29 struct mutex lock;
30 struct mtd_info mtd;
Chris Packham43790752017-06-02 15:21:19 +120031 const struct mchp23_caps *caps;
Andrew Lunn5dc17fa2017-04-12 17:34:31 +020032};
33
34#define MCHP23K256_CMD_WRITE_STATUS 0x01
35#define MCHP23K256_CMD_WRITE 0x02
36#define MCHP23K256_CMD_READ 0x03
37#define MCHP23K256_MODE_SEQ BIT(6)
38
39#define to_mchp23k256_flash(x) container_of(x, struct mchp23k256_flash, mtd)
40
Chris Packham43790752017-06-02 15:21:19 +120041static void mchp23k256_addr2cmd(struct mchp23k256_flash *flash,
42 unsigned int addr, u8 *cmd)
43{
44 int i;
45
46 /*
47 * Address is sent in big endian (MSB first) and we skip
48 * the first entry of the cmd array which contains the cmd
49 * opcode.
50 */
51 for (i = flash->caps->addr_width; i > 0; i--, addr >>= 8)
52 cmd[i] = addr;
53}
54
55static int mchp23k256_cmdsz(struct mchp23k256_flash *flash)
56{
57 return 1 + flash->caps->addr_width;
58}
59
Andrew Lunn5dc17fa2017-04-12 17:34:31 +020060static int mchp23k256_write(struct mtd_info *mtd, loff_t to, size_t len,
61 size_t *retlen, const unsigned char *buf)
62{
63 struct mchp23k256_flash *flash = to_mchp23k256_flash(mtd);
64 struct spi_transfer transfer[2] = {};
65 struct spi_message message;
Chris Packham43790752017-06-02 15:21:19 +120066 unsigned char command[MAX_CMD_SIZE];
Antonio Borneodb601f32017-12-10 16:19:56 +010067 int ret;
Andrew Lunn5dc17fa2017-04-12 17:34:31 +020068
69 spi_message_init(&message);
70
71 command[0] = MCHP23K256_CMD_WRITE;
Chris Packham43790752017-06-02 15:21:19 +120072 mchp23k256_addr2cmd(flash, to, command);
Andrew Lunn5dc17fa2017-04-12 17:34:31 +020073
74 transfer[0].tx_buf = command;
Chris Packham43790752017-06-02 15:21:19 +120075 transfer[0].len = mchp23k256_cmdsz(flash);
Andrew Lunn5dc17fa2017-04-12 17:34:31 +020076 spi_message_add_tail(&transfer[0], &message);
77
78 transfer[1].tx_buf = buf;
79 transfer[1].len = len;
80 spi_message_add_tail(&transfer[1], &message);
81
82 mutex_lock(&flash->lock);
83
Antonio Borneodb601f32017-12-10 16:19:56 +010084 ret = spi_sync(flash->spi, &message);
85
86 mutex_unlock(&flash->lock);
87
88 if (ret)
89 return ret;
Andrew Lunn5dc17fa2017-04-12 17:34:31 +020090
91 if (retlen && message.actual_length > sizeof(command))
92 *retlen += message.actual_length - sizeof(command);
93
Andrew Lunn5dc17fa2017-04-12 17:34:31 +020094 return 0;
95}
96
97static int mchp23k256_read(struct mtd_info *mtd, loff_t from, size_t len,
98 size_t *retlen, unsigned char *buf)
99{
100 struct mchp23k256_flash *flash = to_mchp23k256_flash(mtd);
101 struct spi_transfer transfer[2] = {};
102 struct spi_message message;
Chris Packham43790752017-06-02 15:21:19 +1200103 unsigned char command[MAX_CMD_SIZE];
Antonio Borneodb601f32017-12-10 16:19:56 +0100104 int ret;
Andrew Lunn5dc17fa2017-04-12 17:34:31 +0200105
106 spi_message_init(&message);
107
108 memset(&transfer, 0, sizeof(transfer));
109 command[0] = MCHP23K256_CMD_READ;
Chris Packham43790752017-06-02 15:21:19 +1200110 mchp23k256_addr2cmd(flash, from, command);
Andrew Lunn5dc17fa2017-04-12 17:34:31 +0200111
112 transfer[0].tx_buf = command;
Chris Packham43790752017-06-02 15:21:19 +1200113 transfer[0].len = mchp23k256_cmdsz(flash);
Andrew Lunn5dc17fa2017-04-12 17:34:31 +0200114 spi_message_add_tail(&transfer[0], &message);
115
116 transfer[1].rx_buf = buf;
117 transfer[1].len = len;
118 spi_message_add_tail(&transfer[1], &message);
119
120 mutex_lock(&flash->lock);
121
Antonio Borneodb601f32017-12-10 16:19:56 +0100122 ret = spi_sync(flash->spi, &message);
123
124 mutex_unlock(&flash->lock);
125
126 if (ret)
127 return ret;
Andrew Lunn5dc17fa2017-04-12 17:34:31 +0200128
129 if (retlen && message.actual_length > sizeof(command))
130 *retlen += message.actual_length - sizeof(command);
131
Andrew Lunn5dc17fa2017-04-12 17:34:31 +0200132 return 0;
133}
134
135/*
136 * Set the device into sequential mode. This allows read/writes to the
137 * entire SRAM in a single operation
138 */
139static int mchp23k256_set_mode(struct spi_device *spi)
140{
141 struct spi_transfer transfer = {};
142 struct spi_message message;
143 unsigned char command[2];
144
145 spi_message_init(&message);
146
147 command[0] = MCHP23K256_CMD_WRITE_STATUS;
148 command[1] = MCHP23K256_MODE_SEQ;
149
150 transfer.tx_buf = command;
151 transfer.len = sizeof(command);
152 spi_message_add_tail(&transfer, &message);
153
154 return spi_sync(spi, &message);
155}
156
Chris Packham43790752017-06-02 15:21:19 +1200157static const struct mchp23_caps mchp23k256_caps = {
158 .size = SZ_32K,
159 .addr_width = 2,
160};
161
162static const struct mchp23_caps mchp23lcv1024_caps = {
163 .size = SZ_128K,
164 .addr_width = 3,
165};
166
Andrew Lunn5dc17fa2017-04-12 17:34:31 +0200167static int mchp23k256_probe(struct spi_device *spi)
168{
169 struct mchp23k256_flash *flash;
170 struct flash_platform_data *data;
171 int err;
172
173 flash = devm_kzalloc(&spi->dev, sizeof(*flash), GFP_KERNEL);
174 if (!flash)
175 return -ENOMEM;
176
177 flash->spi = spi;
178 mutex_init(&flash->lock);
179 spi_set_drvdata(spi, flash);
180
181 err = mchp23k256_set_mode(spi);
182 if (err)
183 return err;
184
185 data = dev_get_platdata(&spi->dev);
186
Chris Packham43790752017-06-02 15:21:19 +1200187 flash->caps = of_device_get_match_data(&spi->dev);
188 if (!flash->caps)
189 flash->caps = &mchp23k256_caps;
190
Chris Packham2f071ff2017-06-02 15:21:18 +1200191 mtd_set_of_node(&flash->mtd, spi->dev.of_node);
Andrew Lunn5dc17fa2017-04-12 17:34:31 +0200192 flash->mtd.dev.parent = &spi->dev;
193 flash->mtd.type = MTD_RAM;
194 flash->mtd.flags = MTD_CAP_RAM;
195 flash->mtd.writesize = 1;
Chris Packham43790752017-06-02 15:21:19 +1200196 flash->mtd.size = flash->caps->size;
Andrew Lunn5dc17fa2017-04-12 17:34:31 +0200197 flash->mtd._read = mchp23k256_read;
198 flash->mtd._write = mchp23k256_write;
199
Chris Packham44225c92017-05-25 11:49:13 +1200200 err = mtd_device_register(&flash->mtd, data ? data->parts : NULL,
201 data ? data->nr_parts : 0);
Andrew Lunn5dc17fa2017-04-12 17:34:31 +0200202 if (err)
203 return err;
204
205 return 0;
206}
207
208static int mchp23k256_remove(struct spi_device *spi)
209{
210 struct mchp23k256_flash *flash = spi_get_drvdata(spi);
211
212 return mtd_device_unregister(&flash->mtd);
213}
214
Chris Packham4db4d35e2017-05-25 11:49:12 +1200215static const struct of_device_id mchp23k256_of_table[] = {
Chris Packham43790752017-06-02 15:21:19 +1200216 {
217 .compatible = "microchip,mchp23k256",
218 .data = &mchp23k256_caps,
219 },
220 {
221 .compatible = "microchip,mchp23lcv1024",
222 .data = &mchp23lcv1024_caps,
223 },
Chris Packham4db4d35e2017-05-25 11:49:12 +1200224 {}
225};
226MODULE_DEVICE_TABLE(of, mchp23k256_of_table);
227
Andrew Lunn5dc17fa2017-04-12 17:34:31 +0200228static struct spi_driver mchp23k256_driver = {
229 .driver = {
230 .name = "mchp23k256",
Chris Packham4db4d35e2017-05-25 11:49:12 +1200231 .of_match_table = of_match_ptr(mchp23k256_of_table),
Andrew Lunn5dc17fa2017-04-12 17:34:31 +0200232 },
233 .probe = mchp23k256_probe,
234 .remove = mchp23k256_remove,
235};
236
237module_spi_driver(mchp23k256_driver);
238
239MODULE_DESCRIPTION("MTD SPI driver for MCHP23K256 RAM chips");
240MODULE_AUTHOR("Andrew Lunn <andre@lunn.ch>");
241MODULE_LICENSE("GPL v2");
242MODULE_ALIAS("spi:mchp23k256");