blob: daf76345b179886e99ceebfaad98b2b6b90f3ce1 [file] [log] [blame]
Markus Niebelef384622021-11-22 12:37:40 +01001// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright 2013 Sascha Hauer, Pengutronix
4 *
5 * Copyright 2013-2021 TQ-Systems GmbH
6 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
7 */
8
9#include <dt-bindings/clock/imx6qdl-clock.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/input/input.h>
12#include <dt-bindings/sound/fsl-imx-audmux.h>
13
14/ {
15 aliases {
16 mmc0 = &usdhc3;
17 mmc1 = &usdhc2;
18 /delete-property/ mmc2;
19 /delete-property/ mmc3;
20 };
21
22 chosen {
23 stdout-path = &uart2;
24 };
25
26 beeper: gpio-beeper {
27 compatible = "gpio-beeper";
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_gpiobeeper>;
30 gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
31 };
32
33 gpio_buttons: gpio-buttons {
34 compatible = "gpio-keys";
35 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_gpiobuttons>;
37
38 button1 {
39 label = "s6";
40 linux,code = <KEY_F6>;
41 gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
42 };
43
44 button2 {
45 label = "s7";
46 linux,code = <KEY_F7>;
47 gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
48 };
49
50 button3 {
51 label = "s8";
52 linux,code = <KEY_F8>;
53 gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
54 };
55 };
56
57 gpio-leds {
58 compatible = "gpio-leds";
59 pinctrl-names = "default";
60 pinctrl-0 = <&pinctrl_gpioled>;
61
62 led1 {
63 label = "led1";
64 gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
65 linux,default-trigger = "default-on";
66 };
67
68 led2 {
69 label = "led2";
70 gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>;
71 linux,default-trigger = "heartbeat";
72 };
73 };
74
75 reg_mba6_3p3v: regulator-mba6-3p3v {
76 compatible = "regulator-fixed";
77 regulator-name = "supply-mba6-3p3v";
78 regulator-min-microvolt = <3300000>;
79 regulator-max-microvolt = <3300000>;
80 regulator-always-on;
81 };
82
83 reg_pcie: regulator-pcie {
84 compatible = "regulator-fixed";
85 regulator-name = "supply-pcie";
86 regulator-min-microvolt = <3300000>;
87 regulator-max-microvolt = <3300000>;
88 /* PCIE.PWR_EN */
89 gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>;
90 enable-active-high;
91 regulator-always-on;
92 vin-supply = <&reg_mba6_3p3v>;
93 };
94
95 reg_vcc3v3_audio: regulator-vcc3v3-audio {
96 compatible = "regulator-fixed";
97 regulator-name = "vcc3v3-audio";
98 regulator-min-microvolt = <3300000>;
99 regulator-max-microvolt = <3300000>;
100 vin-supply = <&reg_mba6_3p3v>;
101 };
102
103 sound {
104 compatible = "fsl,imx-audio-tlv320aic32x4";
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_audmux>;
107 model = "imx-audio-tlv320aic32x4";
108 ssi-controller = <&ssi1>;
109 audio-codec = <&tlv320aic32x4>;
110 audio-asrc = <&asrc>;
111 audio-routing =
112 "IN3_L", "Mic Jack",
113 "Mic Jack", "Mic Bias",
114 "IN1_L", "Line In Jack",
115 "IN1_R", "Line In Jack",
116 "Line Out Jack", "LOL",
117 "Line Out Jack", "LOR";
118 mux-int-port = <1>;
119 mux-ext-port = <3>;
120 };
121};
122
123&audmux {
124 status = "okay";
125
126 ssi0 {
127 fsl,audmux-port = <MX31_AUDMUX_PORT1_SSI0>;
128 fsl,port-config = <
129 (IMX_AUDMUX_V2_PTCR_SYN |
130 IMX_AUDMUX_V2_PTCR_TFSDIR |
131 IMX_AUDMUX_V2_PTCR_TFSEL(MX31_AUDMUX_PORT3_SSI_PINS_3) |
132 IMX_AUDMUX_V2_PTCR_TCLKDIR |
133 IMX_AUDMUX_V2_PTCR_TCSEL(MX31_AUDMUX_PORT3_SSI_PINS_3))
134 IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT3_SSI_PINS_3)
135 >;
136 };
137
138 aud3 {
139 fsl,audmux-port = <MX31_AUDMUX_PORT3_SSI_PINS_3>;
140 fsl,port-config = <
141 IMX_AUDMUX_V2_PTCR_SYN
142 IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT1_SSI0)
143 >;
144 };
145};
146
147&can1 {
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_can1>;
150 status = "okay";
151};
152
153&can2 {
154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_can2>;
156 status = "okay";
157};
158
159&ecspi1 {
160 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_mba6>;
162 cs-gpios = <&gpio3 19 0>, <&gpio3 24 0>;
163};
164
165&fec {
166 phy-mode = "rgmii-id";
167 phy-handle = <&ethphy>;
168 mac-address = [00 00 00 00 00 00];
169 status = "okay";
170
171 mdio {
172 #address-cells = <1>;
173 #size-cells = <0>;
174
175 ethphy: ethernet-phy@3 {
176 compatible = "ethernet-phy-ieee802.3-c22";
177 reg = <3>;
178 interrupt-parent = <&gpio1>;
179 interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
180 reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
181 reset-assert-us = <1000>;
182 reset-deassert-us = <100000>;
183 micrel,force-master;
184 max-speed = <1000>;
185 };
186 };
187};
188
189&i2c1 {
190 tlv320aic32x4: audio-codec@18 {
191 compatible = "ti,tlv320aic32x4";
192 reg = <0x18>;
193 clocks = <&clks IMX6QDL_CLK_CKO>;
194 clock-names = "mclk";
195 pinctrl-names = "default";
196 pinctrl-0 = <&pinctrl_codec>;
197 ldoin-supply = <&reg_vcc3v3_audio>;
198 iov-supply = <&reg_mba6_3p3v>;
199 };
200};
201
202&pcie {
203 pinctrl-names = "default";
204 pinctrl-0 = <&pinctrl_pcie>;
205 reset-gpio = <&gpio6 7 GPIO_ACTIVE_LOW>;
206 status = "okay";
207};
208
209&pwm1 {
210 pinctrl-names = "default";
211 pinctrl-0 = <&pinctrl_pwm1>;
212 status = "okay";
213};
214
215&pwm3 {
216 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_pwm3>;
218 status = "okay";
219};
220
221&pwm4 {
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_pwm4>;
224 status = "okay";
225};
226
227&snvs_poweroff {
228 status = "okay";
229};
230
231&ssi1 {
232 status = "okay";
233};
234
235&uart2 {
236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_uart2>;
238 status = "okay";
239};
240
241
242&uart3 {
243 pinctrl-names = "default";
244 pinctrl-0 = <&pinctrl_uart3>;
245 uart-has-rtscts;
246 status = "okay";
247};
248
249&uart4 {
250 pinctrl-names = "default";
251 pinctrl-0 = <&pinctrl_uart4>;
252 uart-has-rtscts;
253 linux,rs485-enabled-at-boot-time;
254 rs485-rts-active-low;
255 rs485-rx-during-tx;
256 status = "okay";
257};
258
259&uart5 {
260 pinctrl-names = "default";
261 pinctrl-0 = <&pinctrl_uart5>;
262 uart-has-rtscts;
263 status = "okay";
264};
265
266&usbh1 {
267 disable-over-current;
268 status = "okay";
269};
270
271&usbotg {
272 pinctrl-names = "default";
273 pinctrl-0 = <&pinctrl_usbotg>;
274 power-active-high;
275 over-current-active-low;
276 srp-disable;
277 hnp-disable;
278 adp-disable;
279 dr_mode = "otg";
280 status = "okay";
281};
282
283/* SD card slot */
284&usdhc2 {
285 pinctrl-names = "default";
286 pinctrl-0 = <&pinctrl_usdhc2>;
287 vmmc-supply = <&reg_mba6_3p3v>;
288 bus-width = <4>;
289 no-1-8-v;
290 no-mmc;
291 no-sdio;
292 cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
293 wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
294 status = "okay";
295};
296
297&wdog1 {
298 pinctrl-names = "default";
299 pinctrl-0 = <&pinctrl_wdog1>;
300 /* does not work on unmodified starter kit */
301 /* fsl,ext-reset-output; */
302 status = "okay";
303};
304
305&iomuxc {
306 pinctrl-names = "default";
307 pinctrl-0 = <&pinctrl_hog>;
308
309 pinctrl_audmux: audmuxgrp {
310 fsl,pins = <
311 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0
312 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0
313 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0
314 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0
315 >;
316 };
317
318 pinctrl_can1: can1grp {
319 fsl,pins = <
320 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0xb099
321 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0xb099
322 >;
323 };
324
325 pinctrl_can2: can2grp {
326 fsl,pins = <
327 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0xb099
328 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0xb099
329 >;
330 };
331
332 pinctrl_codec: codecgrp {
333 fsl,pins = <
334 MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0xb0 /* CLK */
335 >;
336 };
337
338 pinctrl_ecspi1_mba6: ecspimba6grp {
339 fsl,pins = <
340 MX6QDL_PAD_EIM_D24__GPIO3_IO24 0xb099 /* eCSPI1 SS2 */
341 >;
342 };
343
344 pinctrl_enet: enetgrp {
345 fsl,pins = <
346 /* FEC phy IRQ */
347 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x00011008
348 /* FEC phy reset */
349 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b099
350 /* DSE = 100, 100k up, SPEED = MED */
351 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0xb0a0
352 MX6QDL_PAD_ENET_MDC__ENET_MDC 0xb0a0
353 /* DSE = 111, pull 100k up */
354 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0xb038
355 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0xb038
356 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0xb038
357 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0xb038
358 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0xb038
359 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0xb038
360 /* DSE = 111, pull external */
361 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x0038
362 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x0038
363 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x0038
364 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x0038
365 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x0038
366 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x0038
367 /* HYS = 1, DSE = 111, 100k up, SPEED = HIGH */
368 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0f0
369 >;
370 };
371
372 pinctrl_gpiobeeper: gpiobeepergrp {
373 fsl,pins = <
374 MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0xb099
375 >;
376 };
377
378 pinctrl_gpiobuttons: gpiobuttongrp {
379 fsl,pins = <
380 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0001b099
381 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b099
382 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b099
383 >;
384 };
385
386 pinctrl_gpioled: gpioledgrp {
387 fsl,pins = <
388 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0xb099 /* LED V15 */
389 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb099 /* LED V16 */
390 >;
391 };
392
393 pinctrl_hog: hoggrp {
394 fsl,pins = <
395 /* LCD.CONTRAST -> Rev 0100 only, not used on Rev.0200*/
396 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0001b099
397
398 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b099
399 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b099
400 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x0001b099
401
402 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b099
403 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0001b099
404 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0001b099
405 MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0001b099
406 MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0001b099
407 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0001b099
408 MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x0001b099
409
410 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0001b099
411 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0001b099
412 MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0001b099
413 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0001b099
414 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0001b099
415
416 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b099
417 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b099
418 MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b099
419 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x0001b099
420
421 MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x0001b099
422 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x0001b099
423 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x0001b099
424
425 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b099
426 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x0001b099
427 >;
428 };
429
430 pinctrl_pcie: pciegrp {
431 fsl,pins = <
432 /* HYS = 1, DSE = 110, 100k up, SPEED = HIGH (11)*/
433 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x001b0f0 /* #PCIE.WAKE */
434 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x001b0f0 /* #PCIE.RST */
435 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x001b0f0 /* #PCIE.DIS */
436 /* HYS = 1, DSE = 110, PUE+PKE, SPEED = HIGH (11)*/
437 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00130f0 /* PCIE.PWR_EN */
438 >;
439 };
440
441 pinctrl_pwm1: pwm1grp {
442 fsl,pins = <
443 /* 100 k PD, DSE 120 OHM, SPPEED LO */
444 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x00003050
445 >;
446 };
447
448 pinctrl_pwm3: pwm3grp {
449 fsl,pins = <
450 /* 100 k PD, DSE 120 OHM, SPPEED LO */
451 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x00003050
452 >;
453 };
454
455 pinctrl_pwm4: pwm4grp {
456 fsl,pins = <
457 /* 100 k PD, DSE 120 OHM, SPPEED LO */
458 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x00003050
459 >;
460 };
461
462 pinctrl_uart2: uart2grp {
463 fsl,pins = <
464 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b099
465 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b099
466 >;
467 };
468
469 pinctrl_uart3: uart3grp {
470 fsl,pins = <
471 MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
472 MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
473 MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
474 MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
475 >;
476 };
477
478 pinctrl_uart4: uart4grp {
479 fsl,pins = <
480 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
481 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
482 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
483 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
484 >;
485 };
486
487 pinctrl_uart5: uart5grp {
488 fsl,pins = <
489 MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
490 MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
491 MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1
492 MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x1b0b1
493 >;
494 };
495
496 pinctrl_usdhc2: usdhc2grp {
497 fsl,pins = <
498 /* CLK: 47k Pup SPD_LOW DSE 40Ohm SRE_FAST HYS */
499 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00017071
500 /* SD2: 47k Pup SPD_LOW DSE 80Ohm SRE_FAST HYS */
501 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017059
502 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017059
503 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017059
504 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017059
505 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017059
506
507 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b099 /* usdhc2 CD */
508 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0001b099 /* usdhc2 WP */
509 >;
510 };
511
512 pinctrl_usbotg: usbotggrp {
513 fsl,pins = <
514 MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0001b0b0
515 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x00017059
516 MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x0001b099
517 >;
518 };
519
520 pinctrl_wdog1: wdog1grp {
521 fsl,pins = <
522 /* Watchdog out */
523 MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x0000b099
524 >;
525 };
526};