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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 9bc657b28eba22e36efcdf3afa08100f92971eb4 / . / arch / sparc64 / kernel / tsb.S
blob: e1dd37f5e53515d4b73fc785efda36aea342448a [file] [log] [blame]
David S. Miller74bf4312006-01-31 18:29:18 -0800[diff] [blame]1/* tsb.S: Sparc64 TSB table handling.
2 *
3 * Copyright (C) 2006 David S. Miller <davem@davemloft.net>
4 */
5
6#include <asm/tsb.h>
7
8 .text
9 .align 32
10
11 /* Invoked from TLB miss handler, we are in the
12 * MMU global registers and they are setup like
13 * this:
14 *
15 * %g1: TSB entry pointer
16 * %g2: available temporary
17 * %g3: FAULT_CODE_{D,I}TLB
18 * %g4: available temporary
19 * %g5: available temporary
20 * %g6: TAG TARGET
21 * %g7: physical address base of the linux page
22 * tables for the current address space
23 */
24 .globl tsb_miss_dtlb
25tsb_miss_dtlb:
26 mov TLB_TAG_ACCESS, %g4
27 ldxa [%g4] ASI_DMMU, %g4
28 ba,pt %xcc, tsb_miss_page_table_walk
29 nop
30
31 .globl tsb_miss_itlb
32tsb_miss_itlb:
33 mov TLB_TAG_ACCESS, %g4
34 ldxa [%g4] ASI_IMMU, %g4
35 ba,pt %xcc, tsb_miss_page_table_walk
36 nop
37
38tsb_miss_page_table_walk:
David S. Miller56fb4df2006-02-26 23:24:22 -0800[diff] [blame]39 /* This clobbers %g1 and %g6, preserve them... */
40 mov %g1, %g5
41 mov %g6, %g2
42
43 TRAP_LOAD_PGD_PHYS
44
45 mov %g2, %g6
46 mov %g5, %g1
47
David S. Miller74bf4312006-01-31 18:29:18 -0800[diff] [blame]48 USER_PGTABLE_WALK_TL1(%g4, %g7, %g5, %g2, tsb_do_fault)
49
50tsb_reload:
51 TSB_LOCK_TAG(%g1, %g2, %g4)
52
53 /* Load and check PTE. */
54 ldxa [%g5] ASI_PHYS_USE_EC, %g5
55 brgez,a,pn %g5, tsb_do_fault
56 stx %g0, [%g1]
57
David S. Miller09f94282006-01-31 18:31:06 -0800[diff] [blame]58 /* If it is larger than the base page size, don't
59 * bother putting it into the TSB.
60 */
61 srlx %g5, 32, %g2
62 sethi %hi(_PAGE_ALL_SZ_BITS >> 32), %g4
63 sethi %hi(_PAGE_SZBITS >> 32), %g7
64 and %g2, %g4, %g2
65 cmp %g2, %g7
66 bne,a,pn %xcc, tsb_tlb_reload
67 stx %g0, [%g1]
68
David S. Miller74bf4312006-01-31 18:29:18 -0800[diff] [blame]69 TSB_WRITE(%g1, %g5, %g6)
70
71 /* Finally, load TLB and return from trap. */
72tsb_tlb_reload:
73 cmp %g3, FAULT_CODE_DTLB
74 bne,pn %xcc, tsb_itlb_load
75 nop
76
77tsb_dtlb_load:
78 stxa %g5, [%g0] ASI_DTLB_DATA_IN
79 retry
80
81tsb_itlb_load:
82 stxa %g5, [%g0] ASI_ITLB_DATA_IN
83 retry
84
85 /* No valid entry in the page tables, do full fault
86 * processing.
87 */
88
89 .globl tsb_do_fault
90tsb_do_fault:
91 cmp %g3, FAULT_CODE_DTLB
92 rdpr %pstate, %g5
93 bne,pn %xcc, tsb_do_itlb_fault
94 wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
95
96tsb_do_dtlb_fault:
97 rdpr %tl, %g4
98 cmp %g4, 1
99 mov TLB_TAG_ACCESS, %g4
100 ldxa [%g4] ASI_DMMU, %g5
101 be,pt %xcc, sparc64_realfault_common
102 mov FAULT_CODE_DTLB, %g4
103 ba,pt %xcc, winfix_trampoline
104 nop
105
106tsb_do_itlb_fault:
107 rdpr %tpc, %g5
108 ba,pt %xcc, sparc64_realfault_common
109 mov FAULT_CODE_ITLB, %g4
110
111 .globl sparc64_realfault_common
112sparc64_realfault_common:
David S. Miller9bc657b2006-01-31 18:34:21 -0800[diff] [blame^]113 /* fault code in %g4, fault address in %g5, etrap will
114 * preserve these two values in %l4 and %l5 respectively
115 */
David S. Miller74bf4312006-01-31 18:29:18 -0800[diff] [blame]116 ba,pt %xcc, etrap ! Save trap state
1171: rd %pc, %g7 ! ...
David S. Miller9bc657b2006-01-31 18:34:21 -0800[diff] [blame^]118 stb %l4, [%g6 + TI_FAULT_CODE] ! Save fault code
119 stx %l5, [%g6 + TI_FAULT_ADDR] ! Save fault address
David S. Miller74bf4312006-01-31 18:29:18 -0800[diff] [blame]120 call do_sparc64_fault ! Call fault handler
121 add %sp, PTREGS_OFF, %o0 ! Compute pt_regs arg
122 ba,pt %xcc, rtrap_clr_l6 ! Restore cpu state
123 nop ! Delay slot (fill me)
124
125 .globl winfix_trampoline
126winfix_trampoline:
127 rdpr %tpc, %g3 ! Prepare winfixup TNPC
128 or %g3, 0x7c, %g3 ! Compute branch offset
129 wrpr %g3, %tnpc ! Write it into TNPC
130 done ! Trap return
131
David S. Millerb70c0fa2006-01-31 18:32:04 -0800[diff] [blame]132 /* Insert an entry into the TSB.
133 *
134 * %o0: TSB entry pointer
135 * %o1: tag
136 * %o2: pte
137 */
138 .align 32
139 .globl tsb_insert
140tsb_insert:
141 rdpr %pstate, %o5
142 wrpr %o5, PSTATE_IE, %pstate
143 TSB_LOCK_TAG(%o0, %g2, %g3)
144 TSB_WRITE(%o0, %o2, %o1)
145 wrpr %o5, %pstate
146 retl
147 nop
148
David S. Miller74bf4312006-01-31 18:29:18 -0800[diff] [blame]149 /* Reload MMU related context switch state at
150 * schedule() time.
151 *
152 * %o0: page table physical address
David S. Miller98c55842006-01-31 18:31:20 -0800[diff] [blame]153 * %o1: TSB register value
154 * %o2: TSB virtual address
155 * %o3: TSB mapping locked PTE
156 *
157 * We have to run this whole thing with interrupts
158 * disabled so that the current cpu doesn't change
159 * due to preemption.
David S. Miller74bf4312006-01-31 18:29:18 -0800[diff] [blame]160 */
David S. Miller56fb4df2006-02-26 23:24:22 -0800[diff] [blame]161 .align 32
David S. Miller98c55842006-01-31 18:31:20 -0800[diff] [blame]162 .globl __tsb_context_switch
163__tsb_context_switch:
David S. Miller56fb4df2006-02-26 23:24:22 -0800[diff] [blame]164 rdpr %pstate, %o5
165 wrpr %o5, PSTATE_IE, %pstate
David S. Miller74bf4312006-01-31 18:29:18 -0800[diff] [blame]166
David S. Miller98c55842006-01-31 18:31:20 -0800[diff] [blame]167 ldub [%g6 + TI_CPU], %g1
168 sethi %hi(trap_block), %g2
169 sllx %g1, TRAP_BLOCK_SZ_SHIFT, %g1
170 or %g2, %lo(trap_block), %g2
171 add %g2, %g1, %g2
172 stx %o0, [%g2 + TRAP_PER_CPU_PGD_PADDR]
David S. Miller74bf4312006-01-31 18:29:18 -0800[diff] [blame]173
David S. Miller74bf4312006-01-31 18:29:18 -0800[diff] [blame]174 mov TSB_REG, %g1
David S. Miller98c55842006-01-31 18:31:20 -0800[diff] [blame]175 stxa %o1, [%g1] ASI_DMMU
David S. Miller74bf4312006-01-31 18:29:18 -0800[diff] [blame]176 membar #Sync
177
David S. Miller98c55842006-01-31 18:31:20 -0800[diff] [blame]178 stxa %o1, [%g1] ASI_IMMU
David S. Miller74bf4312006-01-31 18:29:18 -0800[diff] [blame]179 membar #Sync
180
David S. Miller98c55842006-01-31 18:31:20 -0800[diff] [blame]181 brz %o2, 9f
182 nop
David S. Miller74bf4312006-01-31 18:29:18 -0800[diff] [blame]183
David S. Miller6b6d01722006-01-31 18:33:12 -0800[diff] [blame]184 sethi %hi(sparc64_highest_unlocked_tlb_ent), %o4
185 mov TLB_TAG_ACCESS, %g1
186 lduw [%o4 + %lo(sparc64_highest_unlocked_tlb_ent)], %g2
187 stxa %o2, [%g1] ASI_DMMU
188 membar #Sync
189 sllx %g2, 3, %g2
190 stxa %o3, [%g2] ASI_DTLB_DATA_ACCESS
191 membar #Sync
David S. Miller74bf4312006-01-31 18:29:18 -0800[diff] [blame]1929:
David S. Miller56fb4df2006-02-26 23:24:22 -0800[diff] [blame]193 wrpr %o5, %pstate
David S. Miller74bf4312006-01-31 18:29:18 -0800[diff] [blame]194
195 retl
David S. Miller98c55842006-01-31 18:31:20 -0800[diff] [blame]196 nop