blob: 07d1fbff36420693d2b6723638c29d927610203f [file] [log] [blame]
Thierry Reding0fe88462016-08-19 19:19:39 +02001/*
Thierry Reding91b1b1c2018-11-28 10:54:13 +01002 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
Thierry Reding0fe88462016-08-19 19:19:39 +02003 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
Thierry Reding91b1b1c2018-11-28 10:54:13 +010014#include <linux/delay.h>
Thierry Reding0fe88462016-08-19 19:19:39 +020015#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/mailbox_controller.h>
18#include <linux/of.h>
19#include <linux/of_device.h>
20#include <linux/platform_device.h>
Thierry Reding9a63f0f2018-11-28 10:54:14 +010021#include <linux/pm.h>
Thierry Reding0fe88462016-08-19 19:19:39 +020022#include <linux/slab.h>
23
24#include <dt-bindings/mailbox/tegra186-hsp.h>
25
Thierry Reding91b1b1c2018-11-28 10:54:13 +010026#include "mailbox.h"
27
28#define HSP_INT_IE(x) (0x100 + ((x) * 4))
29#define HSP_INT_IV 0x300
30#define HSP_INT_IR 0x304
31
32#define HSP_INT_EMPTY_SHIFT 0
33#define HSP_INT_EMPTY_MASK 0xff
34#define HSP_INT_FULL_SHIFT 8
35#define HSP_INT_FULL_MASK 0xff
36
Thierry Reding0fe88462016-08-19 19:19:39 +020037#define HSP_INT_DIMENSIONING 0x380
38#define HSP_nSM_SHIFT 0
39#define HSP_nSS_SHIFT 4
40#define HSP_nAS_SHIFT 8
41#define HSP_nDB_SHIFT 12
42#define HSP_nSI_SHIFT 16
43#define HSP_nINT_MASK 0xf
44
45#define HSP_DB_TRIGGER 0x0
46#define HSP_DB_ENABLE 0x4
47#define HSP_DB_RAW 0x8
48#define HSP_DB_PENDING 0xc
49
Thierry Reding91b1b1c2018-11-28 10:54:13 +010050#define HSP_SM_SHRD_MBOX 0x0
51#define HSP_SM_SHRD_MBOX_FULL BIT(31)
52#define HSP_SM_SHRD_MBOX_FULL_INT_IE 0x04
53#define HSP_SM_SHRD_MBOX_EMPTY_INT_IE 0x08
54
Thierry Reding0fe88462016-08-19 19:19:39 +020055#define HSP_DB_CCPLEX 1
56#define HSP_DB_BPMP 3
57#define HSP_DB_MAX 7
58
59struct tegra_hsp_channel;
60struct tegra_hsp;
61
62struct tegra_hsp_channel {
63 struct tegra_hsp *hsp;
64 struct mbox_chan *chan;
65 void __iomem *regs;
66};
67
68struct tegra_hsp_doorbell {
69 struct tegra_hsp_channel channel;
70 struct list_head list;
71 const char *name;
72 unsigned int master;
73 unsigned int index;
74};
75
Thierry Reding91b1b1c2018-11-28 10:54:13 +010076struct tegra_hsp_mailbox {
77 struct tegra_hsp_channel channel;
78 unsigned int index;
79 bool producer;
80};
81
Thierry Reding0fe88462016-08-19 19:19:39 +020082struct tegra_hsp_db_map {
83 const char *name;
84 unsigned int master;
85 unsigned int index;
86};
87
88struct tegra_hsp_soc {
89 const struct tegra_hsp_db_map *map;
Thierry Reding91b1b1c2018-11-28 10:54:13 +010090 bool has_per_mb_ie;
Thierry Reding0fe88462016-08-19 19:19:39 +020091};
92
93struct tegra_hsp {
Thierry Reding91b1b1c2018-11-28 10:54:13 +010094 struct device *dev;
Thierry Reding0fe88462016-08-19 19:19:39 +020095 const struct tegra_hsp_soc *soc;
Thierry Reding91b1b1c2018-11-28 10:54:13 +010096 struct mbox_controller mbox_db;
97 struct mbox_controller mbox_sm;
Thierry Reding0fe88462016-08-19 19:19:39 +020098 void __iomem *regs;
Thierry Reding91b1b1c2018-11-28 10:54:13 +010099 unsigned int doorbell_irq;
100 unsigned int *shared_irqs;
101 unsigned int shared_irq;
Thierry Reding0fe88462016-08-19 19:19:39 +0200102 unsigned int num_sm;
103 unsigned int num_as;
104 unsigned int num_ss;
105 unsigned int num_db;
106 unsigned int num_si;
107 spinlock_t lock;
108
109 struct list_head doorbells;
Thierry Reding91b1b1c2018-11-28 10:54:13 +0100110 struct tegra_hsp_mailbox *mailboxes;
Thierry Reding0fe88462016-08-19 19:19:39 +0200111
Thierry Reding91b1b1c2018-11-28 10:54:13 +0100112 unsigned long mask;
113};
Thierry Reding0fe88462016-08-19 19:19:39 +0200114
115static inline u32 tegra_hsp_readl(struct tegra_hsp *hsp, unsigned int offset)
116{
117 return readl(hsp->regs + offset);
118}
119
120static inline void tegra_hsp_writel(struct tegra_hsp *hsp, u32 value,
121 unsigned int offset)
122{
123 writel(value, hsp->regs + offset);
124}
125
126static inline u32 tegra_hsp_channel_readl(struct tegra_hsp_channel *channel,
127 unsigned int offset)
128{
129 return readl(channel->regs + offset);
130}
131
132static inline void tegra_hsp_channel_writel(struct tegra_hsp_channel *channel,
133 u32 value, unsigned int offset)
134{
135 writel(value, channel->regs + offset);
136}
137
138static bool tegra_hsp_doorbell_can_ring(struct tegra_hsp_doorbell *db)
139{
140 u32 value;
141
142 value = tegra_hsp_channel_readl(&db->channel, HSP_DB_ENABLE);
143
144 return (value & BIT(TEGRA_HSP_DB_MASTER_CCPLEX)) != 0;
145}
146
147static struct tegra_hsp_doorbell *
148__tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master)
149{
150 struct tegra_hsp_doorbell *entry;
151
152 list_for_each_entry(entry, &hsp->doorbells, list)
153 if (entry->master == master)
154 return entry;
155
156 return NULL;
157}
158
159static struct tegra_hsp_doorbell *
160tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master)
161{
162 struct tegra_hsp_doorbell *db;
163 unsigned long flags;
164
165 spin_lock_irqsave(&hsp->lock, flags);
166 db = __tegra_hsp_doorbell_get(hsp, master);
167 spin_unlock_irqrestore(&hsp->lock, flags);
168
169 return db;
170}
171
172static irqreturn_t tegra_hsp_doorbell_irq(int irq, void *data)
173{
174 struct tegra_hsp *hsp = data;
175 struct tegra_hsp_doorbell *db;
176 unsigned long master, value;
177
178 db = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
179 if (!db)
180 return IRQ_NONE;
181
182 value = tegra_hsp_channel_readl(&db->channel, HSP_DB_PENDING);
183 tegra_hsp_channel_writel(&db->channel, value, HSP_DB_PENDING);
184
185 spin_lock(&hsp->lock);
186
Thierry Reding91b1b1c2018-11-28 10:54:13 +0100187 for_each_set_bit(master, &value, hsp->mbox_db.num_chans) {
Thierry Reding0fe88462016-08-19 19:19:39 +0200188 struct tegra_hsp_doorbell *db;
189
190 db = __tegra_hsp_doorbell_get(hsp, master);
191 /*
192 * Depending on the bootloader chain, the CCPLEX doorbell will
193 * have some doorbells enabled, which means that requesting an
194 * interrupt will immediately fire.
195 *
196 * In that case, db->channel.chan will still be NULL here and
197 * cause a crash if not properly guarded.
198 *
199 * It remains to be seen if ignoring the doorbell in that case
200 * is the correct solution.
201 */
202 if (db && db->channel.chan)
203 mbox_chan_received_data(db->channel.chan, NULL);
204 }
205
206 spin_unlock(&hsp->lock);
207
208 return IRQ_HANDLED;
209}
210
Thierry Reding91b1b1c2018-11-28 10:54:13 +0100211static irqreturn_t tegra_hsp_shared_irq(int irq, void *data)
212{
213 struct tegra_hsp *hsp = data;
214 unsigned long bit, mask;
215 u32 status, value;
216 void *msg;
217
218 status = tegra_hsp_readl(hsp, HSP_INT_IR) & hsp->mask;
219
220 /* process EMPTY interrupts first */
221 mask = (status >> HSP_INT_EMPTY_SHIFT) & HSP_INT_EMPTY_MASK;
222
223 for_each_set_bit(bit, &mask, hsp->num_sm) {
224 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit];
225
226 if (mb->producer) {
227 /*
228 * Disable EMPTY interrupts until data is sent with
229 * the next message. These interrupts are level-
230 * triggered, so if we kept them enabled they would
231 * constantly trigger until we next write data into
232 * the message.
233 */
234 spin_lock(&hsp->lock);
235
236 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
237 tegra_hsp_writel(hsp, hsp->mask,
238 HSP_INT_IE(hsp->shared_irq));
239
240 spin_unlock(&hsp->lock);
241
242 mbox_chan_txdone(mb->channel.chan, 0);
243 }
244 }
245
246 /* process FULL interrupts */
247 mask = (status >> HSP_INT_FULL_SHIFT) & HSP_INT_FULL_MASK;
248
249 for_each_set_bit(bit, &mask, hsp->num_sm) {
250 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit];
251
252 if (!mb->producer) {
253 value = tegra_hsp_channel_readl(&mb->channel,
254 HSP_SM_SHRD_MBOX);
255 value &= ~HSP_SM_SHRD_MBOX_FULL;
256 msg = (void *)(unsigned long)value;
257 mbox_chan_received_data(mb->channel.chan, msg);
258
259 /*
260 * Need to clear all bits here since some producers,
261 * such as TCU, depend on fields in the register
262 * getting cleared by the consumer.
263 *
264 * The mailbox API doesn't give the consumers a way
265 * of doing that explicitly, so we have to make sure
266 * we cover all possible cases.
267 */
268 tegra_hsp_channel_writel(&mb->channel, 0x0,
269 HSP_SM_SHRD_MBOX);
270 }
271 }
272
273 return IRQ_HANDLED;
274}
275
Thierry Reding0fe88462016-08-19 19:19:39 +0200276static struct tegra_hsp_channel *
277tegra_hsp_doorbell_create(struct tegra_hsp *hsp, const char *name,
278 unsigned int master, unsigned int index)
279{
280 struct tegra_hsp_doorbell *db;
281 unsigned int offset;
282 unsigned long flags;
283
284 db = kzalloc(sizeof(*db), GFP_KERNEL);
285 if (!db)
286 return ERR_PTR(-ENOMEM);
287
Thierry Reding91b1b1c2018-11-28 10:54:13 +0100288 offset = (1 + (hsp->num_sm / 2) + hsp->num_ss + hsp->num_as) * SZ_64K;
Thierry Reding0fe88462016-08-19 19:19:39 +0200289 offset += index * 0x100;
290
291 db->channel.regs = hsp->regs + offset;
292 db->channel.hsp = hsp;
293
294 db->name = kstrdup_const(name, GFP_KERNEL);
295 db->master = master;
296 db->index = index;
297
298 spin_lock_irqsave(&hsp->lock, flags);
299 list_add_tail(&db->list, &hsp->doorbells);
300 spin_unlock_irqrestore(&hsp->lock, flags);
301
302 return &db->channel;
303}
304
305static void __tegra_hsp_doorbell_destroy(struct tegra_hsp_doorbell *db)
306{
307 list_del(&db->list);
308 kfree_const(db->name);
309 kfree(db);
310}
311
312static int tegra_hsp_doorbell_send_data(struct mbox_chan *chan, void *data)
313{
314 struct tegra_hsp_doorbell *db = chan->con_priv;
315
316 tegra_hsp_channel_writel(&db->channel, 1, HSP_DB_TRIGGER);
317
318 return 0;
319}
320
321static int tegra_hsp_doorbell_startup(struct mbox_chan *chan)
322{
323 struct tegra_hsp_doorbell *db = chan->con_priv;
324 struct tegra_hsp *hsp = db->channel.hsp;
325 struct tegra_hsp_doorbell *ccplex;
326 unsigned long flags;
327 u32 value;
328
Thierry Reding91b1b1c2018-11-28 10:54:13 +0100329 if (db->master >= chan->mbox->num_chans) {
330 dev_err(chan->mbox->dev,
Thierry Reding0fe88462016-08-19 19:19:39 +0200331 "invalid master ID %u for HSP channel\n",
332 db->master);
333 return -EINVAL;
334 }
335
336 ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
337 if (!ccplex)
338 return -ENODEV;
339
340 if (!tegra_hsp_doorbell_can_ring(db))
341 return -ENODEV;
342
343 spin_lock_irqsave(&hsp->lock, flags);
344
345 value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE);
346 value |= BIT(db->master);
347 tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE);
348
349 spin_unlock_irqrestore(&hsp->lock, flags);
350
351 return 0;
352}
353
354static void tegra_hsp_doorbell_shutdown(struct mbox_chan *chan)
355{
356 struct tegra_hsp_doorbell *db = chan->con_priv;
357 struct tegra_hsp *hsp = db->channel.hsp;
358 struct tegra_hsp_doorbell *ccplex;
359 unsigned long flags;
360 u32 value;
361
362 ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
363 if (!ccplex)
364 return;
365
366 spin_lock_irqsave(&hsp->lock, flags);
367
368 value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE);
369 value &= ~BIT(db->master);
370 tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE);
371
372 spin_unlock_irqrestore(&hsp->lock, flags);
373}
374
Thierry Reding91b1b1c2018-11-28 10:54:13 +0100375static const struct mbox_chan_ops tegra_hsp_db_ops = {
Thierry Reding0fe88462016-08-19 19:19:39 +0200376 .send_data = tegra_hsp_doorbell_send_data,
377 .startup = tegra_hsp_doorbell_startup,
378 .shutdown = tegra_hsp_doorbell_shutdown,
379};
380
Thierry Reding91b1b1c2018-11-28 10:54:13 +0100381static int tegra_hsp_mailbox_send_data(struct mbox_chan *chan, void *data)
382{
383 struct tegra_hsp_mailbox *mb = chan->con_priv;
384 struct tegra_hsp *hsp = mb->channel.hsp;
385 unsigned long flags;
386 u32 value;
387
388 if (WARN_ON(!mb->producer))
389 return -EPERM;
390
391 /* copy data and mark mailbox full */
392 value = (u32)(unsigned long)data;
393 value |= HSP_SM_SHRD_MBOX_FULL;
394
395 tegra_hsp_channel_writel(&mb->channel, value, HSP_SM_SHRD_MBOX);
396
397 /* enable EMPTY interrupt for the shared mailbox */
398 spin_lock_irqsave(&hsp->lock, flags);
399
400 hsp->mask |= BIT(HSP_INT_EMPTY_SHIFT + mb->index);
401 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
402
403 spin_unlock_irqrestore(&hsp->lock, flags);
404
405 return 0;
406}
407
408static int tegra_hsp_mailbox_flush(struct mbox_chan *chan,
409 unsigned long timeout)
410{
411 struct tegra_hsp_mailbox *mb = chan->con_priv;
412 struct tegra_hsp_channel *ch = &mb->channel;
413 u32 value;
414
415 timeout = jiffies + msecs_to_jiffies(timeout);
416
417 while (time_before(jiffies, timeout)) {
418 value = tegra_hsp_channel_readl(ch, HSP_SM_SHRD_MBOX);
419 if ((value & HSP_SM_SHRD_MBOX_FULL) == 0) {
420 mbox_chan_txdone(chan, 0);
421 return 0;
422 }
423
424 udelay(1);
425 }
426
427 return -ETIME;
428}
429
430static int tegra_hsp_mailbox_startup(struct mbox_chan *chan)
431{
432 struct tegra_hsp_mailbox *mb = chan->con_priv;
433 struct tegra_hsp_channel *ch = &mb->channel;
434 struct tegra_hsp *hsp = mb->channel.hsp;
435 unsigned long flags;
436
437 chan->txdone_method = TXDONE_BY_IRQ;
438
439 /*
440 * Shared mailboxes start out as consumers by default. FULL and EMPTY
441 * interrupts are coalesced at the same shared interrupt.
442 *
443 * Keep EMPTY interrupts disabled at startup and only enable them when
444 * the mailbox is actually full. This is required because the FULL and
445 * EMPTY interrupts are level-triggered, so keeping EMPTY interrupts
446 * enabled all the time would cause an interrupt storm while mailboxes
447 * are idle.
448 */
449
450 spin_lock_irqsave(&hsp->lock, flags);
451
452 if (mb->producer)
453 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
454 else
455 hsp->mask |= BIT(HSP_INT_FULL_SHIFT + mb->index);
456
457 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
458
459 spin_unlock_irqrestore(&hsp->lock, flags);
460
461 if (hsp->soc->has_per_mb_ie) {
462 if (mb->producer)
463 tegra_hsp_channel_writel(ch, 0x0,
464 HSP_SM_SHRD_MBOX_EMPTY_INT_IE);
465 else
466 tegra_hsp_channel_writel(ch, 0x1,
467 HSP_SM_SHRD_MBOX_FULL_INT_IE);
468 }
469
470 return 0;
471}
472
473static void tegra_hsp_mailbox_shutdown(struct mbox_chan *chan)
474{
475 struct tegra_hsp_mailbox *mb = chan->con_priv;
476 struct tegra_hsp_channel *ch = &mb->channel;
477 struct tegra_hsp *hsp = mb->channel.hsp;
478 unsigned long flags;
479
480 if (hsp->soc->has_per_mb_ie) {
481 if (mb->producer)
482 tegra_hsp_channel_writel(ch, 0x0,
483 HSP_SM_SHRD_MBOX_EMPTY_INT_IE);
484 else
485 tegra_hsp_channel_writel(ch, 0x0,
486 HSP_SM_SHRD_MBOX_FULL_INT_IE);
487 }
488
489 spin_lock_irqsave(&hsp->lock, flags);
490
491 if (mb->producer)
492 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
493 else
494 hsp->mask &= ~BIT(HSP_INT_FULL_SHIFT + mb->index);
495
496 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
497
498 spin_unlock_irqrestore(&hsp->lock, flags);
499}
500
501static const struct mbox_chan_ops tegra_hsp_sm_ops = {
502 .send_data = tegra_hsp_mailbox_send_data,
503 .flush = tegra_hsp_mailbox_flush,
504 .startup = tegra_hsp_mailbox_startup,
505 .shutdown = tegra_hsp_mailbox_shutdown,
506};
507
508static struct mbox_chan *tegra_hsp_db_xlate(struct mbox_controller *mbox,
Thierry Reding0fe88462016-08-19 19:19:39 +0200509 const struct of_phandle_args *args)
510{
Thierry Reding91b1b1c2018-11-28 10:54:13 +0100511 struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_db);
512 unsigned int type = args->args[0], master = args->args[1];
Thierry Reding0fe88462016-08-19 19:19:39 +0200513 struct tegra_hsp_channel *channel = ERR_PTR(-ENODEV);
Thierry Reding0fe88462016-08-19 19:19:39 +0200514 struct tegra_hsp_doorbell *db;
515 struct mbox_chan *chan;
516 unsigned long flags;
517 unsigned int i;
518
Thierry Reding91b1b1c2018-11-28 10:54:13 +0100519 if (type != TEGRA_HSP_MBOX_TYPE_DB || !hsp->doorbell_irq)
520 return ERR_PTR(-ENODEV);
Thierry Reding0fe88462016-08-19 19:19:39 +0200521
Thierry Reding91b1b1c2018-11-28 10:54:13 +0100522 db = tegra_hsp_doorbell_get(hsp, master);
523 if (db)
524 channel = &db->channel;
Thierry Reding0fe88462016-08-19 19:19:39 +0200525
526 if (IS_ERR(channel))
527 return ERR_CAST(channel);
528
529 spin_lock_irqsave(&hsp->lock, flags);
530
Thierry Reding91b1b1c2018-11-28 10:54:13 +0100531 for (i = 0; i < mbox->num_chans; i++) {
532 chan = &mbox->chans[i];
Thierry Reding0fe88462016-08-19 19:19:39 +0200533 if (!chan->con_priv) {
Thierry Reding0fe88462016-08-19 19:19:39 +0200534 channel->chan = chan;
Thierry Reding91b1b1c2018-11-28 10:54:13 +0100535 chan->con_priv = db;
Thierry Reding0fe88462016-08-19 19:19:39 +0200536 break;
537 }
538
539 chan = NULL;
540 }
541
542 spin_unlock_irqrestore(&hsp->lock, flags);
543
544 return chan ?: ERR_PTR(-EBUSY);
545}
546
Thierry Reding91b1b1c2018-11-28 10:54:13 +0100547static struct mbox_chan *tegra_hsp_sm_xlate(struct mbox_controller *mbox,
548 const struct of_phandle_args *args)
549{
550 struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_sm);
551 unsigned int type = args->args[0], index;
552 struct tegra_hsp_mailbox *mb;
553
554 index = args->args[1] & TEGRA_HSP_SM_MASK;
555
556 if (type != TEGRA_HSP_MBOX_TYPE_SM || !hsp->shared_irqs ||
557 index >= hsp->num_sm)
558 return ERR_PTR(-ENODEV);
559
560 mb = &hsp->mailboxes[index];
561
562 if ((args->args[1] & TEGRA_HSP_SM_FLAG_TX) == 0)
563 mb->producer = false;
564 else
565 mb->producer = true;
566
567 return mb->channel.chan;
568}
569
Thierry Reding0fe88462016-08-19 19:19:39 +0200570static void tegra_hsp_remove_doorbells(struct tegra_hsp *hsp)
571{
Dan Carpenter68050eb2016-11-18 14:34:10 +0300572 struct tegra_hsp_doorbell *db, *tmp;
Thierry Reding0fe88462016-08-19 19:19:39 +0200573 unsigned long flags;
574
575 spin_lock_irqsave(&hsp->lock, flags);
576
Dan Carpenter68050eb2016-11-18 14:34:10 +0300577 list_for_each_entry_safe(db, tmp, &hsp->doorbells, list)
Thierry Reding0fe88462016-08-19 19:19:39 +0200578 __tegra_hsp_doorbell_destroy(db);
579
580 spin_unlock_irqrestore(&hsp->lock, flags);
581}
582
583static int tegra_hsp_add_doorbells(struct tegra_hsp *hsp)
584{
585 const struct tegra_hsp_db_map *map = hsp->soc->map;
586 struct tegra_hsp_channel *channel;
587
588 while (map->name) {
589 channel = tegra_hsp_doorbell_create(hsp, map->name,
590 map->master, map->index);
591 if (IS_ERR(channel)) {
592 tegra_hsp_remove_doorbells(hsp);
593 return PTR_ERR(channel);
594 }
595
596 map++;
597 }
598
599 return 0;
600}
601
Thierry Reding91b1b1c2018-11-28 10:54:13 +0100602static int tegra_hsp_add_mailboxes(struct tegra_hsp *hsp, struct device *dev)
603{
604 int i;
605
606 hsp->mailboxes = devm_kcalloc(dev, hsp->num_sm, sizeof(*hsp->mailboxes),
607 GFP_KERNEL);
608 if (!hsp->mailboxes)
609 return -ENOMEM;
610
611 for (i = 0; i < hsp->num_sm; i++) {
612 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i];
613
614 mb->index = i;
615
616 mb->channel.hsp = hsp;
617 mb->channel.regs = hsp->regs + SZ_64K + i * SZ_32K;
618 mb->channel.chan = &hsp->mbox_sm.chans[i];
619 mb->channel.chan->con_priv = mb;
620 }
621
622 return 0;
623}
624
625static int tegra_hsp_request_shared_irq(struct tegra_hsp *hsp)
626{
627 unsigned int i, irq = 0;
628 int err;
629
630 for (i = 0; i < hsp->num_si; i++) {
631 irq = hsp->shared_irqs[i];
632 if (irq <= 0)
633 continue;
634
635 err = devm_request_irq(hsp->dev, irq, tegra_hsp_shared_irq, 0,
636 dev_name(hsp->dev), hsp);
637 if (err < 0) {
638 dev_err(hsp->dev, "failed to request interrupt: %d\n",
639 err);
640 continue;
641 }
642
643 hsp->shared_irq = i;
644
645 /* disable all interrupts */
646 tegra_hsp_writel(hsp, 0, HSP_INT_IE(hsp->shared_irq));
647
648 dev_dbg(hsp->dev, "interrupt requested: %u\n", irq);
649
650 break;
651 }
652
653 if (i == hsp->num_si) {
654 dev_err(hsp->dev, "failed to find available interrupt\n");
655 return -ENOENT;
656 }
657
658 return 0;
659}
660
Thierry Reding0fe88462016-08-19 19:19:39 +0200661static int tegra_hsp_probe(struct platform_device *pdev)
662{
663 struct tegra_hsp *hsp;
664 struct resource *res;
Thierry Reding91b1b1c2018-11-28 10:54:13 +0100665 unsigned int i;
Thierry Reding0fe88462016-08-19 19:19:39 +0200666 u32 value;
667 int err;
668
669 hsp = devm_kzalloc(&pdev->dev, sizeof(*hsp), GFP_KERNEL);
670 if (!hsp)
671 return -ENOMEM;
672
Thierry Reding91b1b1c2018-11-28 10:54:13 +0100673 hsp->dev = &pdev->dev;
Thierry Reding0fe88462016-08-19 19:19:39 +0200674 hsp->soc = of_device_get_match_data(&pdev->dev);
675 INIT_LIST_HEAD(&hsp->doorbells);
676 spin_lock_init(&hsp->lock);
677
678 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
679 hsp->regs = devm_ioremap_resource(&pdev->dev, res);
680 if (IS_ERR(hsp->regs))
681 return PTR_ERR(hsp->regs);
682
683 value = tegra_hsp_readl(hsp, HSP_INT_DIMENSIONING);
684 hsp->num_sm = (value >> HSP_nSM_SHIFT) & HSP_nINT_MASK;
685 hsp->num_ss = (value >> HSP_nSS_SHIFT) & HSP_nINT_MASK;
686 hsp->num_as = (value >> HSP_nAS_SHIFT) & HSP_nINT_MASK;
687 hsp->num_db = (value >> HSP_nDB_SHIFT) & HSP_nINT_MASK;
688 hsp->num_si = (value >> HSP_nSI_SHIFT) & HSP_nINT_MASK;
689
690 err = platform_get_irq_byname(pdev, "doorbell");
Thierry Reding91b1b1c2018-11-28 10:54:13 +0100691 if (err >= 0)
692 hsp->doorbell_irq = err;
693
694 if (hsp->num_si > 0) {
695 unsigned int count = 0;
696
697 hsp->shared_irqs = devm_kcalloc(&pdev->dev, hsp->num_si,
698 sizeof(*hsp->shared_irqs),
699 GFP_KERNEL);
700 if (!hsp->shared_irqs)
701 return -ENOMEM;
702
703 for (i = 0; i < hsp->num_si; i++) {
704 char *name;
705
706 name = kasprintf(GFP_KERNEL, "shared%u", i);
707 if (!name)
708 return -ENOMEM;
709
710 err = platform_get_irq_byname(pdev, name);
711 if (err >= 0) {
712 hsp->shared_irqs[i] = err;
713 count++;
714 }
715
716 kfree(name);
717 }
718
719 if (count == 0) {
720 devm_kfree(&pdev->dev, hsp->shared_irqs);
721 hsp->shared_irqs = NULL;
722 }
Thierry Reding0fe88462016-08-19 19:19:39 +0200723 }
724
Thierry Reding91b1b1c2018-11-28 10:54:13 +0100725 /* setup the doorbell controller */
726 hsp->mbox_db.of_xlate = tegra_hsp_db_xlate;
727 hsp->mbox_db.num_chans = 32;
728 hsp->mbox_db.dev = &pdev->dev;
729 hsp->mbox_db.ops = &tegra_hsp_db_ops;
Thierry Reding0fe88462016-08-19 19:19:39 +0200730
Thierry Reding91b1b1c2018-11-28 10:54:13 +0100731 hsp->mbox_db.chans = devm_kcalloc(&pdev->dev, hsp->mbox_db.num_chans,
732 sizeof(*hsp->mbox_db.chans),
733 GFP_KERNEL);
734 if (!hsp->mbox_db.chans)
Thierry Reding0fe88462016-08-19 19:19:39 +0200735 return -ENOMEM;
736
Thierry Reding91b1b1c2018-11-28 10:54:13 +0100737 if (hsp->doorbell_irq) {
738 err = tegra_hsp_add_doorbells(hsp);
739 if (err < 0) {
740 dev_err(&pdev->dev, "failed to add doorbells: %d\n",
741 err);
742 return err;
743 }
744 }
745
746 err = mbox_controller_register(&hsp->mbox_db);
Thierry Reding0fe88462016-08-19 19:19:39 +0200747 if (err < 0) {
Thierry Reding91b1b1c2018-11-28 10:54:13 +0100748 dev_err(&pdev->dev, "failed to register doorbell mailbox: %d\n",
749 err);
750 goto remove_doorbells;
751 }
752
753 /* setup the shared mailbox controller */
754 hsp->mbox_sm.of_xlate = tegra_hsp_sm_xlate;
755 hsp->mbox_sm.num_chans = hsp->num_sm;
756 hsp->mbox_sm.dev = &pdev->dev;
757 hsp->mbox_sm.ops = &tegra_hsp_sm_ops;
758
759 hsp->mbox_sm.chans = devm_kcalloc(&pdev->dev, hsp->mbox_sm.num_chans,
760 sizeof(*hsp->mbox_sm.chans),
761 GFP_KERNEL);
762 if (!hsp->mbox_sm.chans)
763 return -ENOMEM;
764
765 if (hsp->shared_irqs) {
766 err = tegra_hsp_add_mailboxes(hsp, &pdev->dev);
767 if (err < 0) {
768 dev_err(&pdev->dev, "failed to add mailboxes: %d\n",
769 err);
770 goto unregister_mbox_db;
771 }
772 }
773
774 err = mbox_controller_register(&hsp->mbox_sm);
775 if (err < 0) {
776 dev_err(&pdev->dev, "failed to register shared mailbox: %d\n",
777 err);
778 goto unregister_mbox_db;
Thierry Reding0fe88462016-08-19 19:19:39 +0200779 }
780
781 platform_set_drvdata(pdev, hsp);
782
Thierry Reding91b1b1c2018-11-28 10:54:13 +0100783 if (hsp->doorbell_irq) {
784 err = devm_request_irq(&pdev->dev, hsp->doorbell_irq,
785 tegra_hsp_doorbell_irq, IRQF_NO_SUSPEND,
786 dev_name(&pdev->dev), hsp);
787 if (err < 0) {
788 dev_err(&pdev->dev,
789 "failed to request doorbell IRQ#%u: %d\n",
790 hsp->doorbell_irq, err);
791 goto unregister_mbox_sm;
792 }
Thierry Reding0fe88462016-08-19 19:19:39 +0200793 }
794
Thierry Reding91b1b1c2018-11-28 10:54:13 +0100795 if (hsp->shared_irqs) {
796 err = tegra_hsp_request_shared_irq(hsp);
797 if (err < 0)
798 goto unregister_mbox_sm;
Thierry Reding0fe88462016-08-19 19:19:39 +0200799 }
800
801 return 0;
Thierry Reding91b1b1c2018-11-28 10:54:13 +0100802
803unregister_mbox_sm:
804 mbox_controller_unregister(&hsp->mbox_sm);
805unregister_mbox_db:
806 mbox_controller_unregister(&hsp->mbox_db);
807remove_doorbells:
808 if (hsp->doorbell_irq)
809 tegra_hsp_remove_doorbells(hsp);
810
811 return err;
Thierry Reding0fe88462016-08-19 19:19:39 +0200812}
813
814static int tegra_hsp_remove(struct platform_device *pdev)
815{
816 struct tegra_hsp *hsp = platform_get_drvdata(pdev);
817
Thierry Reding91b1b1c2018-11-28 10:54:13 +0100818 mbox_controller_unregister(&hsp->mbox_sm);
819 mbox_controller_unregister(&hsp->mbox_db);
820
821 if (hsp->doorbell_irq)
822 tegra_hsp_remove_doorbells(hsp);
Thierry Reding0fe88462016-08-19 19:19:39 +0200823
824 return 0;
825}
826
Thierry Reding9a63f0f2018-11-28 10:54:14 +0100827static int tegra_hsp_resume(struct device *dev)
828{
829 struct tegra_hsp *hsp = dev_get_drvdata(dev);
830 unsigned int i;
831
832 for (i = 0; i < hsp->num_sm; i++) {
833 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i];
834
835 if (mb->channel.chan->cl)
836 tegra_hsp_mailbox_startup(mb->channel.chan);
837 }
838
839 return 0;
840}
841
842static SIMPLE_DEV_PM_OPS(tegra_hsp_pm_ops, NULL, tegra_hsp_resume);
843
Thierry Reding0fe88462016-08-19 19:19:39 +0200844static const struct tegra_hsp_db_map tegra186_hsp_db_map[] = {
845 { "ccplex", TEGRA_HSP_DB_MASTER_CCPLEX, HSP_DB_CCPLEX, },
846 { "bpmp", TEGRA_HSP_DB_MASTER_BPMP, HSP_DB_BPMP, },
847 { /* sentinel */ }
848};
849
850static const struct tegra_hsp_soc tegra186_hsp_soc = {
851 .map = tegra186_hsp_db_map,
Thierry Reding91b1b1c2018-11-28 10:54:13 +0100852 .has_per_mb_ie = false,
853};
854
855static const struct tegra_hsp_soc tegra194_hsp_soc = {
856 .map = tegra186_hsp_db_map,
857 .has_per_mb_ie = true,
Thierry Reding0fe88462016-08-19 19:19:39 +0200858};
859
860static const struct of_device_id tegra_hsp_match[] = {
861 { .compatible = "nvidia,tegra186-hsp", .data = &tegra186_hsp_soc },
Thierry Reding91b1b1c2018-11-28 10:54:13 +0100862 { .compatible = "nvidia,tegra194-hsp", .data = &tegra194_hsp_soc },
Thierry Reding0fe88462016-08-19 19:19:39 +0200863 { }
864};
865
866static struct platform_driver tegra_hsp_driver = {
867 .driver = {
868 .name = "tegra-hsp",
869 .of_match_table = tegra_hsp_match,
Thierry Reding9a63f0f2018-11-28 10:54:14 +0100870 .pm = &tegra_hsp_pm_ops,
Thierry Reding0fe88462016-08-19 19:19:39 +0200871 },
872 .probe = tegra_hsp_probe,
873 .remove = tegra_hsp_remove,
874};
875
876static int __init tegra_hsp_init(void)
877{
878 return platform_driver_register(&tegra_hsp_driver);
879}
880core_initcall(tegra_hsp_init);