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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 99d89e3da31c0c2596553e0a324c526f4fbd66cb / . / arch / arm / boot / dts / am335x-baltos-ir5221.dts
blob: 7d36601697da867a6f5ff1a4d061f0eecc0664dd [file] [log] [blame]
Yegor Yefremov99d89e32015-05-19 10:29:48 +0200[diff] [blame^]1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * VScom OnRISC
11 * http://www.vscom.de
12 */
13
14/dts-v1/;
15
16#include "am33xx.dtsi"
17#include <dt-bindings/pwm/pwm.h>
18#include <dt-bindings/interrupt-controller/irq.h>
19
20/ {
21 model = "OnRISC Baltos iR 5221";
22 compatible = "vscom,onrisc", "ti,am33xx";
23
24 cpus {
25 cpu@0 {
26 cpu0-supply = <&vdd1_reg>;
27 };
28 };
29
30 memory {
31 device_type = "memory";
32 reg = <0x80000000 0x10000000>; /* 256 MB */
33 };
34
35 vbat: fixedregulator@0 {
36 compatible = "regulator-fixed";
37 regulator-name = "vbat";
38 regulator-min-microvolt = <5000000>;
39 regulator-max-microvolt = <5000000>;
40 regulator-boot-on;
41 };
42
43 wl12xx_vmmc: fixedregulator@2 {
44 pinctrl-names = "default";
45 pinctrl-0 = <&wl12xx_gpio>;
46 compatible = "regulator-fixed";
47 regulator-name = "vwl1271";
48 regulator-min-microvolt = <3300000>;
49 regulator-max-microvolt = <3300000>;
50 gpio = <&gpio3 8 0>;
51 startup-delay-us = <70000>;
52 enable-active-high;
53 };
54};
55
56&am33xx_pinmux {
57 mmc2_pins: pinmux_mmc2_pins {
58 pinctrl-single,pins = <
59 0x020 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad8.mmc1_dat0_mux0 */
60 0x024 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad9.mmc1_dat1_mux0 */
61 0x028 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad10.mmc1_dat2_mux0 */
62 0x02c (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad11.mmc1_dat3_mux0 */
63 0x080 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk_mux0 */
64 0x084 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd_mux0 */
65 0x1e4 (PIN_INPUT_PULLUP | MUX_MODE7) /* emu0.gpio3[7] */
66 >;
67 };
68
69 wl12xx_gpio: pinmux_wl12xx_gpio {
70 pinctrl-single,pins = <
71 0x1e8 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* emu1.gpio3[8] */
72 >;
73 };
74
75 tps65910_pins: pinmux_tps65910_pins {
76 pinctrl-single,pins = <
77 0x078 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ben1.gpio1[28] */
78 >;
79 };
80
81 tca6416_pins: pinmux_tca6416_pins {
82 pinctrl-single,pins = <
83 0x1b4 (PIN_INPUT_PULLUP | MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */
84 >;
85 };
86
87 i2c1_pins: pinmux_i2c1_pins {
88 pinctrl-single,pins = <
89 0x158 0x2a /* spi0_d1.i2c1_sda_mux3, INPUT | MODE2 */
90 0x15c 0x2a /* spi0_cs0.i2c1_scl_mux3, INPUT | MODE2 */
91 >;
92 };
93
94 dcan1_pins: pinmux_dcan1_pins {
95 pinctrl-single,pins = <
96 0x168 0x0a /* uart0_ctsn.dcan1_tx_mux0, OUTPUT | MODE2 */
97 0x16c 0x2a /* uart0_rtsn.dcan1_rx_mux0, INPUT | MODE2 */
98 >;
99 };
100
101 uart0_pins: pinmux_uart0_pins {
102 pinctrl-single,pins = <
103 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
104 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
105 >;
106 };
107
108 uart1_pins: pinmux_uart1_pins {
109 pinctrl-single,pins = <
110 0x180 0x28 /* uart1_rxd, INPUT | MODE0 */
111 0x184 0x28 /* uart1_txd, INPUT | MODE0 */
112 /*0x178 0x28*/ /* uart1_ctsn, INPUT | MODE0 */
113 /*0x17c 0x08*/ /* uart1_rtsn, OUTPUT | MODE0 */
114 0x178 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_ctsn, INPUT | MODE0 */
115 0x17c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_rtsn, OUTPUT | MODE0 */
116 0x0e0 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */
117 0x0e4 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */
118 0x0e8 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */
119 0x0ec (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */
120 >;
121 };
122
123 uart2_pins: pinmux_uart2_pins {
124 pinctrl-single,pins = <
125 0x150 0x29 /* spi0_sclk.uart2_rxd_mux3, INPUT | MODE1 */
126 0x154 0x09 /* spi0_d0.uart2_txd_mux3, OUTPUT | MODE1 */
127 /*0x188 0x2a*/ /* i2c0_sda.uart2_ctsn_mux0, INPUT | MODE2 */
128 /*0x18c 0x2a*/ /* i2c0_scl.uart2_rtsn_mux0, INPUT | MODE2 */
129 0x188 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* i2c0_sda.uart2_ctsn_mux0 */
130 0x18c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* i2c0_scl.uart2_rtsn_mux0 */
131 0x030 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.gpio1[12] DTR */
132 0x034 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.gpio1[13] DSR */
133 0x038 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.gpio1[14] DCD */
134 0x03c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.gpio1[15] RI */
135
136 0x1a0 (PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */
137 >;
138 };
139
140 cpsw_default: cpsw_default {
141 pinctrl-single,pins = <
142 /* Slave 1 */
143 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
144 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_tx_en.rmii1_txen */
145 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
146 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
147 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
148 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
149 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */
150
151
152 /* Slave 2 */
153 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
154 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */
155 0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
156 0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
157 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
158 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
159 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
160 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
161 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
162 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
163 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
164 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
165 >;
166 };
167
168 cpsw_sleep: cpsw_sleep {
169 pinctrl-single,pins = <
170 /* Slave 1 reset value */
171 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
172 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
173 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
174 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
175 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
176 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
177 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
178
179 /* Slave 2 reset value*/
180 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7)
181 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)
182 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)
183 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)
184 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7)
185 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7)
186 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7)
187 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7)
188 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7)
189 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)
190 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)
191 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)
192 >;
193 };
194
195 davinci_mdio_default: davinci_mdio_default {
196 pinctrl-single,pins = <
197 /* MDIO */
198 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
199 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
200 >;
201 };
202
203 davinci_mdio_sleep: davinci_mdio_sleep {
204 pinctrl-single,pins = <
205 /* MDIO reset value */
206 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
207 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
208 >;
209 };
210
211 nandflash_pins_s0: nandflash_pins_s0 {
212 pinctrl-single,pins = <
213 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
214 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
215 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
216 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
217 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
218 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
219 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
220 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
221 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
222 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
223 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
224 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
225 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
226 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
227 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
228 >;
229 };
230};
231
232&elm {
233 status = "okay";
234};
235
236&gpmc {
237 pinctrl-names = "default";
238 pinctrl-0 = <&nandflash_pins_s0>;
239 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
240 status = "okay";
241
242 nand@0,0 {
243 reg = <0 0 0>; /* CS0, offset 0 */
244 nand-bus-width = <8>;
245 ti,nand-ecc-opt = "bch8";
246 ti,nand-xfer-type = "polled";
247
248 gpmc,device-nand = "true";
249 gpmc,device-width = <1>;
250 gpmc,sync-clk-ps = <0>;
251 gpmc,cs-on-ns = <0>;
252 gpmc,cs-rd-off-ns = <44>;
253 gpmc,cs-wr-off-ns = <44>;
254 gpmc,adv-on-ns = <6>;
255 gpmc,adv-rd-off-ns = <34>;
256 gpmc,adv-wr-off-ns = <44>;
257 gpmc,we-on-ns = <0>;
258 gpmc,we-off-ns = <40>;
259 gpmc,oe-on-ns = <0>;
260 gpmc,oe-off-ns = <54>;
261 gpmc,access-ns = <64>;
262 gpmc,rd-cycle-ns = <82>;
263 gpmc,wr-cycle-ns = <82>;
264 gpmc,wait-on-read = "true";
265 gpmc,wait-on-write = "true";
266 gpmc,bus-turnaround-ns = <0>;
267 gpmc,cycle2cycle-delay-ns = <0>;
268 gpmc,clk-activation-ns = <0>;
269 gpmc,wait-monitoring-ns = <0>;
270 gpmc,wr-access-ns = <40>;
271 gpmc,wr-data-mux-bus-ns = <0>;
272
273 #address-cells = <1>;
274 #size-cells = <1>;
275 elm_id = <&elm>;
276 };
277};
278
279&uart0 {
280 pinctrl-names = "default";
281 pinctrl-0 = <&uart0_pins>;
282
283 status = "okay";
284};
285
286&uart1 {
287 pinctrl-names = "default";
288 pinctrl-0 = <&uart1_pins>;
289 dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
290 dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
291 dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
292 rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;
293 cts-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
294 rts-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
295
296 status = "okay";
297};
298
299&uart2 {
300 pinctrl-names = "default";
301 pinctrl-0 = <&uart2_pins>;
302 dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
303 dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
304 dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
305 rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
306 cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
307 rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
308
309 status = "okay";
310};
311
312&i2c1 {
313 pinctrl-names = "default";
314 pinctrl-0 = <&i2c1_pins>;
315
316 status = "okay";
317 clock-frequency = <400000>;
318
319 tps: tps@2d {
320 reg = <0x2d>;
321 gpio-controller;
322 #gpio-cells = <2>;
323 interrupt-parent = <&gpio1>;
324 interrupts = <28 GPIO_ACTIVE_LOW>;
325 pinctrl-names = "default";
326 pinctrl-0 = <&tps65910_pins>;
327 };
328
329 at24@50 {
330 compatible = "at24,24c02";
331 pagesize = <8>;
332 reg = <0x50>;
333 };
334
335 tca6416: gpio@20 {
336 compatible = "ti,tca6416";
337 reg = <0x20>;
338 gpio-controller;
339 #gpio-cells = <2>;
340 interrupt-parent = <&gpio0>;
341 interrupts = <20 GPIO_ACTIVE_LOW>;
342 pinctrl-names = "default";
343 pinctrl-0 = <&tca6416_pins>;
344 };
345};
346
347&usb {
348 status = "okay";
349};
350
351&usb_ctrl_mod {
352 status = "okay";
353};
354
355&usb0_phy {
356 status = "okay";
357};
358
359&usb1_phy {
360 status = "okay";
361};
362
363&usb0 {
364 status = "okay";
365 dr_mode = "host";
366};
367
368&usb1 {
369 status = "okay";
370 dr_mode = "otg";
371};
372
373&cppi41dma {
374 status = "okay";
375};
376
377#include "tps65910.dtsi"
378
379&tps {
380 vcc1-supply = <&vbat>;
381 vcc2-supply = <&vbat>;
382 vcc3-supply = <&vbat>;
383 vcc4-supply = <&vbat>;
384 vcc5-supply = <&vbat>;
385 vcc6-supply = <&vbat>;
386 vcc7-supply = <&vbat>;
387 vccio-supply = <&vbat>;
388
389 ti,en-ck32k-xtal = <1>;
390
391 regulators {
392 vrtc_reg: regulator@0 {
393 regulator-always-on;
394 };
395
396 vio_reg: regulator@1 {
397 regulator-always-on;
398 };
399
400 vdd1_reg: regulator@2 {
401 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
402 regulator-name = "vdd_mpu";
403 regulator-min-microvolt = <912500>;
404 regulator-max-microvolt = <1312500>;
405 regulator-boot-on;
406 regulator-always-on;
407 };
408
409 vdd2_reg: regulator@3 {
410 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
411 regulator-name = "vdd_core";
412 regulator-min-microvolt = <912500>;
413 regulator-max-microvolt = <1150000>;
414 regulator-boot-on;
415 regulator-always-on;
416 };
417
418 vdd3_reg: regulator@4 {
419 regulator-always-on;
420 };
421
422 vdig1_reg: regulator@5 {
423 regulator-always-on;
424 };
425
426 vdig2_reg: regulator@6 {
427 regulator-always-on;
428 };
429
430 vpll_reg: regulator@7 {
431 regulator-always-on;
432 };
433
434 vdac_reg: regulator@8 {
435 regulator-always-on;
436 };
437
438 vaux1_reg: regulator@9 {
439 regulator-always-on;
440 };
441
442 vaux2_reg: regulator@10 {
443 regulator-always-on;
444 };
445
446 vaux33_reg: regulator@11 {
447 regulator-always-on;
448 };
449
450 vmmc_reg: regulator@12 {
451 regulator-min-microvolt = <1800000>;
452 regulator-max-microvolt = <3300000>;
453 regulator-always-on;
454 };
455 };
456};
457
458&mac {
459 pinctrl-names = "default", "sleep";
460 pinctrl-0 = <&cpsw_default>;
461 pinctrl-1 = <&cpsw_sleep>;
462 dual_emac = <1>;
463
464 status = "okay";
465};
466
467&davinci_mdio {
468 pinctrl-names = "default", "sleep";
469 pinctrl-0 = <&davinci_mdio_default>;
470 pinctrl-1 = <&davinci_mdio_sleep>;
471
472 status = "okay";
473};
474
475&cpsw_emac0 {
476 phy_id = <&davinci_mdio>, <0>;
477 phy-mode = "rmii";
478 dual_emac_res_vlan = <1>;
479};
480
481&cpsw_emac1 {
482 phy_id = <&davinci_mdio>, <7>;
483 phy-mode = "rgmii-txid";
484 dual_emac_res_vlan = <2>;
485};
486
487&phy_sel {
488 rmii-clock-ext = <1>;
489};
490
491&mmc1 {
492 vmmc-supply = <&vmmc_reg>;
493 status = "okay";
494};
495
496&mmc2 {
497 status = "okay";
498 vmmc-supply = <&wl12xx_vmmc>;
499 ti,non-removable;
500 bus-width = <4>;
501 cap-power-off-card;
502 pinctrl-names = "default";
503 pinctrl-0 = <&mmc2_pins>;
504
505 #address-cells = <1>;
506 #size-cells = <0>;
507 wlcore: wlcore@2 {
508 compatible = "ti,wl1835";
509 reg = <2>;
510 interrupt-parent = <&gpio3>;
511 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
512 };
513};
514
515&sham {
516 status = "okay";
517};
518
519&aes {
520 status = "okay";
521};
522
523&gpio0 {
524 ti,no-reset-on-init;
525};
526
527&dcan1 {
528 pinctrl-names = "default";
529 pinctrl-0 = <&dcan1_pins>;
530
531 status = "okay";
532};