Mauro Carvalho Chehab | 9b5db89 | 2019-06-28 18:23:13 -0300 | [diff] [blame] | 1 | ==================== |
R.Marek@sh.cvut.cz | 7f15b66 | 2005-05-26 12:42:19 +0000 | [diff] [blame] | 2 | Kernel driver eeprom |
| 3 | ==================== |
| 4 | |
| 5 | Supported chips: |
Mauro Carvalho Chehab | 9b5db89 | 2019-06-28 18:23:13 -0300 | [diff] [blame] | 6 | |
R.Marek@sh.cvut.cz | 7f15b66 | 2005-05-26 12:42:19 +0000 | [diff] [blame] | 7 | * Any EEPROM chip in the designated address range |
Mauro Carvalho Chehab | 9b5db89 | 2019-06-28 18:23:13 -0300 | [diff] [blame] | 8 | |
R.Marek@sh.cvut.cz | 7f15b66 | 2005-05-26 12:42:19 +0000 | [diff] [blame] | 9 | Prefix: 'eeprom' |
Mauro Carvalho Chehab | 9b5db89 | 2019-06-28 18:23:13 -0300 | [diff] [blame] | 10 | |
R.Marek@sh.cvut.cz | 7f15b66 | 2005-05-26 12:42:19 +0000 | [diff] [blame] | 11 | Addresses scanned: I2C 0x50 - 0x57 |
Mauro Carvalho Chehab | 9b5db89 | 2019-06-28 18:23:13 -0300 | [diff] [blame] | 12 | |
R.Marek@sh.cvut.cz | 7f15b66 | 2005-05-26 12:42:19 +0000 | [diff] [blame] | 13 | Datasheets: Publicly available from: |
Mauro Carvalho Chehab | 9b5db89 | 2019-06-28 18:23:13 -0300 | [diff] [blame] | 14 | |
R.Marek@sh.cvut.cz | 7f15b66 | 2005-05-26 12:42:19 +0000 | [diff] [blame] | 15 | Atmel (www.atmel.com), |
| 16 | Catalyst (www.catsemi.com), |
| 17 | Fairchild (www.fairchildsemi.com), |
| 18 | Microchip (www.microchip.com), |
| 19 | Philips (www.semiconductor.philips.com), |
| 20 | Rohm (www.rohm.com), |
| 21 | ST (www.st.com), |
| 22 | Xicor (www.xicor.com), |
| 23 | and others. |
| 24 | |
Mauro Carvalho Chehab | 9b5db89 | 2019-06-28 18:23:13 -0300 | [diff] [blame] | 25 | ========= ============= ============================================ |
| 26 | Chip Size (bits) Address |
| 27 | ========= ============= ============================================ |
R.Marek@sh.cvut.cz | 7f15b66 | 2005-05-26 12:42:19 +0000 | [diff] [blame] | 28 | 24C01 1K 0x50 (shadows at 0x51 - 0x57) |
| 29 | 24C01A 1K 0x50 - 0x57 (Typical device on DIMMs) |
| 30 | 24C02 2K 0x50 - 0x57 |
| 31 | 24C04 4K 0x50, 0x52, 0x54, 0x56 |
| 32 | (additional data at 0x51, 0x53, 0x55, 0x57) |
| 33 | 24C08 8K 0x50, 0x54 (additional data at 0x51, 0x52, |
| 34 | 0x53, 0x55, 0x56, 0x57) |
Mauro Carvalho Chehab | 9b5db89 | 2019-06-28 18:23:13 -0300 | [diff] [blame] | 35 | 24C16 16K 0x50 (additional data at 0x51 - 0x57) |
R.Marek@sh.cvut.cz | 7f15b66 | 2005-05-26 12:42:19 +0000 | [diff] [blame] | 36 | Sony 2K 0x57 |
| 37 | |
| 38 | Atmel 34C02B 2K 0x50 - 0x57, SW write protect at 0x30-37 |
| 39 | Catalyst 34FC02 2K 0x50 - 0x57, SW write protect at 0x30-37 |
| 40 | Catalyst 34RC02 2K 0x50 - 0x57, SW write protect at 0x30-37 |
| 41 | Fairchild 34W02 2K 0x50 - 0x57, SW write protect at 0x30-37 |
| 42 | Microchip 24AA52 2K 0x50 - 0x57, SW write protect at 0x30-37 |
| 43 | ST M34C02 2K 0x50 - 0x57, SW write protect at 0x30-37 |
Mauro Carvalho Chehab | 9b5db89 | 2019-06-28 18:23:13 -0300 | [diff] [blame] | 44 | ========= ============= ============================================ |
R.Marek@sh.cvut.cz | 7f15b66 | 2005-05-26 12:42:19 +0000 | [diff] [blame] | 45 | |
| 46 | |
| 47 | Authors: |
Mauro Carvalho Chehab | 9b5db89 | 2019-06-28 18:23:13 -0300 | [diff] [blame] | 48 | - Frodo Looijaard <frodol@dds.nl>, |
| 49 | - Philip Edelbrock <phil@netroedge.com>, |
| 50 | - Jean Delvare <jdelvare@suse.de>, |
| 51 | - Greg Kroah-Hartman <greg@kroah.com>, |
| 52 | - IBM Corp. |
R.Marek@sh.cvut.cz | 7f15b66 | 2005-05-26 12:42:19 +0000 | [diff] [blame] | 53 | |
| 54 | Description |
| 55 | ----------- |
| 56 | |
| 57 | This is a simple EEPROM module meant to enable reading the first 256 bytes |
| 58 | of an EEPROM (on a SDRAM DIMM for example). However, it will access serial |
| 59 | EEPROMs on any I2C adapter. The supported devices are generically called |
| 60 | 24Cxx, and are listed above; however the numbering for these |
| 61 | industry-standard devices may vary by manufacturer. |
| 62 | |
| 63 | This module was a programming exercise to get used to the new project |
| 64 | organization laid out by Frodo, but it should be at least completely |
| 65 | effective for decoding the contents of EEPROMs on DIMMs. |
| 66 | |
| 67 | DIMMS will typically contain a 24C01A or 24C02, or the 34C02 variants. |
| 68 | The other devices will not be found on a DIMM because they respond to more |
| 69 | than one address. |
| 70 | |
| 71 | DDC Monitors may contain any device. Often a 24C01, which responds to all 8 |
| 72 | addresses, is found. |
| 73 | |
| 74 | Recent Sony Vaio laptops have an EEPROM at 0x57. We couldn't get the |
| 75 | specification, so it is guess work and far from being complete. |
| 76 | |
| 77 | The Microchip 24AA52/24LCS52, ST M34C02, and others support an additional |
| 78 | software write protect register at 0x30 - 0x37 (0x20 less than the memory |
| 79 | location). The chip responds to "write quick" detection at this address but |
| 80 | does not respond to byte reads. If this register is present, the lower 128 |
| 81 | bytes of the memory array are not write protected. Any byte data write to |
| 82 | this address will write protect the memory array permanently, and the |
| 83 | device will no longer respond at the 0x30-37 address. The eeprom driver |
| 84 | does not support this register. |
| 85 | |
Mauro Carvalho Chehab | 9b5db89 | 2019-06-28 18:23:13 -0300 | [diff] [blame] | 86 | Lacking functionality |
| 87 | --------------------- |
R.Marek@sh.cvut.cz | 7f15b66 | 2005-05-26 12:42:19 +0000 | [diff] [blame] | 88 | |
| 89 | * Full support for larger devices (24C04, 24C08, 24C16). These are not |
Mauro Carvalho Chehab | 9b5db89 | 2019-06-28 18:23:13 -0300 | [diff] [blame] | 90 | typically found on a PC. These devices will appear as separate devices at |
| 91 | multiple addresses. |
R.Marek@sh.cvut.cz | 7f15b66 | 2005-05-26 12:42:19 +0000 | [diff] [blame] | 92 | |
| 93 | * Support for really large devices (24C32, 24C64, 24C128, 24C256, 24C512). |
Mauro Carvalho Chehab | 9b5db89 | 2019-06-28 18:23:13 -0300 | [diff] [blame] | 94 | These devices require two-byte address fields and are not supported. |
R.Marek@sh.cvut.cz | 7f15b66 | 2005-05-26 12:42:19 +0000 | [diff] [blame] | 95 | |
| 96 | * Enable Writing. Again, no technical reason why not, but making it easy |
Mauro Carvalho Chehab | 9b5db89 | 2019-06-28 18:23:13 -0300 | [diff] [blame] | 97 | to change the contents of the EEPROMs (on DIMMs anyway) also makes it easy |
| 98 | to disable the DIMMs (potentially preventing the computer from booting) |
| 99 | until the values are restored somehow. |
R.Marek@sh.cvut.cz | 7f15b66 | 2005-05-26 12:42:19 +0000 | [diff] [blame] | 100 | |
Mauro Carvalho Chehab | 9b5db89 | 2019-06-28 18:23:13 -0300 | [diff] [blame] | 101 | Use |
| 102 | --- |
R.Marek@sh.cvut.cz | 7f15b66 | 2005-05-26 12:42:19 +0000 | [diff] [blame] | 103 | |
| 104 | After inserting the module (and any other required SMBus/i2c modules), you |
Mauro Carvalho Chehab | 9b5db89 | 2019-06-28 18:23:13 -0300 | [diff] [blame] | 105 | should have some EEPROM directories in ``/sys/bus/i2c/devices/*`` of names such |
R.Marek@sh.cvut.cz | 7f15b66 | 2005-05-26 12:42:19 +0000 | [diff] [blame] | 106 | as "0-0050". Inside each of these is a series of files, the eeprom file |
| 107 | contains the binary data from EEPROM. |