Greg Kroah-Hartman | b244131 | 2017-11-01 15:07:57 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | |
| 3 | /* |
| 4 | * ATI Mach64 CT/VT/GT/LT Support |
| 5 | */ |
| 6 | |
| 7 | #include <linux/fb.h> |
| 8 | #include <linux/delay.h> |
| 9 | #include <asm/io.h> |
| 10 | #include <video/mach64.h> |
| 11 | #include "atyfb.h" |
Risto Suominen | 7fbb7ca | 2009-01-13 20:09:30 +0000 | [diff] [blame] | 12 | #ifdef CONFIG_PPC |
| 13 | #include <asm/machdep.h> |
| 14 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15 | |
| 16 | #undef DEBUG |
| 17 | |
| 18 | static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll); |
| 19 | static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll); |
| 20 | static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll); |
| 21 | static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll); |
| 22 | |
| 23 | u8 aty_ld_pll_ct(int offset, const struct atyfb_par *par) |
| 24 | { |
| 25 | u8 res; |
| 26 | |
| 27 | /* write addr byte */ |
| 28 | aty_st_8(CLOCK_CNTL_ADDR, (offset << 2) & PLL_ADDR, par); |
| 29 | /* read the register value */ |
| 30 | res = aty_ld_8(CLOCK_CNTL_DATA, par); |
| 31 | return res; |
| 32 | } |
| 33 | |
Adrian Bunk | 9c5b39e | 2006-10-03 01:15:02 -0700 | [diff] [blame] | 34 | static void aty_st_pll_ct(int offset, u8 val, const struct atyfb_par *par) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 35 | { |
| 36 | /* write addr byte */ |
| 37 | aty_st_8(CLOCK_CNTL_ADDR, ((offset << 2) & PLL_ADDR) | PLL_WR_EN, par); |
| 38 | /* write the register value */ |
| 39 | aty_st_8(CLOCK_CNTL_DATA, val & PLL_DATA, par); |
| 40 | aty_st_8(CLOCK_CNTL_ADDR, ((offset << 2) & PLL_ADDR) & ~PLL_WR_EN, par); |
| 41 | } |
| 42 | |
| 43 | /* |
| 44 | * by Daniel Mantione |
| 45 | * <daniel.mantione@freepascal.org> |
| 46 | * |
| 47 | * |
| 48 | * ATI Mach64 CT clock synthesis description. |
| 49 | * |
| 50 | * All clocks on the Mach64 can be calculated using the same principle: |
| 51 | * |
| 52 | * XTALIN * x * FB_DIV |
| 53 | * CLK = ---------------------- |
| 54 | * PLL_REF_DIV * POST_DIV |
| 55 | * |
| 56 | * XTALIN is a fixed speed clock. Common speeds are 14.31 MHz and 29.50 MHz. |
| 57 | * PLL_REF_DIV can be set by the user, but is the same for all clocks. |
| 58 | * FB_DIV can be set by the user for each clock individually, it should be set |
| 59 | * between 128 and 255, the chip will generate a bad clock signal for too low |
| 60 | * values. |
| 61 | * x depends on the type of clock; usually it is 2, but for the MCLK it can also |
| 62 | * be set to 4. |
| 63 | * POST_DIV can be set by the user for each clock individually, Possible values |
| 64 | * are 1,2,4,8 and for some clocks other values are available too. |
| 65 | * CLK is of course the clock speed that is generated. |
| 66 | * |
| 67 | * The Mach64 has these clocks: |
| 68 | * |
| 69 | * MCLK The clock rate of the chip |
| 70 | * XCLK The clock rate of the on-chip memory |
| 71 | * VCLK0 First pixel clock of first CRT controller |
| 72 | * VCLK1 Second pixel clock of first CRT controller |
| 73 | * VCLK2 Third pixel clock of first CRT controller |
| 74 | * VCLK3 Fourth pixel clock of first CRT controller |
| 75 | * VCLK Selected pixel clock, one of VCLK0, VCLK1, VCLK2, VCLK3 |
| 76 | * V2CLK Pixel clock of the second CRT controller. |
| 77 | * SCLK Multi-purpose clock |
| 78 | * |
| 79 | * - MCLK and XCLK use the same FB_DIV |
| 80 | * - VCLK0 .. VCLK3 use the same FB_DIV |
| 81 | * - V2CLK is needed when the second CRTC is used (can be used for dualhead); |
| 82 | * i.e. CRT monitor connected to laptop has different resolution than built |
| 83 | * in LCD monitor. |
| 84 | * - SCLK is not available on all cards; it is know to exist on the Rage LT-PRO, |
| 85 | * Rage XL and Rage Mobility. It is know not to exist on the Mach64 VT. |
| 86 | * - V2CLK is not available on all cards, most likely only the Rage LT-PRO, |
| 87 | * the Rage XL and the Rage Mobility |
| 88 | * |
| 89 | * SCLK can be used to: |
| 90 | * - Clock the chip instead of MCLK |
| 91 | * - Replace XTALIN with a user defined frequency |
| 92 | * - Generate the pixel clock for the LCD monitor (instead of VCLK) |
| 93 | */ |
| 94 | |
| 95 | /* |
| 96 | * It can be quite hard to calculate XCLK and MCLK if they don't run at the |
| 97 | * same frequency. Luckily, until now all cards that need asynchrone clock |
| 98 | * speeds seem to have SCLK. |
| 99 | * So this driver uses SCLK to clock the chip and XCLK to clock the memory. |
| 100 | */ |
| 101 | |
| 102 | /* ------------------------------------------------------------------------- */ |
| 103 | |
| 104 | /* |
| 105 | * PLL programming (Mach64 CT family) |
| 106 | * |
| 107 | * |
| 108 | * This procedure sets the display fifo. The display fifo is a buffer that |
| 109 | * contains data read from the video memory that waits to be processed by |
| 110 | * the CRT controller. |
| 111 | * |
| 112 | * On the more modern Mach64 variants, the chip doesn't calculate the |
| 113 | * interval after which the display fifo has to be reloaded from memory |
| 114 | * automatically, the driver has to do it instead. |
| 115 | */ |
| 116 | |
| 117 | #define Maximum_DSP_PRECISION 7 |
| 118 | static u8 postdividers[] = {1,2,4,8,3}; |
| 119 | |
| 120 | static int aty_dsp_gt(const struct fb_info *info, u32 bpp, struct pll_ct *pll) |
| 121 | { |
| 122 | u32 dsp_off, dsp_on, dsp_xclks; |
| 123 | u32 multiplier, divider, ras_multiplier, ras_divider, tmp; |
| 124 | u8 vshift, xshift; |
| 125 | s8 dsp_precision; |
| 126 | |
| 127 | multiplier = ((u32)pll->mclk_fb_div) * pll->vclk_post_div_real; |
| 128 | divider = ((u32)pll->vclk_fb_div) * pll->xclk_ref_div; |
| 129 | |
| 130 | ras_multiplier = pll->xclkmaxrasdelay; |
| 131 | ras_divider = 1; |
| 132 | |
| 133 | if (bpp>=8) |
| 134 | divider = divider * (bpp >> 2); |
| 135 | |
| 136 | vshift = (6 - 2) - pll->xclk_post_div; /* FIFO is 64 bits wide in accelerator mode ... */ |
| 137 | |
| 138 | if (bpp == 0) |
| 139 | vshift--; /* ... but only 32 bits in VGA mode. */ |
| 140 | |
| 141 | #ifdef CONFIG_FB_ATY_GENERIC_LCD |
| 142 | if (pll->xres != 0) { |
| 143 | struct atyfb_par *par = (struct atyfb_par *) info->par; |
| 144 | |
| 145 | multiplier = multiplier * par->lcd_width; |
| 146 | divider = divider * pll->xres & ~7; |
| 147 | |
| 148 | ras_multiplier = ras_multiplier * par->lcd_width; |
| 149 | ras_divider = ras_divider * pll->xres & ~7; |
| 150 | } |
| 151 | #endif |
| 152 | /* If we don't do this, 32 bits for multiplier & divider won't be |
| 153 | enough in certain situations! */ |
| 154 | while (((multiplier | divider) & 1) == 0) { |
| 155 | multiplier = multiplier >> 1; |
| 156 | divider = divider >> 1; |
| 157 | } |
| 158 | |
| 159 | /* Determine DSP precision first */ |
| 160 | tmp = ((multiplier * pll->fifo_size) << vshift) / divider; |
| 161 | |
| 162 | for (dsp_precision = -5; tmp; dsp_precision++) |
| 163 | tmp >>= 1; |
| 164 | if (dsp_precision < 0) |
| 165 | dsp_precision = 0; |
| 166 | else if (dsp_precision > Maximum_DSP_PRECISION) |
| 167 | dsp_precision = Maximum_DSP_PRECISION; |
| 168 | |
| 169 | xshift = 6 - dsp_precision; |
| 170 | vshift += xshift; |
| 171 | |
| 172 | /* Move on to dsp_off */ |
| 173 | dsp_off = ((multiplier * (pll->fifo_size - 1)) << vshift) / divider - |
| 174 | (1 << (vshift - xshift)); |
| 175 | |
| 176 | /* if (bpp == 0) |
| 177 | dsp_on = ((multiplier * 20 << vshift) + divider) / divider; |
| 178 | else */ |
| 179 | { |
| 180 | dsp_on = ((multiplier << vshift) + divider) / divider; |
| 181 | tmp = ((ras_multiplier << xshift) + ras_divider) / ras_divider; |
| 182 | if (dsp_on < tmp) |
| 183 | dsp_on = tmp; |
| 184 | dsp_on = dsp_on + (tmp * 2) + (pll->xclkpagefaultdelay << xshift); |
| 185 | } |
| 186 | |
| 187 | /* Calculate rounding factor and apply it to dsp_on */ |
| 188 | tmp = ((1 << (Maximum_DSP_PRECISION - dsp_precision)) - 1) >> 1; |
| 189 | dsp_on = ((dsp_on + tmp) / (tmp + 1)) * (tmp + 1); |
| 190 | |
| 191 | if (dsp_on >= ((dsp_off / (tmp + 1)) * (tmp + 1))) { |
| 192 | dsp_on = dsp_off - (multiplier << vshift) / divider; |
| 193 | dsp_on = (dsp_on / (tmp + 1)) * (tmp + 1); |
| 194 | } |
| 195 | |
| 196 | /* Last but not least: dsp_xclks */ |
| 197 | dsp_xclks = ((multiplier << (vshift + 5)) + divider) / divider; |
| 198 | |
| 199 | /* Get register values. */ |
| 200 | pll->dsp_on_off = (dsp_on << 16) + dsp_off; |
| 201 | pll->dsp_config = (dsp_precision << 20) | (pll->dsp_loop_latency << 16) | dsp_xclks; |
| 202 | #ifdef DEBUG |
| 203 | printk("atyfb(%s): dsp_config 0x%08x, dsp_on_off 0x%08x\n", |
Harvey Harrison | 5ae1217 | 2008-04-28 02:15:47 -0700 | [diff] [blame] | 204 | __func__, pll->dsp_config, pll->dsp_on_off); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 205 | #endif |
| 206 | return 0; |
| 207 | } |
| 208 | |
| 209 | static int aty_valid_pll_ct(const struct fb_info *info, u32 vclk_per, struct pll_ct *pll) |
| 210 | { |
| 211 | u32 q; |
| 212 | struct atyfb_par *par = (struct atyfb_par *) info->par; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 213 | int pllvclk; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 214 | |
| 215 | /* FIXME: use the VTB/GTB /{3,6,12} post dividers if they're better suited */ |
| 216 | q = par->ref_clk_per * pll->pll_ref_div * 4 / vclk_per; |
| 217 | if (q < 16*8 || q > 255*8) { |
| 218 | printk(KERN_CRIT "atyfb: vclk out of range\n"); |
| 219 | return -EINVAL; |
| 220 | } else { |
| 221 | pll->vclk_post_div = (q < 128*8); |
| 222 | pll->vclk_post_div += (q < 64*8); |
| 223 | pll->vclk_post_div += (q < 32*8); |
| 224 | } |
| 225 | pll->vclk_post_div_real = postdividers[pll->vclk_post_div]; |
| 226 | // pll->vclk_post_div <<= 6; |
| 227 | pll->vclk_fb_div = q * pll->vclk_post_div_real / 8; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 228 | pllvclk = (1000000 * 2 * pll->vclk_fb_div) / |
| 229 | (par->ref_clk_per * pll->pll_ref_div); |
Ville Syrjälä | 25163c5 | 2006-01-09 20:53:27 -0800 | [diff] [blame] | 230 | #ifdef DEBUG |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 231 | printk("atyfb(%s): pllvclk=%d MHz, vclk=%d MHz\n", |
Harvey Harrison | 5ae1217 | 2008-04-28 02:15:47 -0700 | [diff] [blame] | 232 | __func__, pllvclk, pllvclk / pll->vclk_post_div_real); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 233 | #endif |
| 234 | pll->pll_vclk_cntl = 0x03; /* VCLK = PLL_VCLK/VCLKx_POST */ |
Ville Syrjälä | 25163c5 | 2006-01-09 20:53:27 -0800 | [diff] [blame] | 235 | |
| 236 | /* Set ECP (scaler/overlay clock) divider */ |
| 237 | if (par->pll_limits.ecp_max) { |
| 238 | int ecp = pllvclk / pll->vclk_post_div_real; |
| 239 | int ecp_div = 0; |
| 240 | |
| 241 | while (ecp > par->pll_limits.ecp_max && ecp_div < 2) { |
| 242 | ecp >>= 1; |
| 243 | ecp_div++; |
| 244 | } |
| 245 | pll->pll_vclk_cntl |= ecp_div << 4; |
| 246 | } |
| 247 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 248 | return 0; |
| 249 | } |
| 250 | |
| 251 | static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll) |
| 252 | { |
| 253 | struct atyfb_par *par = (struct atyfb_par *) info->par; |
| 254 | int err; |
| 255 | |
| 256 | if ((err = aty_valid_pll_ct(info, vclk_per, &pll->ct))) |
| 257 | return err; |
| 258 | if (M64_HAS(GTB_DSP) && (err = aty_dsp_gt(info, bpp, &pll->ct))) |
| 259 | return err; |
| 260 | /*aty_calc_pll_ct(info, &pll->ct);*/ |
| 261 | return 0; |
| 262 | } |
| 263 | |
| 264 | static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll) |
| 265 | { |
| 266 | struct atyfb_par *par = (struct atyfb_par *) info->par; |
| 267 | u32 ret; |
| 268 | ret = par->ref_clk_per * pll->ct.pll_ref_div * pll->ct.vclk_post_div_real / pll->ct.vclk_fb_div / 2; |
| 269 | #ifdef CONFIG_FB_ATY_GENERIC_LCD |
| 270 | if(pll->ct.xres > 0) { |
| 271 | ret *= par->lcd_width; |
| 272 | ret /= pll->ct.xres; |
| 273 | } |
| 274 | #endif |
| 275 | #ifdef DEBUG |
Harvey Harrison | 5ae1217 | 2008-04-28 02:15:47 -0700 | [diff] [blame] | 276 | printk("atyfb(%s): calculated 0x%08X(%i)\n", __func__, ret, ret); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 277 | #endif |
| 278 | return ret; |
| 279 | } |
| 280 | |
| 281 | void aty_set_pll_ct(const struct fb_info *info, const union aty_pll *pll) |
| 282 | { |
| 283 | struct atyfb_par *par = (struct atyfb_par *) info->par; |
| 284 | u32 crtc_gen_cntl, lcd_gen_cntrl; |
| 285 | u8 tmp, tmp2; |
| 286 | |
| 287 | lcd_gen_cntrl = 0; |
| 288 | #ifdef DEBUG |
| 289 | printk("atyfb(%s): about to program:\n" |
| 290 | "pll_ext_cntl=0x%02x pll_gen_cntl=0x%02x pll_vclk_cntl=0x%02x\n", |
Harvey Harrison | 5ae1217 | 2008-04-28 02:15:47 -0700 | [diff] [blame] | 291 | __func__, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 292 | pll->ct.pll_ext_cntl, pll->ct.pll_gen_cntl, pll->ct.pll_vclk_cntl); |
| 293 | |
| 294 | printk("atyfb(%s): setting clock %lu for FeedBackDivider %i, ReferenceDivider %i, PostDivider %i(%i)\n", |
Harvey Harrison | 5ae1217 | 2008-04-28 02:15:47 -0700 | [diff] [blame] | 295 | __func__, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 296 | par->clk_wr_offset, pll->ct.vclk_fb_div, |
| 297 | pll->ct.pll_ref_div, pll->ct.vclk_post_div, pll->ct.vclk_post_div_real); |
| 298 | #endif |
| 299 | #ifdef CONFIG_FB_ATY_GENERIC_LCD |
| 300 | if (par->lcd_table != 0) { |
| 301 | /* turn off LCD */ |
| 302 | lcd_gen_cntrl = aty_ld_lcd(LCD_GEN_CNTL, par); |
| 303 | aty_st_lcd(LCD_GEN_CNTL, lcd_gen_cntrl & ~LCD_ON, par); |
| 304 | } |
| 305 | #endif |
| 306 | aty_st_8(CLOCK_CNTL, par->clk_wr_offset | CLOCK_STROBE, par); |
| 307 | |
| 308 | /* Temporarily switch to accelerator mode */ |
| 309 | crtc_gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par); |
| 310 | if (!(crtc_gen_cntl & CRTC_EXT_DISP_EN)) |
| 311 | aty_st_le32(CRTC_GEN_CNTL, crtc_gen_cntl | CRTC_EXT_DISP_EN, par); |
| 312 | |
| 313 | /* Reset VCLK generator */ |
| 314 | aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par); |
| 315 | |
| 316 | /* Set post-divider */ |
| 317 | tmp2 = par->clk_wr_offset << 1; |
| 318 | tmp = aty_ld_pll_ct(VCLK_POST_DIV, par); |
| 319 | tmp &= ~(0x03U << tmp2); |
| 320 | tmp |= ((pll->ct.vclk_post_div & 0x03U) << tmp2); |
| 321 | aty_st_pll_ct(VCLK_POST_DIV, tmp, par); |
| 322 | |
| 323 | /* Set extended post-divider */ |
| 324 | tmp = aty_ld_pll_ct(PLL_EXT_CNTL, par); |
| 325 | tmp &= ~(0x10U << par->clk_wr_offset); |
| 326 | tmp &= 0xF0U; |
| 327 | tmp |= pll->ct.pll_ext_cntl; |
| 328 | aty_st_pll_ct(PLL_EXT_CNTL, tmp, par); |
| 329 | |
| 330 | /* Set feedback divider */ |
| 331 | tmp = VCLK0_FB_DIV + par->clk_wr_offset; |
| 332 | aty_st_pll_ct(tmp, (pll->ct.vclk_fb_div & 0xFFU), par); |
| 333 | |
| 334 | aty_st_pll_ct(PLL_GEN_CNTL, (pll->ct.pll_gen_cntl & (~(PLL_OVERRIDE | PLL_MCLK_RST))) | OSC_EN, par); |
| 335 | |
| 336 | /* End VCLK generator reset */ |
| 337 | aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl & ~(PLL_VCLK_RST), par); |
| 338 | mdelay(5); |
| 339 | |
| 340 | aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par); |
| 341 | aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par); |
| 342 | mdelay(1); |
| 343 | |
| 344 | /* Restore mode register */ |
| 345 | if (!(crtc_gen_cntl & CRTC_EXT_DISP_EN)) |
| 346 | aty_st_le32(CRTC_GEN_CNTL, crtc_gen_cntl, par); |
| 347 | |
| 348 | if (M64_HAS(GTB_DSP)) { |
| 349 | u8 dll_cntl; |
| 350 | |
| 351 | if (M64_HAS(XL_DLL)) |
| 352 | dll_cntl = 0x80; |
| 353 | else if (par->ram_type >= SDRAM) |
| 354 | dll_cntl = 0xa6; |
| 355 | else |
| 356 | dll_cntl = 0xa0; |
| 357 | aty_st_pll_ct(DLL_CNTL, dll_cntl, par); |
| 358 | aty_st_pll_ct(VFC_CNTL, 0x1b, par); |
| 359 | aty_st_le32(DSP_CONFIG, pll->ct.dsp_config, par); |
| 360 | aty_st_le32(DSP_ON_OFF, pll->ct.dsp_on_off, par); |
| 361 | |
| 362 | mdelay(10); |
| 363 | aty_st_pll_ct(DLL_CNTL, dll_cntl, par); |
| 364 | mdelay(10); |
| 365 | aty_st_pll_ct(DLL_CNTL, dll_cntl | 0x40, par); |
| 366 | mdelay(10); |
| 367 | aty_st_pll_ct(DLL_CNTL, dll_cntl & ~0x40, par); |
| 368 | } |
| 369 | #ifdef CONFIG_FB_ATY_GENERIC_LCD |
| 370 | if (par->lcd_table != 0) { |
| 371 | /* restore LCD */ |
| 372 | aty_st_lcd(LCD_GEN_CNTL, lcd_gen_cntrl, par); |
| 373 | } |
| 374 | #endif |
| 375 | } |
| 376 | |
Greg Kroah-Hartman | 48c68c4 | 2012-12-21 13:07:39 -0800 | [diff] [blame] | 377 | static void aty_get_pll_ct(const struct fb_info *info, union aty_pll *pll) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 378 | { |
| 379 | struct atyfb_par *par = (struct atyfb_par *) info->par; |
| 380 | u8 tmp, clock; |
| 381 | |
| 382 | clock = aty_ld_8(CLOCK_CNTL, par) & 0x03U; |
| 383 | tmp = clock << 1; |
| 384 | pll->ct.vclk_post_div = (aty_ld_pll_ct(VCLK_POST_DIV, par) >> tmp) & 0x03U; |
| 385 | |
| 386 | pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par) & 0x0FU; |
| 387 | pll->ct.vclk_fb_div = aty_ld_pll_ct(VCLK0_FB_DIV + clock, par) & 0xFFU; |
| 388 | pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par); |
| 389 | pll->ct.mclk_fb_div = aty_ld_pll_ct(MCLK_FB_DIV, par); |
| 390 | |
| 391 | pll->ct.pll_gen_cntl = aty_ld_pll_ct(PLL_GEN_CNTL, par); |
| 392 | pll->ct.pll_vclk_cntl = aty_ld_pll_ct(PLL_VCLK_CNTL, par); |
| 393 | |
| 394 | if (M64_HAS(GTB_DSP)) { |
| 395 | pll->ct.dsp_config = aty_ld_le32(DSP_CONFIG, par); |
| 396 | pll->ct.dsp_on_off = aty_ld_le32(DSP_ON_OFF, par); |
| 397 | } |
| 398 | } |
| 399 | |
Greg Kroah-Hartman | 48c68c4 | 2012-12-21 13:07:39 -0800 | [diff] [blame] | 400 | static int aty_init_pll_ct(const struct fb_info *info, union aty_pll *pll) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 401 | { |
| 402 | struct atyfb_par *par = (struct atyfb_par *) info->par; |
Ville Syrjala | efc08a7 | 2006-12-08 02:40:45 -0800 | [diff] [blame] | 403 | u8 mpost_div, xpost_div, sclk_post_div_real; |
| 404 | u32 q, memcntl, trp; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 405 | u32 dsp_config, dsp_on_off, vga_dsp_config, vga_dsp_on_off; |
| 406 | #ifdef DEBUG |
| 407 | int pllmclk, pllsclk; |
| 408 | #endif |
| 409 | pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par); |
| 410 | pll->ct.xclk_post_div = pll->ct.pll_ext_cntl & 0x07; |
| 411 | pll->ct.xclk_ref_div = 1; |
| 412 | switch (pll->ct.xclk_post_div) { |
| 413 | case 0: case 1: case 2: case 3: |
| 414 | break; |
| 415 | |
| 416 | case 4: |
| 417 | pll->ct.xclk_ref_div = 3; |
| 418 | pll->ct.xclk_post_div = 0; |
| 419 | break; |
| 420 | |
| 421 | default: |
| 422 | printk(KERN_CRIT "atyfb: Unsupported xclk source: %d.\n", pll->ct.xclk_post_div); |
| 423 | return -EINVAL; |
| 424 | } |
| 425 | pll->ct.mclk_fb_mult = 2; |
| 426 | if(pll->ct.pll_ext_cntl & PLL_MFB_TIMES_4_2B) { |
| 427 | pll->ct.mclk_fb_mult = 4; |
| 428 | pll->ct.xclk_post_div -= 1; |
| 429 | } |
| 430 | |
| 431 | #ifdef DEBUG |
| 432 | printk("atyfb(%s): mclk_fb_mult=%d, xclk_post_div=%d\n", |
Harvey Harrison | 5ae1217 | 2008-04-28 02:15:47 -0700 | [diff] [blame] | 433 | __func__, pll->ct.mclk_fb_mult, pll->ct.xclk_post_div); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 434 | #endif |
| 435 | |
| 436 | memcntl = aty_ld_le32(MEM_CNTL, par); |
| 437 | trp = (memcntl & 0x300) >> 8; |
| 438 | |
| 439 | pll->ct.xclkpagefaultdelay = ((memcntl & 0xc00) >> 10) + ((memcntl & 0x1000) >> 12) + trp + 2; |
| 440 | pll->ct.xclkmaxrasdelay = ((memcntl & 0x70000) >> 16) + trp + 2; |
| 441 | |
| 442 | if (M64_HAS(FIFO_32)) { |
| 443 | pll->ct.fifo_size = 32; |
| 444 | } else { |
| 445 | pll->ct.fifo_size = 24; |
| 446 | pll->ct.xclkpagefaultdelay += 2; |
| 447 | pll->ct.xclkmaxrasdelay += 3; |
| 448 | } |
| 449 | |
| 450 | switch (par->ram_type) { |
| 451 | case DRAM: |
| 452 | if (info->fix.smem_len<=ONE_MB) { |
| 453 | pll->ct.dsp_loop_latency = 10; |
| 454 | } else { |
| 455 | pll->ct.dsp_loop_latency = 8; |
| 456 | pll->ct.xclkpagefaultdelay += 2; |
| 457 | } |
| 458 | break; |
| 459 | case EDO: |
| 460 | case PSEUDO_EDO: |
| 461 | if (info->fix.smem_len<=ONE_MB) { |
| 462 | pll->ct.dsp_loop_latency = 9; |
| 463 | } else { |
| 464 | pll->ct.dsp_loop_latency = 8; |
| 465 | pll->ct.xclkpagefaultdelay += 1; |
| 466 | } |
| 467 | break; |
| 468 | case SDRAM: |
| 469 | if (info->fix.smem_len<=ONE_MB) { |
| 470 | pll->ct.dsp_loop_latency = 11; |
| 471 | } else { |
| 472 | pll->ct.dsp_loop_latency = 10; |
| 473 | pll->ct.xclkpagefaultdelay += 1; |
| 474 | } |
| 475 | break; |
| 476 | case SGRAM: |
| 477 | pll->ct.dsp_loop_latency = 8; |
| 478 | pll->ct.xclkpagefaultdelay += 3; |
| 479 | break; |
| 480 | default: |
| 481 | pll->ct.dsp_loop_latency = 11; |
| 482 | pll->ct.xclkpagefaultdelay += 3; |
| 483 | break; |
| 484 | } |
| 485 | |
| 486 | if (pll->ct.xclkmaxrasdelay <= pll->ct.xclkpagefaultdelay) |
| 487 | pll->ct.xclkmaxrasdelay = pll->ct.xclkpagefaultdelay + 1; |
| 488 | |
| 489 | /* Allow BIOS to override */ |
| 490 | dsp_config = aty_ld_le32(DSP_CONFIG, par); |
| 491 | dsp_on_off = aty_ld_le32(DSP_ON_OFF, par); |
| 492 | vga_dsp_config = aty_ld_le32(VGA_DSP_CONFIG, par); |
| 493 | vga_dsp_on_off = aty_ld_le32(VGA_DSP_ON_OFF, par); |
| 494 | |
| 495 | if (dsp_config) |
| 496 | pll->ct.dsp_loop_latency = (dsp_config & DSP_LOOP_LATENCY) >> 16; |
| 497 | #if 0 |
| 498 | FIXME: is it relevant for us? |
| 499 | if ((!dsp_on_off && !M64_HAS(RESET_3D)) || |
| 500 | ((dsp_on_off == vga_dsp_on_off) && |
| 501 | (!dsp_config || !((dsp_config ^ vga_dsp_config) & DSP_XCLKS_PER_QW)))) { |
| 502 | vga_dsp_on_off &= VGA_DSP_OFF; |
| 503 | vga_dsp_config &= VGA_DSP_XCLKS_PER_QW; |
| 504 | if (ATIDivide(vga_dsp_on_off, vga_dsp_config, 5, 1) > 24) |
| 505 | pll->ct.fifo_size = 32; |
| 506 | else |
| 507 | pll->ct.fifo_size = 24; |
| 508 | } |
| 509 | #endif |
| 510 | /* Exit if the user does not want us to tamper with the clock |
| 511 | rates of her chip. */ |
| 512 | if (par->mclk_per == 0) { |
| 513 | u8 mclk_fb_div, pll_ext_cntl; |
| 514 | pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par); |
| 515 | pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par); |
| 516 | pll->ct.xclk_post_div_real = postdividers[pll_ext_cntl & 0x07]; |
| 517 | mclk_fb_div = aty_ld_pll_ct(MCLK_FB_DIV, par); |
| 518 | if (pll_ext_cntl & PLL_MFB_TIMES_4_2B) |
| 519 | mclk_fb_div <<= 1; |
| 520 | pll->ct.mclk_fb_div = mclk_fb_div; |
| 521 | return 0; |
| 522 | } |
| 523 | |
| 524 | pll->ct.pll_ref_div = par->pll_per * 2 * 255 / par->ref_clk_per; |
| 525 | |
| 526 | /* FIXME: use the VTB/GTB /3 post divider if it's better suited */ |
| 527 | q = par->ref_clk_per * pll->ct.pll_ref_div * 8 / |
| 528 | (pll->ct.mclk_fb_mult * par->xclk_per); |
| 529 | |
| 530 | if (q < 16*8 || q > 255*8) { |
| 531 | printk(KERN_CRIT "atxfb: xclk out of range\n"); |
| 532 | return -EINVAL; |
| 533 | } else { |
| 534 | xpost_div = (q < 128*8); |
| 535 | xpost_div += (q < 64*8); |
| 536 | xpost_div += (q < 32*8); |
| 537 | } |
| 538 | pll->ct.xclk_post_div_real = postdividers[xpost_div]; |
| 539 | pll->ct.mclk_fb_div = q * pll->ct.xclk_post_div_real / 8; |
| 540 | |
Risto Suominen | 7fbb7ca | 2009-01-13 20:09:30 +0000 | [diff] [blame] | 541 | #ifdef CONFIG_PPC |
| 542 | if (machine_is(powermac)) { |
| 543 | /* Override PLL_EXT_CNTL & 0x07. */ |
| 544 | pll->ct.xclk_post_div = xpost_div; |
| 545 | pll->ct.xclk_ref_div = 1; |
| 546 | } |
| 547 | #endif |
| 548 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 549 | #ifdef DEBUG |
| 550 | pllmclk = (1000000 * pll->ct.mclk_fb_mult * pll->ct.mclk_fb_div) / |
| 551 | (par->ref_clk_per * pll->ct.pll_ref_div); |
| 552 | printk("atyfb(%s): pllmclk=%d MHz, xclk=%d MHz\n", |
Harvey Harrison | 5ae1217 | 2008-04-28 02:15:47 -0700 | [diff] [blame] | 553 | __func__, pllmclk, pllmclk / pll->ct.xclk_post_div_real); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 554 | #endif |
| 555 | |
| 556 | if (M64_HAS(SDRAM_MAGIC_PLL) && (par->ram_type >= SDRAM)) |
| 557 | pll->ct.pll_gen_cntl = OSC_EN; |
| 558 | else |
| 559 | pll->ct.pll_gen_cntl = OSC_EN | DLL_PWDN /* | FORCE_DCLK_TRI_STATE */; |
| 560 | |
| 561 | if (M64_HAS(MAGIC_POSTDIV)) |
| 562 | pll->ct.pll_ext_cntl = 0; |
| 563 | else |
| 564 | pll->ct.pll_ext_cntl = xpost_div; |
| 565 | |
| 566 | if (pll->ct.mclk_fb_mult == 4) |
| 567 | pll->ct.pll_ext_cntl |= PLL_MFB_TIMES_4_2B; |
| 568 | |
| 569 | if (par->mclk_per == par->xclk_per) { |
| 570 | pll->ct.pll_gen_cntl |= (xpost_div << 4); /* mclk == xclk */ |
| 571 | } else { |
| 572 | /* |
| 573 | * The chip clock is not equal to the memory clock. |
| 574 | * Therefore we will use sclk to clock the chip. |
| 575 | */ |
| 576 | pll->ct.pll_gen_cntl |= (6 << 4); /* mclk == sclk */ |
| 577 | |
| 578 | q = par->ref_clk_per * pll->ct.pll_ref_div * 4 / par->mclk_per; |
| 579 | if (q < 16*8 || q > 255*8) { |
| 580 | printk(KERN_CRIT "atyfb: mclk out of range\n"); |
| 581 | return -EINVAL; |
| 582 | } else { |
| 583 | mpost_div = (q < 128*8); |
| 584 | mpost_div += (q < 64*8); |
| 585 | mpost_div += (q < 32*8); |
| 586 | } |
| 587 | sclk_post_div_real = postdividers[mpost_div]; |
Ville Syrjala | efc08a7 | 2006-12-08 02:40:45 -0800 | [diff] [blame] | 588 | pll->ct.sclk_fb_div = q * sclk_post_div_real / 8; |
| 589 | pll->ct.spll_cntl2 = mpost_div << 4; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 590 | #ifdef DEBUG |
Ville Syrjala | efc08a7 | 2006-12-08 02:40:45 -0800 | [diff] [blame] | 591 | pllsclk = (1000000 * 2 * pll->ct.sclk_fb_div) / |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 592 | (par->ref_clk_per * pll->ct.pll_ref_div); |
| 593 | printk("atyfb(%s): use sclk, pllsclk=%d MHz, sclk=mclk=%d MHz\n", |
Harvey Harrison | 5ae1217 | 2008-04-28 02:15:47 -0700 | [diff] [blame] | 594 | __func__, pllsclk, pllsclk / sclk_post_div_real); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 595 | #endif |
Ville Syrjala | efc08a7 | 2006-12-08 02:40:45 -0800 | [diff] [blame] | 596 | } |
| 597 | |
| 598 | /* Disable the extra precision pixel clock controls since we do not use them. */ |
| 599 | pll->ct.ext_vpll_cntl = aty_ld_pll_ct(EXT_VPLL_CNTL, par); |
| 600 | pll->ct.ext_vpll_cntl &= ~(EXT_VPLL_EN | EXT_VPLL_VGA_EN | EXT_VPLL_INSYNC); |
| 601 | |
| 602 | return 0; |
| 603 | } |
| 604 | |
| 605 | static void aty_resume_pll_ct(const struct fb_info *info, |
| 606 | union aty_pll *pll) |
| 607 | { |
| 608 | struct atyfb_par *par = info->par; |
| 609 | |
| 610 | if (par->mclk_per != par->xclk_per) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 611 | /* |
| 612 | * This disables the sclk, crashes the computer as reported: |
| 613 | * aty_st_pll_ct(SPLL_CNTL2, 3, info); |
| 614 | * |
| 615 | * So it seems the sclk must be enabled before it is used; |
| 616 | * so PLL_GEN_CNTL must be programmed *after* the sclk. |
| 617 | */ |
Ville Syrjala | efc08a7 | 2006-12-08 02:40:45 -0800 | [diff] [blame] | 618 | aty_st_pll_ct(SCLK_FB_DIV, pll->ct.sclk_fb_div, par); |
| 619 | aty_st_pll_ct(SPLL_CNTL2, pll->ct.spll_cntl2, par); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 620 | /* |
Ville Syrjala | 94f45bc | 2007-05-08 00:39:44 -0700 | [diff] [blame] | 621 | * SCLK has been started. Wait for the PLL to lock. 5 ms |
| 622 | * should be enough according to mach64 programmer's guide. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 623 | */ |
Ville Syrjala | 94f45bc | 2007-05-08 00:39:44 -0700 | [diff] [blame] | 624 | mdelay(5); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 625 | } |
| 626 | |
| 627 | aty_st_pll_ct(PLL_REF_DIV, pll->ct.pll_ref_div, par); |
| 628 | aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par); |
| 629 | aty_st_pll_ct(MCLK_FB_DIV, pll->ct.mclk_fb_div, par); |
| 630 | aty_st_pll_ct(PLL_EXT_CNTL, pll->ct.pll_ext_cntl, par); |
Ville Syrjala | efc08a7 | 2006-12-08 02:40:45 -0800 | [diff] [blame] | 631 | aty_st_pll_ct(EXT_VPLL_CNTL, pll->ct.ext_vpll_cntl, par); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 632 | } |
| 633 | |
| 634 | static int dummy(void) |
| 635 | { |
| 636 | return 0; |
| 637 | } |
| 638 | |
| 639 | const struct aty_dac_ops aty_dac_ct = { |
| 640 | .set_dac = (void *) dummy, |
| 641 | }; |
| 642 | |
| 643 | const struct aty_pll_ops aty_pll_ct = { |
| 644 | .var_to_pll = aty_var_to_pll_ct, |
| 645 | .pll_to_var = aty_pll_to_var_ct, |
| 646 | .set_pll = aty_set_pll_ct, |
| 647 | .get_pll = aty_get_pll_ct, |
Ville Syrjala | efc08a7 | 2006-12-08 02:40:45 -0800 | [diff] [blame] | 648 | .init_pll = aty_init_pll_ct, |
| 649 | .resume_pll = aty_resume_pll_ct, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 650 | }; |